1304478 九、發明說明： 【發明所屬之技術領域】 • 本發明涉及一種印刷電路板設計完整性檢查的 及方法，尤指一種訊號線的參考平面完整性的檢查系統及 方法。 【先前技術】 印刷電路板（Printing Circuit Board，PCB)是電子産 品中電路元件的支撐件，它提供了電路元件和元件之間的 電氣連接。其將零件與零件之間複雜的電路銅線，經過細 緻整齊的規劃後，蝕刻在一塊板子上，提供電子零元件在 安裝與互連時的主要支撐體，是所有電子産品不可或缺的 基礎零件。 印刷電路板是以不導電材料所製成的平板，在此平板 上通常都有設計預鑽孔以安裝晶片和其他電子元件。元件 的孔有助於讓預先定義在板面上印製的金屬路徑以電子方 •式連接起來，將電子元件的接腳穿過PCB後，再以導電性 的金屬焊條黏附在PCB上而形成電路。 依其應用領域，PCB可分爲單面板、雙面板、四層板 以上多層板及軟板。-般而言，電子產品功能越複雜、回 路距離越長、接點腳數越多，PCB所需層數亦越多，如高 W費1·生電子、貝訊及通訊産品等；而軟板主要應用於需 要彎繞的産品中：如筆記型電腦、照相機、汽車儀鐵等。 隨著印刷電路板上晶片的工作頻率越來越高 ，信號的 上升速度也越來越快。在目前的印刷電路板上，信號頻率 7 13044781304478 IX. Description of the Invention: [Technical Field] The present invention relates to a method and method for inspecting the integrity of a printed circuit board design, and more particularly to an inspection system and method for reference plane integrity of a signal line. [Prior Art] A Printed Circuit Board (PCB) is a support for circuit components in an electronic product that provides electrical connections between circuit components and components. The complex circuit copper wire between the parts and parts is carefully etched and etched on a board to provide the main support for the installation and interconnection of electronic components. It is an indispensable foundation for all electronic products. Components. Printed circuit boards are flat sheets of non-conductive material on which the pre-drilled holes are typically designed to mount wafers and other electronic components. The hole of the component helps to connect the metal paths pre-defined on the board surface in an electronic manner, and the pins of the electronic component pass through the PCB, and then adhere to the PCB with a conductive metal electrode. Circuit. Depending on the application area, PCBs can be divided into single-panel, double-panel, multi-layer and multi-layer boards and soft boards. In general, the more complex the functions of electronic products, the longer the loop distance, the more the number of contacts, the more layers the PCB requires, such as the high W fee, the raw electronics, the beixun and the communication products; The board is mainly used in products that need to be bent: such as notebook computers, cameras, car irons, etc. As the operating frequency of the wafer on the printed circuit board gets higher and higher, the signal rises faster and faster. On current printed circuit boards, signal frequency 7 1304478
已經達到10GHz，甚至更古的4nriJ 有幾十皮秒u皮秒=^Γ) 錢的上升時間只 •而對於高速訊號線而言，复该π + 走線下方附近的參考平面（地層m路齡儘量沿著 但由於印刷電路板設計的需要=)流回信號源頭。 應的參考平面，以及參考平面心；：走線會換層並變更對 次過孔，也兮H祕爲+ 子在者分割，並且每經過一 例如速二二、：；流返回路徑就變得更加複雜-些。 電源平面中的連接不同直考千面_如 回雷冷一—a ,、〔电，愿的供電線路部分）時，返 刷電跋;I： & 9、到某些其他的路#流回電源。如此，在印 況，進ίίΓ佈縣構上齡產生返回電流路徑不連續的狀 進而加大兩頻信號電磁場的干擾雜訊。 =刷電路板的設計中，地/電源層提供訊號線相對應 多考平面。爲了避免因爲返回電流路徑的不連續性，而 造成高速信號完整性與高頻電斜擾的問題，設計 限制參考平面的完整性。然則，傳統作法是採用人工檢杳 參=平面的完整性，往往費㈣力，且難以保持—定的二 查品質。就一般佈線軟體而言，僅能提供訊號線結構的= 制及檢查，而無法做參考平面完整性的檢查。 【發明内容】 ，鑒於以上内容，有必要提供一種訊號線參考平面撿杳 系統。該系統包括一個訊號線選擇單元，一個參考平面^ 查單元，一個資料庫及一個顯示單元。所述資料庫存儲= ° U線文件，母一個訊號線文件用於存儲一個印刷電略极1 8 .!3〇4478 的所有訊號線，在該訊號線文件中共用一個匯流排的訊號 線是一個群組，在同一個群組中，所有的訊號線都有相同 的命名字元。所述訊號線選擇單元包括一個訊號線過濾器 及一個訊號線選擇模組，該訊號線過濾器以相同字元爲依 據’將一^固訊號線群組從該訊號線文件中Ί買取出來，該訊 號線選擇模組從所讀取的訊號線群組中選擇待測訊號線。 所述參考平面檢查單元利用所選擇的待測訊號線檢查其所 對應的參考平面的完整性，該檢查待測訊號線所對應參考 B 平面的完整性是透過將該待測訊號線正投影於其所對應的 參考平面上，檢查該投影與參考平面之間的關係，或透過 檢查待測訊號線從晶片接腳出來到換層之間的距離是否過 長以檢查該參考平面是否完整。所述顯示單元用於將上述 參考平面檢查單元所檢查的結果顯示出來。 本發明還φξ：供一種訊號線參考平面檢查方法，該方法 包括如下步驟·透過訊號線選擇單元從資料庫中選擇一個 馨訊號線文件；從該訊號線文件中過濾出欲檢查的訊號線群 組，從該sfU虎線群組中選擇待測的訊號線；選取欲檢查的 項目；針對所選擇的檢查項目，利用參考平面檢查單元對 上述待測訊號線執行參考平面完整性檢查，顯示檢查結 果，同時對不符合完整性的檢查項目做出標記。 任/、中Y欲檢查的項目包括：檢查待測訊號線的參考平 面是否連續、檢查待測訊號線是否跨越參考平面、檢查待 測訊號線從晶片接腳出來到換層前所走線的長度是科於 所設定的最大長度限制及檢查待測訊號線與其參考平面的 9 1304478 - 間隙是否太過接近。 •利用本發明提供的訊號線參考平面檢查系統及方 渗，可進行印刷電路板上每一個訊號線所對應參考平面的 完整性檢查，進而有效控制返回電流路徑的連續性，使信 5虎Π口質與電磁相容以滿足印刷電路板的設計需求。 【實施方式】 參閱圖1所不，爲本發明訊號線參考平面檢查系統較 佳實施例的70件結構圖。該訊號線參考平面檢查系統工包括 籲：個訊㈣選擇單元5，-個參考平面檢查單元3，一個顯 示單元4，一個報表産生單元7，一個資料庫6。 其中，該資料庫6用於存儲訊號線文件。在該資料庫6 中’每4gIPCB板上的所有訊號線存儲在同一個訊號線文 件中；在該訊號線文件中，共用一個匯流排（Bus)的訊 唬線是一個群組；在同一群組中，所有的訊號線都有相同 的命名字元。 φ 訊號線選擇單元5包括一個訊號線過濾器50，一個訊 號線選擇模組51。其中，該訊號線過濾器5〇以相同字元爲 依據，將訊號線群組從訊號線文件中讀取出來。訊號線選 擇核組51用於從所項取的訊號線群組中選擇待測訊號線。 參考平面檢查單元3用於利用所選擇的待測訊號線檢 查該待測訊號線所對應參考平面的完整性。在本較佳實施 例中，該檢查參考平面完整性是透過將所選擇的待測訊號 線正投影在其所對應的參考平面上，檢查該投影與參考平 面之間的關係，或透過檢查待測訊號線的從晶片接腳出來 χ3〇4478 多ij換層之間的距離是否過長（BreakOut)以檢查該參考平 面是否完整，以避免參考平面的不完整性所造成較大的返 淨電流，進而産生更大的電感效應。該透過檢查投影與參 考乎面之間的關係進行完整性檢查包括：（1)檢查參考平 面是否保持連續性（Continue) ; (2)檢查訊號線是否跨越 間隊，造成某部分線段缺乏參考平面（CrossMoat) ; ( 3 ) 檢查訊號線與參考平面邊界之間的距離（MoatDist)。其中 戶斤述的參考平面爲距離訊號線最近的平面，可以是地声或 電源層。 其中’對Continue的檢查，是將訊號線正投影在所對 應的參考平面上，檢查該投影所經過的參考平面是否皆爲 同〆平面名稱，若參考至兩個以上的不同參考平面，則判 斷爲Fail。 對CrossMoat的檢查，是將該訊號線正投影於所對應 參考平面，檢查該投影是否與該參考平面切割線有重^Has reached 10GHz, even the older 4nriJ has tens of picoseconds u picoseconds = ^ Γ) The rise time of money only • For high-speed signal lines, the reference plane near the bottom of the π + trace (the formation m road) Age as far as possible but due to the need for printed circuit board design =) flow back to the source. The reference plane, and the reference plane; the trace will change layers and change the secondary via, and the 秘H secret is + sub-divided, and each time passes, for example, speed 22::; It's more complicated - some. The connection in the power plane is different from the direct test of thousands of faces _ such as back to the cold one - a,, [electric, willing power supply line part), return to brush; I: & 9, to some other road #流Return to the power supply. In this way, in the printing condition, the age of the returning current path is discontinuous, and the interference noise of the electromagnetic field of the two-frequency signal is increased. = In the design of the brush board, the ground/power layer provides the signal line corresponding to the multi-test plane. In order to avoid the problem of high-speed signal integrity and high-frequency electrical skew due to the discontinuity of the return current path, the design limits the integrity of the reference plane. However, the traditional practice is to use manual inspection of the integrity of the reference = plane, often cost (four) force, and difficult to maintain - the quality of the two checks. As far as the general wiring software is concerned, only the system and the inspection of the signal line structure can be provided, and the reference plane integrity check cannot be performed. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a signal line reference plane system. The system includes a signal line selection unit, a reference plane, a database, and a display unit. The data library storage = ° U line file, the parent one signal line file is used to store all the signal lines of a printing power slightly 8 8 .! 3 〇 4478, and the signal line sharing a bus bar in the signal line file is A group, in the same group, all signal lines have the same named characters. The signal line selection unit includes a signal line filter and a signal line selection module. The signal line filter is based on the same character, and the group of the fixed signal line is bought and retrieved from the signal line file. The signal line selection module selects a signal line to be tested from the group of signal lines read. The reference plane inspection unit checks the integrity of the reference plane corresponding to the signal line to be tested by using the selected signal line to be tested. The integrity of the reference plane B corresponding to the signal line to be tested is determined by orthographically projecting the signal line to be tested. On the corresponding reference plane, check the relationship between the projection and the reference plane, or check whether the reference plane is complete by checking whether the distance between the signal line and the layer to be tested is too long. The display unit is configured to display the result checked by the reference plane inspection unit. The invention also provides a signal line reference plane inspection method, the method comprising the steps of: selecting a sensible line file from the database through the signal line selection unit; filtering the signal line group to be checked from the signal line file The group selects the signal line to be tested from the sfU tiger line group; selects the item to be inspected; and performs a reference plane integrity check on the signal line to be tested by using the reference plane inspection unit for the selected inspection item, and displays the check As a result, the inspection items that are not in conformity are marked at the same time. The items to be checked by /, Y, and Y include: checking whether the reference plane of the signal line to be tested is continuous, checking whether the signal line to be tested crosses the reference plane, and checking the line of the signal to be tested from the chip pin to the line before the layer change. The length is based on the set maximum length limit and checks the signal line to be tested with its reference plane 9 1304478 - if the gap is too close. The signal line reference plane inspection system and the square leakage provided by the invention can perform integrity check on the reference plane corresponding to each signal line on the printed circuit board, thereby effectively controlling the continuity of the return current path, so as to effectively control the continuity of the return current path. The mouth is electromagnetically compatible to meet the design requirements of printed circuit boards. [Embodiment] Referring to Figure 1, there is shown a structural diagram of 70 pieces of a preferred embodiment of the signal line reference plane inspection system of the present invention. The signal line reference plane inspection system includes: a message (4) selection unit 5, a reference plane inspection unit 3, a display unit 4, a report generation unit 7, and a database 6. The database 6 is used to store signal line files. In the database 6, 'every signal line on every 4gI PCB board is stored in the same signal line file; in the signal line file, the signal line sharing a bus is a group; in the same group In the group, all signal lines have the same named character. The φ signal line selecting unit 5 includes a signal line filter 50 and a signal line selecting module 51. The signal line filter 5 读取 reads the signal line group from the signal line file based on the same character. The signal line selection core group 51 is used to select a signal line to be tested from the group of signal lines taken. The reference plane inspection unit 3 is configured to check the integrity of the reference plane corresponding to the signal line to be tested by using the selected signal line to be tested. In the preferred embodiment, the inspection reference plane integrity is performed by examining the selected signal line to be tested on its corresponding reference plane, checking the relationship between the projection and the reference plane, or The distance between the signal line and the chip pin is 〇3〇4478. The distance between the layers is too long (BreakOut) to check whether the reference plane is complete to avoid the large return current caused by the incompleteness of the reference plane. , which in turn produces a greater inductance effect. The integrity check by checking the relationship between the projection and the reference surface includes: (1) checking whether the reference plane maintains continuity; (2) checking whether the signal line crosses the inter-team, causing a certain portion of the line segment lacking a reference plane (CrossMoat) ; ( 3 ) Check the distance between the signal line and the reference plane boundary (MoatDist). The reference plane of the user is the plane closest to the signal line, which can be a ground or power layer. The check for Continue is to project the signal line on the corresponding reference plane, and check whether the reference planes passing through the projection are all the same plane name. If referring to more than two different reference planes, judge For Fail. The inspection of CrossMoat is to project the signal line to the corresponding reference plane, and check whether the projection has a weight with the reference plane cutting line.
部分，若有重疊則表示該訊號線有跨越參考平面 將判定爲Fail。 對Moat胸的檢查，是將該訊號線正投影 參考平面，檢查該投影與該參考平面切割線之間的距離 否大於所設定的最小輯限制，若小於所限定的距] 不該訊號線與該參考平面的間隙太過接近， 、、、 電流路徑被迫截去部分面積，將判定爲邮。^成^丨 =離:制需遵·Rule，該_訊號線至參二: 垂直南度的3倍，以目前PCB設計而言，h會介於 11 1304478 (1H)到9〜18mils (3H)之間。 •對Breakout的檢查，是以該實際訊號線爲準，檢查該 斛號線從晶片接腳出來到換層前所走線的長度是否有小於 所设疋的隶大長度限制，若大於所設定的長度則將判定爲 Fail。在本較佳實施例中，對該檢查提供5個最大長度限制 值，分別爲 lOOmils，200mils，300mils，500mils及lOOOmils， 其中，lmils等於千分之一英寸，該值是可擴充的，還可以 為800mils及1500mils，最常見的長度限制爲500mils。 顯示單元4用於將參考平面檢查單元3所檢查的結果 顯示出來。報表産生單元7用於將檢查結果以報表形式輪 出。該檢查報表包括每一個訊號線所對應參考平面的檢查 結果及每一個訊號線各個線段長度的列表，以提供整個訊 號線群組的檢查比對。 參閱圖2所示，爲本發明訊號線參考平面檢查系統較 佳實施例的介面圖。在該介面圖中，區域25是顯示訊號線 _ 過濾器以相同字元爲依據，從資料庫6中的訊號線文件中過 濾出一個訊號線群組，如以相同字進行過濾。 區域22是檢查項目選定區域，在該區域22中，有四個可選 擇的檢查項目：Continue，CrossMoat，BreakOut，MoatDist。 區域24表示在進行Break〇ut檢查時，所設定的最大長度限 制。區域23表示在進行MoatDist檢查時，所設定分割的最 小距離限制。區域21是所選擇的訊號線的部分線段顯示區 域。按鈕20是檢查鈕，選擇好訊號線後，點擊該按鈕20， 就可進行所選擇訊號線的參考平面檢查。按鈕26是單一訊 12 1304478 號線報表產生叙，按紐27是全部訊號線報表產生紐，區域 28代表檢查結果顯示區域。 • 參閱圖3所示，爲本發明訊號線參考平面檢查方法較 佳實施例的利用單一訊號線進行檢查的流程圖。步驟 S300 ’從資料庫6中選取一個需檢查的訊號線文件，再由 訊號線過濾器50從該訊號線文件以相同字元爲依據過濾出 需檢查的一個訊號線群組。 步驟S302 ’訊號線選擇模組51從該群組中選擇出一個 待測訊號線。 步驟S304，在檢查項目選定區域22，選擇需要檢查的 項目’該所需要檢查的項目包括·· Continue，CrossMoat， BreakOut，MoatDist。其中，Continue表示檢查參考平面是 否保持連續性；CrossMoat表示檢查訊號線是否跨越間隙， 造成某部分線段缺乏參考平面；]8]|^仏〇111表示檢查訊號線 從晶片接腳出來到換層之間的距離是否過長；厘⑽山以表 示檢查訊號線與參考平面邊界之間的距離。 在該步驟S304中，可以只選擇一個檢查項目 ，也可以 選擇多個。 步驟S306 ’對該訊號線執行參考平面完整性檢查，其 中’，果在步驟S304中選擇的檢查項目是c〇ntinue，則將 該訊號線正投影於所對應的參考平面，檢查該投影所經過 的參考平面是否皆爲同—參考平面名稱，若參考至兩個以 上的不同參考平面則判定爲触，顯示出該檢查結果並將 該檢查選項標示一個錯誤記號； 13 1304478 如果在步驟S3G4中選擇的檢查項目是Cn)ssM()at，則將 Μ訊號線正&景;於所對應的參考平面，檢查該投影是否與 •該參考平面㈣線有重疊的部分，若有重疊則表示該訊號 、線有跨越參考平面的間隙，將判定爲_，顯示出該檢查 結果並將該檢查選項標示—個錯誤記號； 如果在步驟S304中選擇的檢查項目是Break〇ut，則以 2貝際《線爲準，撿查該訊號線從日日日片接腳出來到換層 別所走線的長度是否有]、於區域24所設定的最大長度限 $ ’若大於所設定的長度則將判定爲Fail，以目前設計規 範而a ’此最大長度限制以5〇〇mil_1〇〇〇mils較常見，其 中檢查報表會將該訊號線每個線段的長度表列出， 以方便 確遇訊號線在晶片接腳區域的走線長度，顯示出該檢查結 果並將該檢查選項標示_個錯誤記號； 如果在步驟S304中選擇的檢查項目是MoatDist，則將 該訊號線正投影於所對應的參考平面，檢查該投影與該參 1304478 平1^ ’特別是電源層更需要用切割線來防止不同電源平面 的短路。 ‘ 步驟S308，按照所選擇的檢查項目，將利用該訊號綠 $考平面進行檢查的各項檢查結果由報表産生單元7產 生檢查結果報表。該報表包括該訊號線的參考平面的各個 檢杳 目的檢查結果及該訊號線每個線段的長度列表。 步驟S3l〇，判斷是否還要檢查其他訊號線，如果需 則返回步騍S302選擇下一個待測訊號線，否則結束該 檢查流程。 本發明還可對所選擇的訊號線群組根據所選擇的檢 杳j頁日、 —、 進行抵次檢查參考平面的完整性，該檢查項目可以 同時iPin , 告、谭，也可以只選一個，或同時選擇二個或三個。其 =質還是對每一個訊號線按照所選擇的檢查項目進行撿 —’其檢查方法同利用單一訊號線檢查參考平面一樣進行 檢$，# 〜報表的產生是將該批次所選擇的訊號線的檢查結 、報表方式輪出。顯示單元4會有顯示檢查的進度百分 4見圖4所示，是進行訊號線批次檢查的進度顯示。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明。任何熟悉此項技藝者，在不脫離本發明之精神和 範圍内，當可做更動與潤飾，因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1爲本發明訊號線參考平面檢查系統較佳實施例的 元件結構圖。 15 .1304478 圖2爲本發明訊號線參考平面檢查系統較佳實施例的 介面圖。 圖3爲本發明訊號線參考平面檢查方法較佳實施例的 單一訊號線檢查的流程圖。 圖4爲本發明訊號線參考平面檢查方 次檢查的進度顯示。 乜實施例批 【主要元件符號說明】 訊號線參考平面檢查系統 B 訊號線選擇單元 1 訊號線過濾器 5 訊號線選擇模組 5() 資料庫 51 參考平面檢查單元 6 郎一 S 一 3 顯卓兀 報表產生單元 4 Ί 16In part, if there is overlap, it means that the signal line crosses the reference plane and will be judged as Fail. The inspection of the Moat chest is to orthographically project the reference plane of the signal line, and check whether the distance between the projection and the reference plane cutting line is greater than the set minimum limit, if less than the defined distance], the signal line is not The gap of the reference plane is too close, and the current path is forced to cut off part of the area and will be judged as postal. ^成^丨=Off: System needs to comply with Rule, the _ signal line to the second: 3 times the vertical south, in the current PCB design, h will be between 11 1304478 (1H) to 9~18mils (3H )between. • Check the Breakout based on the actual signal line. Check whether the length of the line from the chip pin to the layer before the layer change is less than the length limit of the set. If it is greater than the set The length will be judged as Fail. In the preferred embodiment, the maximum length limit values are provided for the inspection, which are 100 mils, 200 mils, 300 mils, 500 mils, and 1000 mils, wherein lmils is equal to one thousandth of an inch, and the value is expandable. For 800 mils and 1500 mils, the most common length limit is 500 mils. The display unit 4 is for displaying the result checked by the reference plane inspection unit 3. The report generation unit 7 is for rotating the inspection result in the form of a report. The inspection report includes a check result of the reference plane corresponding to each signal line and a list of the lengths of each line segment of each signal line to provide an inspection comparison of the entire signal line group. Referring to Figure 2, there is shown an interface diagram of a preferred embodiment of the signal line reference plane inspection system of the present invention. In the interface diagram, the area 25 is the display signal line _ filter based on the same character, and a signal line group is filtered from the signal line file in the database 6, for example, filtered by the same word. Area 22 is the inspection item selection area in which there are four optional inspection items: Continue, CrossMoat, BreakOut, MoatDist. Area 24 represents the maximum length limit that is set when performing a Break〇ut check. The area 23 indicates the minimum distance limit of the set division when performing the MoatDist check. The area 21 is a partial line segment display area of the selected signal line. The button 20 is a check button. After selecting the signal line, clicking the button 20 can perform a reference plane check of the selected signal line. The button 26 is a single message 12 1304478 line report generation, button 27 is the all signal line report generation button, and area 28 represents the inspection result display area. • Referring to FIG. 3, a flow chart of a single signal line inspection is a preferred embodiment of the signal line reference plane inspection method of the present invention. Step S300' selects a signal line file to be inspected from the database 6, and then the signal line filter 50 filters out a group of signal lines to be checked from the signal line file based on the same character. Step S302, the signal line selection module 51 selects a signal line to be tested from the group. In step S304, in the inspection item selection area 22, the item to be inspected is selected. The items to be inspected include: Continue, CrossMoat, BreakOut, MoatDist. Among them, Continue means to check whether the reference plane maintains continuity; CrossMoat means to check whether the signal line crosses the gap, causing some part of the line segment to lack the reference plane;]8]|^仏〇111 means checking the signal line from the chip pin to the layer Whether the distance between them is too long; PCT (10) mountain to indicate the distance between the signal line and the boundary of the reference plane. In this step S304, only one inspection item may be selected, or a plurality of inspection items may be selected. Step S306: Perform a reference plane integrity check on the signal line, where ', if the check item selected in step S304 is c〇ntinue, the signal line is projected to the corresponding reference plane, and the projection is checked. Whether the reference planes are all the same - the reference plane name, if it is referenced to more than two different reference planes, it is determined to be a touch, the inspection result is displayed and the check option is marked with an error mark; 13 1304478 If selected in step S3G4 The check item is Cn)ssM()at, then the signal line is positive & the corresponding reference plane, check whether the projection overlaps with the reference plane (four) line, if there is overlap, it means The signal and the line have a gap across the reference plane, which will be judged as _, the inspection result is displayed and the check option is marked as an error mark; if the check item selected in step S304 is Break 〇ut, then 2 bounce "The line shall prevail, check whether the length of the signal line from the day and the day to the line of the change layer is there], and the maximum length limit set in area 24 is greater than The set length will be judged as Fail. According to the current design specification, a 'this maximum length limit is more common with 5〇〇mil_1〇〇〇mils. The check report will list the length table of each line segment of the signal line to Facilitating the length of the trace of the signal line in the wafer pin area, displaying the check result and marking the check option with an error mark; if the check item selected in step S304 is MoatDist, the signal line is orthographically projected In the corresponding reference plane, it is checked that the projection and the parameter 1304478, especially the power layer, need to use a cutting line to prevent short circuit of different power planes. ‘Step S308, according to the selected inspection item, the inspection result report is generated by the report generation unit 7 for each inspection result which is checked by the signal green plane. The report includes a check result of each check object of the reference plane of the signal line and a length list of each line segment of the signal line. In step S3l, it is determined whether other signal lines are to be checked. If necessary, return to step S302 to select the next signal line to be tested, otherwise the inspection process ends. The invention can also check the integrity of the reference plane for the selected signal line group according to the selected check page, and the check item can be iPin, advertised, Tan, or only one. , or choose two or three at the same time. The quality is still checked for each signal line according to the selected inspection item—the inspection method is the same as the inspection of the reference plane with a single signal line. # ～ The report generation is the signal line selected for the batch. The check and report methods are rounded out. The display unit 4 will display the progress percentage of the inspection. 4 As shown in Fig. 4, it is a progress display of the signal line batch check. The present invention has been described above by way of a preferred embodiment, and is not intended to limit the invention. The scope of the present invention is defined by the scope of the appended claims, unless otherwise claimed. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing the structure of a preferred embodiment of a signal line reference plane inspection system of the present invention. 15 .1304478 FIG. 2 is an interface diagram of a preferred embodiment of a signal line reference plane inspection system of the present invention. 3 is a flow chart of a single signal line check of a preferred embodiment of the signal line reference plane inspection method of the present invention. Fig. 4 is a diagram showing the progress of the inspection of the signal line reference plane inspection method of the present invention.乜Example batch [Main component symbol description] Signal line reference plane inspection system B Signal line selection unit 1 Signal line filter 5 Signal line selection module 5 () Database 51 Reference plane inspection unit 6 Lang Yi S a 3兀Report generation unit 4 Ί 16