1304244 修正日期92.7.8 07986twfl.doc/006 玖、發明說明： 本發明是關於一種金屬內連線（metal interconnect)之 製造方法及其結構，且特別是關於一種不需使用接觸層 (contact layer)的局部內連線（local interconnect)之製造方法 及其結構。 於習知之積體電路中，係於基底上形成金氧半電晶體 元件，再經由金屬內連線之製程，以完成積體電路之製備。 其中各種金氧半電晶體元件係利用插塞及金屬導線進行彼 此間的電性連接，以形成一個完整之電路（drcmt)。此金 屬內連線之結構，請參照第1圖所示，基底1〇〇上之元件 104a、104b或位於隔離結構102上導線106係利用接觸層 112內之接觸窗108、接觸層122內之接觸窗120、以及金 屬導線116、126等進行電性連接，以形成一個完整之電 路。其中於接觸窗108、120、金屬導線116、126、元件104a、 104b、及導線106之間塡充介電層110、114、118、124， .以爲避免前述之電路發生短路之現象。 然而，由於在前述之元件l〇4a、104b、導線106、及 各層金屬導線116、126之間需利用接觸窗108、120以完 成各層之間的電路連接，因此，於整個積體電路之佈局中， 含有接觸窗108、120之接觸層112、122係佔用了不小之 1304244 〇7986twfl.doc/006 修正日期 92.7.8 佈局面積（layout area)。又，當不使用接觸窗108、120作 爲元件104a、104b、導線106、及各層金屬導線U6、ι26 之間的中繼電性連接時，則於此積體電路之製程中，會有 過多之電荷傳遞至元件104a、104b中，而造成元件i〇4a、 l〇4b之損壞。因此，在無法避免使用接觸窗1〇8、12〇以 減少佈局面積之情形下，積體電路之積集度無法獲得更進 一步地提升。 ’ 因此’習知爲使電路佈局面積能更進一步地縮小，而 將第1圖之元件104a與導線106之間用以電性連接之接 觸窗108與金屬導線116改以第2圖之局部內連線130取 代，並且將第1圖之其他未相互電性連接之元件104a、104b 上的接觸窗108與金屬導線116改以第2圖之接觸窗128 取代。經由前述之方式，可使原接觸窗108與金屬導線層 116所構成之雙層結構替換成接觸窗128與局部內連線接 觸窗130所構成之單層結構，如此，即可有效降低積體電 路之佈局面積。 又，在傳統局部內連線結構中，接觸層122之功能係 爲（1)避免傳統的金屬蝕刻製程或是金屬鑲嵌製程中的蝕刻 步驟對已成形之局部內連線接觸窗造成損害（2)降低金屬層 與局部內連線接觸窗之間的寄生電容。 1304244 修正日期92.7.8 〇7986twfl.doc/006 然而’在上述之局部內連線結構中，由於在形成局音G 內連線接觸窗130之後，仍須進行多道複雜之步驟才能完 成上述之局部內連線結構，因此，僅能縮短些許製程時間， 而無法達到大幅縮短製程時間之目的。 本發明之目的係提供一種局部內連線結構，以大幅降 低整體電路佈局面積。 又，本發明之再一目的係提供一種局部內連線的製造 方法，以減少局部內連線結構之形成步驟，進而大幅減少 製程時間及降低生產成本。 本發明提出一'種局部內連線之製造方法’此方法係於 基底上形成一層介電層，再圖案化此介電層，以形成局部 內連線接觸窗開口，接著，於局部內連線接觸窗開口中形 成局部內連線接觸窗，再於局部內連線接觸窗及介電層之 上形成金屬蝕刻停止層。之後，圖案化此金屬蝕刻停止層， 以形成裸露部分局部內連線接觸窗的開口，再於金屬蝕刻 停止層上形成具圖案且遮蔽前述開口之金屬導線。 又，本發明提出一種局部內連線結構，其結構包括基 底、位於基底上之介電層、嵌於介電層中的局部內連線接 觸窗、位於局部內連線接觸窗及介電層之上的金屬蝕刻停 止層、以及位於金屬蝕刻停止層之上且與局部內連線接觸 1304244 07986twfl.doc/006 修正日期 92.7.8 窗相接觸的金屬導線。 另外，本發明提出一種局部內連線之製造方法，此方 法係於基底上形成第一介電層，再圖案化此第一介電層， 以形成局部內連線接觸窗開口。接著，於局部內連線接觸 窗開口中形成局部內連線接觸窗，再於局部內連線接觸窗 及介電層之上依序形成溝渠蝕刻停止層及第二介電層。之 後，圖索化此第二介電層及此溝渠蝕刻停止層，以形成裸 露部分局部內連線接觸窗之溝渠開口，再於溝渠開口內形 成鑲嵌金屬導線。 再者，本發明提出一種局部內連線結構，其結構包括 基底、位於基底上之第一介電層、嵌於第一介電層中的局 部內連線接觸窗、位於部分局部內連線接觸窗及第一介電 層之上的溝渠蝕刻停止層、位於溝渠蝕刻停止層之上的第 二介電層、以及嵌於第二介電層及蝕刻停止層中且與部分 局部內連線接觸窗接觸的金屬導線。 另外，本發明提出一種金屬內連線之製造方法，此方 法係於第一金屬層之上形成金屬蝕刻停止層，再圖案化此 金屬蝕刻停止層，以形成裸露部分第一金屬層的開□，之 後，於金屬蝕刻停止層上形成遮蔽前述開口之具圖案之第 1304244 07986twfl.doc/006 修正日期 92.7.8 本發明係利用厚度遠薄於習知接觸層厚度的蝕刻停止 層取代習知之接觸層，且不需額外形成插塞即可使位於此 蝕刻停止層之上下二層導體電性連接，因此，可於兼具習 知之接觸層之功能的情形下，大幅降低整體電路佈局面 積。 又，本發明之局部內連線接觸窗形成步驟與次層金屬 導線形成步驟之間，僅需進行一道沈積步驟與一道微影蝕 刻步驟。由於，本發明之整體製程步驟遠少於習知之接觸 層形成步驟（二道沈積步驟、一道微影蝕刻步驟、一道化 學機械硏磨或回蝕刻步驟），因此，可大幅縮短製程時間 及降低生產成本。 再者，在本發明之金屬內連線結構中，由於利用厚度 較薄之蝕刻停止層取代習知兩金屬層之間的接觸層，因此 可大幅降低整體電路佈局面積。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明 第1圖所示爲習知之金屬內連線結構的示意圖。 第2圖所示爲習知之局部內連線結構的示意圖。 1304244 07986twfl.doc/006 修正日期 92.7.8 第3圖至第6圖所示爲本發明之第一較佳實施例之局 部內連線之製造方法的示意圖。 第7圖所示爲本發明之第二較佳實施例之局部內連線 結構的示意圖。 第8圖所示爲本發明之一較佳實施例之金屬內連線結 構的示意圖。 * 圖式之標記說明·· 100，200 :基底 102，202 :隔離結構 104a，104b，204a，204b :元件 106，206 :導線 108，120，128，214 :接觸窗 110，114，118，124，132，216，228 :介電層 112，122 :接觸層 116，126，224，232 ·•金屬導線 130，212 :局部內連線接觸窗 208 :局部內連線接觸窗開口 210 :接觸窗開口 218，302 :金屬蝕刻停止層 220，306 ··開口 1304244 修正臼期92.7.8 07986twfl.doc/006 222，300，304 :金屬層 226 :溝渠蝕刻停止層 230 :溝渠開口 實施例一 桌3圖至第6圖所不爲本發明之第一較佳實施例之局 部內連線之製造方法的示意圖。請參照第3圖所示，提供 基底200，在基底200上已形成元件204a、2〇4b ;隔離結 構202、以及位於隔離結構202上之導線206。位於隔離 結構202上之導線206之作用係作爲連結電路使用之導 線，此導線206之材質例如是摻雜多晶矽。而元件2〇4a 或元件204b可以僅由單一金氧半電晶體元件所構成，也 可以由多個金氧半電晶體所構成，視實際需要而作變動。 又，本發明之隔離結構202例如是淺溝渠隔離結構(ShaU〇w trench isolation)或是場氧化層。 另外，兀件204a、204b、隔離結構202、以及位於隔 離結構202上之導線206等的形成方法係利用習知之製造 方法所形成，爲避免混淆本發明之技術內容，因此在本發 明中省略其詳細之製程敘述。 接著’利用化學氣相沈積法卜hemical vapor deposition)，於基底200上形成一層介電層216，以覆蓋 1304244 07986twfl.doc/006 修正日期 92.7.8 基底200上之元件204a、204b、隔離結構202、以及位於 隔離結構202上之導線206。介電層216之材質例如是氧 化矽或氮化矽。再者，本發明之介電層216之形成方法雖 以化學氣相沈積法爲例進行說明，然並不以此爲限，而可 使用旋轉塗佈等方法形成。 之後，利用微影蝕刻之方式，圖案化介電層216，以 於介電層216中形成局部內連線接觸窗開口 2〇8以及接觸 窗開口 210。例如在圖案化介電層216之後，於介電層216 中形成裸露出導線206、元件204a之源極/汲極、隔離結 構202的局部內連線接觸窗開口 208，以及裸露出元件2〇4a 之閘極、元件204b之閘極、源極/汲極的接觸窗開口 21〇。 接者’利用濺鍍沈積（sputtering deposition)及化學機 械硏磨（chemical mechanical polishing)之方法，於介電層 216之局部內連線接觸窗開口 208及接觸窗開口 21〇中， 形成局部內連線接觸窗212以及接觸窗214。其中，本發 明之濺鍍沈積之方法也可以改由化學氣相沈積法或其他種 類之物理氣相沈積（physical vapor deposition)法所取代， 且本發明之化學機械硏磨法也可以改由回蝕刻（etch baek) 等的平坦化方法取代。本發明之局部內連線接觸窗212以 及接觸窗214之材質例如是鎢。又，本發明之局部內連線 修正B期92.7.8 1304244 07986twfl.doc/006 接觸窗212以及接觸窗214之材質雖以鎢爲例進行說明， 然並不以此爲限，而可使用鋁、銅、鉬、鉑、钼及鈦化物。 之後，請參照第4圖所示，利用化學氣相沈積法，於 介電層216、局部內連線接觸窗212、以及接觸窗214之 上形成一層厚約200埃至600埃的金屬蝕刻停止層218。 金屬蝕刻停止層218之材質例如爲氮化矽或氮氧化矽。接 著，再利用微影蝕刻之方法，圖案化金_屬蝕刻停止層218， 以形成開口 220以裸露部分局部內連線接觸窗212與接觸 窗214。又，本發明之形成金屬蝕刻停止層218之方法雖 以化學氣相沈積法爲例進行說明，然並不以此爲限，而可 使用旋轉塗佈等方法形成。另外，在圖案化金屬蝕刻停止 層218之過程中，金屬蝕刻停止層218之蝕刻速率與局部 內連線接觸窗212或接觸窗214的蝕刻速率不同。 其後，請參照第5圖所示，於金屬蝕刻停止層218之 上，覆蓋一層金屬層222，且此金屬層222塡滿開口 22〇。 金屬層222之材質例如是鋁，其形成的方法例如爲濺鏟法。 金屬層222之形成方法雖以濺鍍沈積法爲例進行說明，然 並不以此爲限，其亦可使用化學氣相沈積法或其他種類之 物理氣相沈積法。 接著，請參照第6圖所示，利用微影蝕刻之方法，圖 12 1304244 07986twfl.doc/006 修正日期 92.7.8 案化金屬層222，以形成遮蔽開口 220之金屬導線224。 其中金屬導線224係與局部內連線接觸窗212電性連接， 或與接觸窗214電性連接。再者，在圖案化金屬層222之 過程中，金屬層222之蝕刻速率與金屬蝕刻停止層218之 蝕刻速率不同。 在本較佳實施例之局部內連線接觸窗212雖以隔離結 構202上之導線206與元件204a之源極/汲極之間的電性 連接爲例進行說明，然並不以此爲限，而可使用於相鄰二 個元件之源極/汲極之間的電性連接。 實施例二 第7圖所示爲本發明之第二較佳實施例之局部內連線 結構的示意圖。由於本較佳實施例於形成溝渠飩刻停止層 226之前的製造方法及步驟係與第一較佳實施例於形成金 屬蝕刻停止層218之前的製造方法及步驟相同，因此在本 較佳實施例中不予贅述。又，本較佳實施例與第一較佳實 施例相同之物件，係使用相同之標號表示。 請參照第7圖所示，於形成局部內連線接觸窗212與 接觸窗214之後，利用化學氣相沈積法，於介電層216 ' 局部內連線接觸窗212、以及接觸窗214之上形成一層厚 13 1304244 07986twfl.doc/006 修正曰期 92.7.8 約200埃至600埃的溝渠蝕刻停止層226。溝渠蝕刻停止 層226之材質例如是氮化矽或氮氧化矽。形成溝渠蝕刻停 止層226之方法亦可採用旋轉塗佈等方法形成。 之後，於溝渠蝕刻停止層226之上形成一層介電層 228。介電層228之材質例如是氧化砂或氮化砂，其形成 的方法例如是化學氣相沈積法。 接著，利用微影蝕刻乏方法，圖案化介電層228及溝 渠蝕刻停止層226，以形成裸露部分局部內連線接觸窗212 與接觸窗214之的溝渠開口 230。另外，在圖案化介電層 228及溝渠蝕刻停止層226之過程中，溝渠蝕刻停止層226 之蝕刻速率與介電層216、局部內連線接觸窗212、或接 觸窗214之蝕刻速率不同。 其後，利用濺鍍沈積法與化學機械硏磨法，於溝渠開 α 23〇中，形成金屬導線232。金屬導線232之材質例如 是銅、鎢、鈦等金屬。又，金屬導線232的沉積方法亦可 &改用化學氣相沈積法或其他種類之物理氣相沈積法取 代’而化學機械硏磨法也可以改用回蝕刻等的平坦化方法 取代。此時，金屬導線232係與局部內連線接觸窗212或 接觸窗214電性連接。 另外，本發明金屬導線232之結構雖以金屬鑲嵌結構 l3〇4244 0798 6twfl.doc/〇〇6 修正0期92.7.8 爲例進行說明，然並不以此爲限，而可爲雙層金屬鑲嵌結 擒。 在本較佳實施例之局部內連線接觸窗212雖以隔離結 構202上之導線206與元件204a之源極/汲極之間的電性 連接爲例進行說明，然並不以此爲限，而可使用於相鄰二 個元件之源極/汲極之間的電性連接。 由上述可知，本發明之局部內連線接觸窗形成步驟與 次層金屬導線形成步驟之間，僅需進行一道沈積步驟與一 道微影蝕刻步驟。由於，本發明之整體製程步驟遠少於習 知之接觸層形成步驟（二道沈積步驟、一道微影蝕刻步驟、 〜道化學機械硏磨或回蝕刻步驟），因此，可大幅縮短製 程時間及降低生產成本。 又，在本發明之局部內連線結構中，係利用厚度遠薄 於習知接觸層厚度（約3000埃至6000埃）的餓刻停止層 取代習知之接觸層，且不需額外形成插塞即可使位於此蝕 刻停止層之上下二層導體電性連接，因此，可於兼具習知 之接觸層之功能的情形下，大幅降低整體電路佈局面積。 另外，於第一較佳實施例中，由於本發明之金屬導線 係利用鑲嵌於金屬蝕刻停止層之小面積開口內的金屬導線 突出部分與接觸窗或局邰內連線接觸窗電性連接，因此， 15 1304244 07986twfl.doc/006 修正日期 92.7.8 可以避免金屬蝕刻製程或是金屬鑲嵌製程中的蝕刻步驟對 已成形之局部內連線接觸窗造成損害，且同時可以降低金 屬層與局部內連線接觸窗之間的寄生電容。 再者，於第二較佳實施例中，由於金屬導線與局部內 連線接觸窗係利用金屬導線與局部內連線接觸窗邊緣之小 面積的接觸部份進行電性連接，因此，可以避免金屬蝕刻 製程或是金屬鑲嵌製程中的蝕刻步驟對已成形之局部內連 線接觸窗造成損害，且同時可以降低金屬層與局部內連線 接觸窗之間的寄生電容。 再者，本發明之局部內連線之製造方法也可以應用於 金屬內連線之製造方法中，例如，請參照第8圖所示，於 金屬層300與金屬層304之間，利用例如是氮化矽且厚度 介於200埃至600埃之間的金屬蝕刻停止層302隔離，且 金屬層304經由鑲嵌於金屬餓刻停止層302之小面積開口 306內的金屬層304之突出部分與金屬層300電性連接。 因此，使用前述之結構，可大幅減少金屬層之間的絕緣層 使用體積，進而大幅減少金屬內連線結構之電路佈局面 積。 再者，由於上述之金屬層形成步驟之間，僅需進行一 道沈積步驟與一道微影蝕刻步驟，此金屬蝕刻停止層之形 16 1304244 07986twfl.doc/006 修正日期 92.7.8 成步驟遠少於習知之接觸層形成步驟（二道沈積步驟、一 道微影蝕刻步驟、一道化學機械硏磨或回蝕刻步驟），因 此，可大幅縮短製程時間及降低生產成本。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。1304244 Revision Date 92.7.8 07986twfl.doc/006 BRIEF DESCRIPTION OF THE INVENTION The present invention relates to a method of fabricating a metal interconnect and its structure, and more particularly to a contact layer that does not require the use of a contact layer. The manufacturing method of the local interconnect and its structure. In the conventional integrated circuit, a gold-oxygen semi-transistor element is formed on a substrate, and then a metal interconnect process is performed to complete the preparation of the integrated circuit. Among them, various MOS semi-transistor components are electrically connected to each other by plugs and metal wires to form a complete circuit (drcmt). For the structure of the metal interconnect, as shown in FIG. 1, the elements 104a, 104b on the substrate 1 or the wires 106 on the isolation structure 102 are in the contact window 108 in the contact layer 112, and in the contact layer 122. The contact window 120, and the metal wires 116, 126, etc. are electrically connected to form a complete circuit. The dielectric layers 110, 114, 118, 124 are interposed between the contact windows 108, 120, the metal wires 116, 126, the elements 104a, 104b, and the wires 106, in order to avoid the short circuit of the aforementioned circuit. However, since the contact windows 108, 120 are required to be used between the aforementioned components 104a, 104b, the wires 106, and the respective metal wires 116, 126 to complete the circuit connection between the layers, the layout of the entire integrated circuit is performed. The contact layers 112, 122 containing the contact windows 108, 120 occupy a large amount of 1304244 〇 7986 twfl.doc / 006 date 92.7.8 layout area. Moreover, when the contact windows 108 and 120 are not used as the relay electrical connection between the elements 104a and 104b, the wires 106, and the metal wires U6 and ι26 of the respective layers, there are too many processes in the integrated circuit. The charge is transferred to the elements 104a, 104b, causing damage to the elements i〇4a, l4b. Therefore, in the case where the contact windows 1〇8, 12〇 cannot be avoided to reduce the layout area, the integration of the integrated circuits cannot be further improved. Therefore, it is known that the circuit layout area can be further reduced, and the contact window 108 and the metal wire 116 for electrically connecting the element 104a and the wire 106 of FIG. 1 are changed to the inside of the second figure. The wire 130 is replaced and the contact window 108 and the metal wire 116 on the other non-interconnecting elements 104a, 104b of Fig. 1 are replaced by the contact window 128 of Fig. 2. Through the foregoing manner, the double-layer structure formed by the original contact window 108 and the metal wire layer 116 can be replaced by the single-layer structure formed by the contact window 128 and the partial interconnecting contact window 130, so that the integrated body can be effectively reduced. The layout area of the circuit. Moreover, in the conventional partial interconnect structure, the function of the contact layer 122 is to (1) avoid the damage of the formed local interconnect contact window by the conventional metal etching process or the etching step in the damascene process (2) ) reducing the parasitic capacitance between the metal layer and the local interconnect contact window. 1304244 Amendment date 92.7.8 〇7986twfl.doc/006 However, in the above-mentioned partial interconnect structure, since the inter-line contact window 130 is formed after the interstation G is formed, multiple complicated steps are required to complete the above. The local interconnect structure, therefore, can only shorten the process time, and can not achieve the purpose of greatly shortening the process time. SUMMARY OF THE INVENTION It is an object of the present invention to provide a partial interconnect structure to substantially reduce the overall circuit layout area. Still another object of the present invention is to provide a method of fabricating a partial interconnect to reduce the formation of a local interconnect structure, thereby substantially reducing process time and manufacturing cost. The present invention provides a method for fabricating a local interconnect. This method forms a dielectric layer on a substrate, and then patterned the dielectric layer to form a local interconnect contact opening, and then in a local interconnect. A local interconnect contact window is formed in the line contact window opening, and a metal etch stop layer is formed on the local interconnect contact window and the dielectric layer. Thereafter, the metal etch stop layer is patterned to form an opening of the exposed portion of the local interconnect contact window, and a metal trace having a pattern and shielding the opening is formed on the metal etch stop layer. Moreover, the present invention provides a partial interconnect structure having a structure including a substrate, a dielectric layer on the substrate, a local interconnect contact window embedded in the dielectric layer, a local interconnect contact window, and a dielectric layer. A metal etch stop layer overlying the metal traces over the metal etch stop layer and in contact with the local interconnect contact 1304244 07986 twfl.doc/006 revision date 92.7.8 window. In addition, the present invention provides a method of fabricating a partial interconnect which is formed by forming a first dielectric layer on a substrate and then patterning the first dielectric layer to form a local interconnect contact opening. Then, a local interconnect contact window is formed in the local interconnect contact window opening, and the trench etch stop layer and the second dielectric layer are sequentially formed on the local interconnect contact window and the dielectric layer. Thereafter, the second dielectric layer and the trench etch stop layer are patterned to form a trench opening of the exposed portion of the partial interconnect contact window, and a damascene metal trace is formed in the trench opening. Furthermore, the present invention provides a partial interconnect structure having a structure including a substrate, a first dielectric layer on the substrate, a local interconnect contact window embedded in the first dielectric layer, and a partial local interconnect a contact etch stop layer over the contact window and the first dielectric layer, a second dielectric layer over the trench etch stop layer, and a second dielectric layer and an etch stop layer and a portion of the local interconnect A metal wire that contacts the contact window. In addition, the present invention provides a method for fabricating a metal interconnect by forming a metal etch stop layer over the first metal layer and patterning the metal etch stop layer to form a first metal layer of the exposed portion. Thereafter, a pattern for shielding the opening is formed on the metal etch stop layer. The first invention is to replace the conventional contact with an etch stop layer having a thickness much thinner than the thickness of the conventional contact layer. The layers can be electrically connected to the lower two layers of conductors located above the etch stop layer without additional plug formation. Therefore, the overall circuit layout area can be greatly reduced in the case of the function of the conventional contact layer. Further, between the partial interconnect contact window forming step of the present invention and the sub-layer metal wire forming step, only one deposition step and one lithography step are required. Since the overall process steps of the present invention are much less than the conventional contact layer formation step (two deposition steps, one lithography etching step, one chemical mechanical honing or etchback step), the process time and production can be greatly shortened. cost. Further, in the metal interconnect structure of the present invention, since the etching stop layer having a relatively small thickness is used instead of the contact layer between the conventional two metal layers, the overall circuit layout area can be greatly reduced. The above and other objects, features and advantages of the present invention will become more <RTIgt; Shown as a schematic diagram of a conventional metal interconnect structure. Figure 2 is a schematic illustration of a conventional local interconnect structure. 1304244 07986twfl.doc/006 Revision Date 92.7.8 FIGS. 3 to 6 are schematic views showing a method of manufacturing a local interconnect of the first preferred embodiment of the present invention. Fig. 7 is a view showing a partial interconnect structure of a second preferred embodiment of the present invention. Figure 8 is a schematic illustration of a metal interconnect structure in accordance with a preferred embodiment of the present invention. * Schematic description of the figure · 100,200: substrate 102, 202: isolation structure 104a, 104b, 204a, 204b: element 106, 206: wire 108, 120, 128, 214: contact window 110, 114, 118, 124 , 132, 216, 228: dielectric layer 112, 122: contact layer 116, 126, 224, 232 · metal wire 130, 212: partial interconnect contact window 208: local interconnect contact opening 210: contact window Openings 218, 302: metal etch stop layer 220, 306 · opening 1304244 modified period 92.7.8 07986twfl.doc / 006 222, 300, 304: metal layer 226: trench etch stop layer 230: trench opening embodiment 1 table 3 Figures 6 through 6 are schematic views of a method of fabricating a partial interconnect of a first preferred embodiment of the present invention. Referring to Figure 3, a substrate 200 is provided on which elements 204a, 2〇4b, isolation structure 202, and wires 206 on isolation structure 202 have been formed. The wire 206 on the isolation structure 202 acts as a conductor for the connection circuit, and the material of the wire 206 is, for example, doped polysilicon. The element 2〇4a or the element 204b may be composed of only a single MOS transistor, or may be composed of a plurality of MOS transistors, and may be varied as needed. Moreover, the isolation structure 202 of the present invention is, for example, a shallow trench isolation structure or a field oxide layer. In addition, the forming methods of the elements 204a, 204b, the isolation structure 202, and the wires 206 and the like on the isolation structure 202 are formed by a conventional manufacturing method, and in order to avoid obscuring the technical contents of the present invention, the description thereof is omitted in the present invention. Detailed process description. Next, a dielectric layer 216 is formed on the substrate 200 to cover the elements 204a, 204b and the isolation structure 202 on the substrate 200. And a wire 206 on the isolation structure 202. The material of the dielectric layer 216 is, for example, tantalum oxide or tantalum nitride. Further, although the method of forming the dielectric layer 216 of the present invention has been described by taking a chemical vapor deposition method as an example, it is not limited thereto, and it can be formed by a method such as spin coating. Thereafter, dielectric layer 216 is patterned by lithography to form local interconnect contact opening 2 〇 8 and contact opening 210 in dielectric layer 216. For example, after patterning dielectric layer 216, bare exposed wires 206, source/drain of element 204a, local interconnect contact opening 208 of isolation structure 202, and exposed features 2 are formed in dielectric layer 216. The gate of 4a, the gate of element 204b, and the contact opening 21 of the source/drain. The contactor's use of sputtering deposition and chemical mechanical polishing to form a local interconnect in the local interconnect contact opening 208 and the contact opening 21 of the dielectric layer 216 Line contact window 212 and contact window 214. Wherein, the method of sputter deposition of the present invention may also be replaced by chemical vapor deposition or other kinds of physical vapor deposition, and the chemical mechanical honing method of the present invention may also be modified. Replacement by a planarization method such as etching (etch baek). The material of the partial interconnect contact window 212 and the contact window 214 of the present invention is, for example, tungsten. Moreover, the local interconnect modification B of the present invention is 92.7.8 1304244 07986twfl.doc/006. The material of the contact window 212 and the contact window 214 is described by taking tungsten as an example, but not limited thereto, aluminum can be used. , copper, molybdenum, platinum, molybdenum and titanium. Thereafter, as shown in FIG. 4, a metal etch stop having a thickness of about 200 angstroms to 600 angstroms is formed over the dielectric layer 216, the local interconnect contact window 212, and the contact window 214 by chemical vapor deposition. Layer 218. The material of the metal etch stop layer 218 is, for example, tantalum nitride or hafnium oxynitride. Next, the etch stop layer 218 is patterned by photolithography to form openings 220 to expose portions of the inner interconnect contact 212 and contact 214. Further, the method of forming the metal etch stop layer 218 of the present invention is described by taking a chemical vapor deposition method as an example, but it is not limited thereto, and it can be formed by a method such as spin coating. Additionally, during the patterning of the metal etch stop layer 218, the etch rate of the metal etch stop layer 218 is different than the etch rate of the local interconnect contact 212 or contact 214. Thereafter, referring to FIG. 5, a metal layer 222 is overlaid on the metal etch stop layer 218, and the metal layer 222 fills the opening 22 〇. The material of the metal layer 222 is, for example, aluminum, and the method of forming the metal layer 222 is, for example, a sputtering method. Although the method of forming the metal layer 222 is described by way of a sputtering deposition method, it is not limited thereto, and chemical vapor deposition or other kinds of physical vapor deposition methods may be used. Next, referring to Fig. 6, the metal layer 222 is formed by the method of lithography etching, as shown in Fig. 12 1304244 07986 tw. doc/006, to modify the date 92.7.8 to form the metal wire 224 of the shielding opening 220. The metal wire 224 is electrically connected to the local interconnecting contact window 212 or electrically connected to the contact window 214. Moreover, during the patterning of the metal layer 222, the etch rate of the metal layer 222 is different from the etch rate of the metal etch stop layer 218. The partial interconnect contact window 212 in the preferred embodiment is described by taking the electrical connection between the wire 206 on the isolation structure 202 and the source/drain of the component 204a as an example. It can be used for electrical connection between the source/drain of two adjacent elements. Embodiment 2 FIG. 7 is a schematic view showing a partial interconnect structure of a second preferred embodiment of the present invention. The manufacturing method and the steps of the preferred embodiment before forming the trench etch stop layer 226 are the same as those of the first preferred embodiment before the metal etch stop layer 218 is formed. Therefore, in the preferred embodiment I will not repeat them. Further, the same items as those of the first preferred embodiment of the present preferred embodiment are denoted by the same reference numerals. Referring to FIG. 7, after forming the local interconnect contact window 212 and the contact window 214, the dielectric layer 216' is partially connected to the contact layer 212 and the contact window 214 by chemical vapor deposition. Form a layer of thickness 13 1304244 07986twfl.doc / 006 to modify the etch period stop layer 226 of 92.7.8 about 200 angstroms to 600 angstroms. The material of the trench etch stop layer 226 is, for example, tantalum nitride or hafnium oxynitride. The method of forming the trench etch stop layer 226 can also be formed by a method such as spin coating. Thereafter, a dielectric layer 228 is formed over the trench etch stop layer 226. The material of the dielectric layer 228 is, for example, oxidized sand or nitrided sand, and the method of forming it is, for example, chemical vapor deposition. Next, the dielectric layer 228 and the trench etch stop layer 226 are patterned by a lithography etch process to form the bare portion local interconnect contact 212 and the trench opening 230 of the contact 214. In addition, during the patterning of the dielectric layer 228 and the trench etch stop layer 226, the etch rate of the trench etch stop layer 226 is different from the etch rate of the dielectric layer 216, the local interconnect contact 212, or the contact window 214. Thereafter, a metal wire 232 is formed in the trench opening α 23〇 by a sputtering deposition method and a chemical mechanical honing method. The material of the metal wire 232 is, for example, a metal such as copper, tungsten or titanium. Further, the method of depositing the metal wires 232 may be replaced by a chemical vapor deposition method or another type of physical vapor deposition method, and the chemical mechanical honing method may be replaced by a planarization method such as etchback. At this time, the metal wire 232 is electrically connected to the partial interconnect contact window 212 or the contact window 214. In addition, although the structure of the metal wire 232 of the present invention is illustrated by the metal mosaic structure l3〇4244 0798 6twfl.doc/〇〇6 revision 0, 92.7.8, it is not limited thereto, but may be a double metal. Inlaid with knots. The partial interconnect contact window 212 in the preferred embodiment is described by taking the electrical connection between the wire 206 on the isolation structure 202 and the source/drain of the component 204a as an example. It can be used for electrical connection between the source/drain of two adjacent elements. From the above, it can be seen that between the partial interconnect contact window forming step and the sub-layer metal wire forming step of the present invention, only one deposition step and one lithography etching step are required. Since the overall process steps of the present invention are far less than the conventional contact layer formation step (two deposition steps, one photolithography etching step, ~channel chemical mechanical honing or etchback step), the process time can be greatly shortened and reduced. Cost of production. Further, in the partial interconnect structure of the present invention, the conventional contact layer is replaced by a hungry stop layer having a thickness much thinner than the conventional contact layer thickness (about 3000 angstroms to 6000 angstroms), and no additional plug is required. The two layers of conductors located above the etch stop layer can be electrically connected. Therefore, the overall circuit layout area can be greatly reduced in the case of the function of the conventional contact layer. In addition, in the first preferred embodiment, since the metal wire of the present invention is electrically connected to the contact window or the contact line of the contact wire by using the protruding portion of the metal wire embedded in the small-area opening of the metal etch stop layer, Therefore, 15 1304244 07986twfl.doc/006 Amendment date 92.7.8 can avoid the metal etching process or the etching step in the damascene process to damage the formed local interconnect contact window, and at the same time reduce the metal layer and the local part Connect the parasitic capacitance between the contact windows. Furthermore, in the second preferred embodiment, since the metal wire and the partial interconnect contact window are electrically connected by the metal wire and the small-area contact portion of the edge of the partial interconnect contact window, it can be avoided. The metal etching process or the etching step in the damascene process damages the formed local interconnect contact window and at the same time reduces the parasitic capacitance between the metal layer and the local interconnect contact window. Furthermore, the method of manufacturing the partial interconnection of the present invention can also be applied to a method of manufacturing a metal interconnection. For example, as shown in FIG. 8, between the metal layer 300 and the metal layer 304, for example, The metal etch stop layer 302 is isolated from tantalum nitride and having a thickness between 200 angstroms and 600 angstroms, and the metal layer 304 is over the metal portion 304 and the metal portion 304 embedded in the small area opening 306 of the metal stop layer 302. Layer 300 is electrically connected. Therefore, by using the above structure, the use volume of the insulating layer between the metal layers can be greatly reduced, and the circuit layout area of the metal interconnect structure can be greatly reduced. Furthermore, since the metal layer forming step is performed, only one deposition step and one lithography etching step are required, and the shape of the metal etch stop layer is 16 1304244 07986 twfl.doc/006, and the correction date is 92.7.8. The conventional contact layer forming step (two deposition steps, one lithography etching step, one chemical mechanical honing or etch back step) can greatly shorten the processing time and reduce the production cost. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
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