TWI303829B - Internal voltage geneator of semiconductor integrated circuit - Google Patents

Description

1303829 IX. Description of the invention: [Technical field to which the invention pertains] In particular, a semiconductor integrated body The present invention relates to an internal voltage generator of a semiconductor integrated circuit. [Prior Art]

The external voltage VDD from the I, the semiconductor integrated circuit, especially the DRAM (moving_access memory) has been reduced. Therefore, it is necessary to suppress internal power variations due to temperature changes as much as possible. Again: square 2 controls each internal power change (positive or negative) to a better direction. In the basic memory cell structure of f, connect the transistor/electric thief to the - word line and one bit line, as shown in the first. For the transistors used in DRAM, crystals have been used, and their performance is better than that of PMOS transistors, but the size of the car is larger than the comparison between the different levels of electricity in M. According to the peak result, the magnitude of the (four) pressure level is cis, VDD, VCORE, VBLP & VCP, and vbb. The VDD is the voltage supplied from the outside of the DRAM, and the voltage sign VCORE, VBLP & VCP and VBB are generated by increasing or decreasing the voltage vdd. The voltage VPP is basically used for the loss of the threshold voltage VT of the transistor, which is used for the word_(4), the data output drive β or the like to compensate for the basic element of the memory cell. This voltage νρρ is generated by the increase voltage VDD, which is greater than the voltage Vc 〇 RE + the critical value ντ (which is the maximum value of the internal power 6 1303829 f :). The voltage VCORE is the data level corresponding to the cell memory cell. The voltage VBLP corresponds to the charging voltage 'and the voltage VCP is the cell voltage, and the bit line is pre-

= the level of =. In addition, the electricity B corresponds to a group of P " is added to most of the transistors with a negative value. & voltage, and . The attached schematic of the latter semiconductor integrated circuit will be described.仏屋生电路 will refer to

^ Two® for semiconductor integrated circuit diagrams based on related feats. The fourth figure is a circuit diagram of the base-shaped internal structure shown in the third figure. The fifth figure is a circuit diagram of the internal structure of === shown in the third figure. The sixth picture is a graph of the voltage change according to the reference of the relevant ^:. The seventh picture is a graph of the pressure demand conditions at low temperatures. a As shown in the second figure, the internal voltage generating circuit of the semiconductor integrated circuit according to the related art includes a reference voltage generating unit 1 产生 which generates a basic reference voltage VREF_BASE when an external voltage VDD is increased to reach a predetermined level. And a level shifter u, which converts the basic reference voltage VREF-BASE into a first reference voltage VREF-c for generating a cell voltage and a substrate bias voltage, and a second reference voltage VREF- P, for generating an elevated voltage and outputting it; a cell generating unit 12, which uses the first reference voltage VREF-C to generate a cell voltage VC0RE; a substrate bias voltage generating unit, which uses The first reference voltage VREF_C generates a substrate bias voltage VBB, and the _ boost voltage generating unit 14 generates a liter 1303829 high voltage VPP using the second reference voltage VREFjp.

W This level offset $u has the structure of the _differential comparator. The reference voltage VREF-BASE and the electrical VR differentiated by the resistors R1 and R2 are maintained at the same value through a feedback operation while the first reference voltage vref_C is The ratio of the resistance between the phantoms is determined. In addition, the second reference voltage vref is generated by adjusting, the ratio of the resistance of the sea, as in the first reference voltage vref. For example, a plurality of capacitors having a resistance value smaller than the resistors R1 and R2 and connected to each other, and the second reference voltage VREF_p is output by the node, which is selected at the plurality of points, and outputs - desired Voltage. The cell generating unit 12 includes a comparator, 12 small having a reverse terminal 'for receiving the first reference voltage VREF-c, and a second transistor 12_2' having a gate for receiving the comparator 12- When the wheel is turned back to the non-inverting terminal + of the comparator m, the external voltage lion is converted according to the gate, and the output is - MG 〇rE. At this time, in order to maintain the level of the cell voltage VCORE at the value, the generating unit 12 operates in the following manner. That is, the cell

Cct VREF~C and the cell voltage Adam's cell voltage VCORE is reduced to not exceed the voltage of the parameter, and the bank 赚2 is earned so that the cell 12 is supplied to the external voltage side, thereby increasing the cell ι RE. In addition, when the voltage of the cell voltage VCQRE is at the voltage of the third:?=2EF-C, the cell voltage generating unit 12 turns off the side body 12_2 so that the cell voltage VC0RE is not added. 1303829 Further, the substrate bias voltage generating unit 13 includes a comparator 13-1, a transistor 13-2, and a substrate bias voltage detector 13-3 for detecting the transistor 13-2. Outputting a level of a voltage VC0RE_BB, and outputting a substrate bias voltage pump enable signal, and a substrate bias voltage pump 13-4' driven by the substrate bias voltage spring enable signal, and extracting the substrate Bias voltage VBB. The connection structure between the comparator 13-1 and the transistor 13-2 is the same as that of the cell voltage generating unit 12. However, although the level of the voltage VCORE_BB is the same as the level of the cell voltage VCORE, since the amount of current consumed by the device is smaller in the substrate bias voltage generating unit 13, the voltage VCORE-BB is different from the cell voltage. VCORE, in which the size of the comparator 13-1 and the transistor 13-2 in the substrate bias voltage generating unit 13 is smaller than those in the cell voltage generating unit 12. Further, the structure of the substrate bias voltage detector 13-3 is as shown in the fourth figure. If the absolute value of the substrate bias voltage VBB becomes smaller, the impedance component of a lower transistor increases. Therefore, the substrate bias voltage detector 13-3 causes a potential difference at the DET, φ node to become a high level, thereby causing the potential difference of 'BB-ENM' to become a low level. At this time, Ββ_ΕΝΜ is a signal oscillating between the voltage VCORE_BB outputted from the transistor 13-2 and the ground voltage VSS. The level shifter converts, BB_Enbl, the signal into a substrate bias voltage pump enable signal 'BB_ENb2', which swings between the external voltage VDD and the ground voltage VSS. When 'BB-ENb2, it becomes a low-level quasi-day ^*'. ‘The power of the DET node will increase when the V-C-C is increased for any reason. Thereby, in order to allow the potential difference at the node of 1303829 to become a low level, the substrate bias voltage vest must be increased, and the sub-value must be increased. Therefore, the absolute value of the substrate bias voltage is increased. The booster voltage generating unit 7〇14 includes an elevated electric (four) detector 14-1 which is output by the level of the second reference cake vref. A = high voltage pump enable signal, and a The boosting voltage pump 14_2 is driven by the pump to the fifth pump and extracts the boosted voltage VPP. • =, the structure of the elevated voltage debt test 1114] is as shown in the fifth figure. That is to say, the voltage at an 'X node' and a second reference voltage vref_p are clocked into the two wheel terminals of the differential comparator. The χ node corresponds to a node to which the impedance can be distributed such that it has the same potential difference as the second reference voltage VREF_p when the boosted voltage νρρ is a target value. Therefore, when the boosted voltage VPP becomes lower than the target value, since the voltage at the 'X node' also becomes smaller than the second reference voltage VREF-P, the boosted voltage pump enables the signal f#" ipp__EN, which becomes a high level through the operation of the comparison device, such that the boosted voltage pump can extract the boosted voltage VPP. If the second reference voltage VREF p for generating the boosted voltage is For any reason, in the increased voltage detector 14, the boosted voltage WP will become greater than the original target value, which causes the boosted voltage pump enable signal, PP-EN' The level becomes the low level. Therefore, the boosted voltage VPP is increased. At this time, if the reference voltage VREFBASE is changed, the first shift by the level shifter 11 The second reference electric grinder 10 1303829 VREF_P also changes. That is, when the basic reference voltage VREF_BASE is lowered, the second reference voltage VREF JP for generating the boosted voltage is also lowered. Meanwhile, in the low temperature condition (ie, At cooler temperatures, such as _ 1 〇. 〇, even when the rise When the voltage vpp, the cell voltage VCC)RE, and the substrate bias voltage VBB are constant, the critical value VTN of the NMOS NM0S transistor is increased, which causes the current driving of the NMOS transistor to be reduced. As shown in the seventh figure, under the low temperature condition, increasing the voltage vpp and the cell voltage VCORE, and lowering the substrate bias voltage house vbb (then the substrate bias voltage VBB is reduced, that is, the absolute value is reduced) That is, it has an effect on the normal operation of the semiconductor integrated circuit. However, according to the related art, the corresponding internal voltage is generated by using the reference voltage generated by the source without considering the change due to the temperature condition. Therefore, if the corresponding internal voltage, that is, the boosted voltage VPP and the cell voltage vc〇RE, is increased by increasing the reference voltage and VREF-C under the low temperature condition, the substrate leakage is VBB. That is, it must be lower than the corresponding level, or _ at the corresponding level 'it will also increase ((4), the increase of the substrate bias money VBB will refer to the increase of the absolute value). Therefore, the semiconductor Product The present invention is directed to solving the above problems. It is an object of the present invention to provide an internal power generator for a semiconductor integrated circuit that can be used according to each of the temperature conditions of 11 1303829. Controlling each internal voltage level and preventing degradation of the performance of the semiconductor integrated circuit. According to a first aspect of the present invention, an internal voltage generator of a semiconductor integrated circuit includes at least one variable reference voltage generating unit, which can be a change in temperature to produce an increase or decrease in a basic reference voltage; at least one quasi-offset unit that converts the basic reference voltage output by the at least one variable reference voltage generating unit to at least generate an internal voltage a predetermined reference voltage, and outputting the converted reference voltage, and at least one internal voltage > generating unit that generates an internal voltage by using the at least one reference voltage for generating a quasi-offset by the at least one bit The internal voltage output by the unit. According to a second aspect of the present invention, there is provided an internal voltage generator of a semiconductor integrated circuit using a cell voltage VCORE, an elevated voltage VPP, and a substrate bias voltage VBB, which are applied by the outside by conversion The external voltage is generated by the internal voltage. The internal power of the semiconductor integrated circuit includes a temperature-inverse ratio type reference voltage generating unit that generates an increased basic reference voltage according to a decrease in temperature; a first level shifting unit, which can Converting the basic reference voltage outputted by the temperature-inverse ratio type reference voltage generating unit to a voltage generating reference voltage and a voltage of one liter south generating a reference voltage, and outputting the converted McCaw voltage; a first internal voltage a generating unit that generates the reference voltage by using the cell voltage to generate a reference voltage and the boosted voltage output by the first level shifting unit to generate the reference voltage and the boosted voltage; a temperature-proportional type reference a voltage generating unit that generates a reduced base reference voltage 12 1303829 according to a decrease in temperature; a second level shifting unit that converts the basic reference voltage output by the temperature proportional type reference voltage generating unit a substrate bias voltage generates a reference voltage and outputs the converted reference voltage; and a second internal voltage generating unit by Generating the substrate bias voltage with a reference voltage generated by the second level-shift the output of the unit substrate bias voltage voltage. According to a third aspect of the present invention, there is provided an internal voltage generator of a semiconductor integrated circuit using a cell voltage VCORE, an elevated voltage VPP, and a substrate bias voltage VBB, which are converted by the outside world. The applied external voltage is generated by the internal voltage. An internal voltage generator of a semiconductor integrated circuit includes a temperature-independent type reference voltage generating unit that generates a predetermined reference basic reference voltage without any change in temperature: a first level shifting unit, The basic reference voltage outputted by the temperature-independent type reference voltage generating unit is converted into a cell voltage generating reference voltage and an elevated voltage generating reference voltage, and the converted reference voltage φ is output; An internal voltage generating unit that generates a reference voltage by using the cell voltage to generate a reference voltage and the boosted voltage output by the first level shifting unit to generate the reference voltage and the boosted voltage; a temperature-proportional type a state reference voltage generating unit that generates a reduced basic reference voltage according to a decrease in temperature; a second level shifting unit that converts the basic reference voltage output by the temperature proportional type reference voltage generating unit into a a substrate bias voltage generates a reference voltage and outputs the converted reference voltage; and a second internal voltage generating unit by The substrate 13 1303829 bias voltage is generated using the substrate bias voltage output by the second level shifting unit to generate a reference voltage. According to a fourth aspect of the present invention, an internal voltage generator of a semiconductor integrated circuit is provided which uses a cell voltage VCORE, an elevated voltage VPP, and a substrate bias voltage VBB which is applied by the outside by conversion The external voltage is generated by the internal voltage. An internal voltage generator of a semiconductor integrated circuit includes a temperature-inverse ratio type reference voltage generating unit that generates an increased basic reference voltage according to a decrease in temperature; a first level shifting unit that is convertible by The basic reference voltage outputted by the temperature-inverse ratio type reference voltage generating unit becomes a cell voltage generating reference voltage and an elevated voltage generating reference voltage, and outputs the converted reference voltage; a first internal voltage generating unit Generating the cell voltage and the boosted voltage by generating a reference voltage by using the cell voltage and generating the reference voltage by the boosted voltage output by the first level shifting unit; a temperature-independent type reference voltage generating unit, It generates a predetermined reference level of the reference voltage without any change in temperature; a second level shifting unit that converts the basic reference voltage output by the temperature independent type reference voltage generating unit into a substrate bias The voltage voltage generates a reference voltage and outputs the converted reference voltage; and a second internal voltage generating unit The substrate bias voltage is generated by generating a reference voltage by the substrate bias voltage outputted by the second level shifting unit. [Embodiment] Before describing a preferred embodiment of the present invention, a specific embodiment of the basic idea according to the present invention will be described with reference to the eighth embodiment. 14 1303829 As shown in the eighth embodiment, the internal voltage generator of the semiconductor integrated circuit according to an embodiment of the present invention includes a first variable reference voltage generating unit 20, which can generate any basic reference voltage according to a change in temperature. The increase, the decrease of the basic reference voltage according to the temperature change, and a basic reference voltage having a predetermined level, irrespective of the temperature change; a first level shifter 21, the conversion is performed by the first variable reference The basic reference voltage outputted by the voltage generating unit 20 becomes at least a predetermined reference voltage for generating an internal voltage and outputting the same; a first internal voltage generating unit 22 generates an internal voltage by using at least one reference voltage. , which is used to generate an internal voltage output by the first level shifter 21; a second variable reference voltage generating unit 30, which can generate any basic reference voltage according to the temperature change, and generate according to the temperature change a reduced basic reference voltage, and a basic reference voltage having a predetermined level, irrespective of temperature changes, a second a quasi-offset 31 that converts the basic reference voltage outputted by the second variable reference voltage generating unit 30 into at least one predetermined reference voltage for generating an internal voltage and outputting the same; The internal voltage generating unit 32 generates an internal voltage by using at least one reference voltage to generate an internal voltage output by the second level shifter 31. Each of the first variable reference voltage generating unit 20 and the second variable reference voltage generating unit 30 is composed of the following temperature proportional type reference voltage generating unit, a temperature-inverse ratio type reference voltage generating unit, and a temperature-independent type. The state reference voltage generating unit is constructed by any one of the corresponding internal voltage systems to increase, decrease or maintain, thereby improving the operating characteristics under a corresponding temperature condition of 15 1303829. The temperature-proportional type reference voltage generating unit is decreased according to the temperature drop, and the temperature is inflamed: two:: = special (four) the output level is decreased according to the temperature: the temple; ^ produces the characteristics of the irrelevant type reference voltage generating unit In order to maintain a predetermined;:: accurate, and no change in temperature. Output bit

That is, each of the first-variable reference_generating units is referred to as a reference voltage generating unit 3. It is composed of the temperature-inverse ratio type reference Ϊ; f is early, and it needs to be added under the specific temperature conditions: voltage, that is, under low temperature conditions. Furthermore, each of the first reference voltage generating unit 2G and the second variable reference voltage generating unit are constituted by the temperature_positive state reference voltage generating unit, and when it is required to be reduced under the low temperature condition - the internal voltage Time. Furthermore, each of the first variable reference voltage generating unit 2A and the second variable reference voltage generating unit 3 is constituted by the temperature-independent type s reference voltage generating unit, and the demand thereof is that the maintenance-internal surface is required. Time, regardless of temperature changes. In particular, if the first variable reference voltage generating unit 2 is constituted by a temperature-inverse ratio type reference voltage generating unit, it increases a basic reference voltage VREF_BASE when operating under a low temperature condition, and outputs the increased Basic reference voltage. Therefore, the internal voltages VINT1 and VINTU are output by the first internal voltage generating unit 22, which is also outputted using a voltage level that is increased by an original voltage level. In addition, if the first variable reference voltage generating unit 20 is constituted by a temperature-proportional type reference voltage generating unit, it lowers the basic reference voltage 16 1303829 VREF-BASE and the internal voltage when operating under low temperature conditions. VINT1 and VINT11, and output the reduced basic reference voltage and internal voltage. Furthermore, if the first variable reference voltage generating unit 20 is constituted by a temperature independent type reference voltage generating unit, the basic reference voltage VREF_BASE and the internal voltages VINT1 and VINT11 are maintained at the original voltage level without any concern. temperature change. In the embodiment of the present invention shown in the eighth figure, a set of variable reference voltage generating unit 20, a first level shifter 21, a first internal voltage generating unit 22, and a second group are illustrated. The variable reference voltage generating unit 30, the second level shifter 31, and the second internal voltage generating unit 32. However, it must be understood that the specific embodiments described above are not limiting and are merely illustrative of the various aspects. That is, the number of combinations is increased or decreased depending on the number of internal voltages required. Since the preferred embodiments of the present invention will be described later, the detailed description of the structure of the eighth embodiment will be omitted. The principle and structure example of forming the temperature-ratio type reference voltage generating unit, the temperature-reverse 0 ratio type tang test voltage generating element or the temperature-independent type tang test voltage generating unit will refer to the ninth figure and the first Ten pictures are explained in detail. The ninth diagram is a circuit diagram illustrating the concept of the variable reference voltage generating unit shown in the eighth diagram. The tenth diagram is a circuit diagram illustrating the internal structure of the variable reference voltage generating unit shown in the eighth diagram. The variable reference voltage generating unit may be constituted by any one of a temperature-ratio type reference voltage generating unit, a temperature-inverse ratio type reference voltage generating unit, and a temperature-independent type reference voltage generating unit 17 1303829 includes a voltage generating unit 41 for generating a voltage according to a first temperature coefficient, a multiplier 42 multiplying the output of the voltage generating unit 41 by a proportional constant K, a bipolar junction transistor BJT 43, It can generate a voltage VBE according to a second temperature coefficient, and an adder 44 can be added to the output of the multiplier 42 to the output of the BJT 43, and output a reference voltage VREFJBASE, as shown in the ninth figure. At this time, the reference voltage VREF_BASE is defined by the following Equation 1. •[Formula 1]

VREF—BASE = VBE + K * VTHERM In this example, the temperature coefficient of a base-emitter voltage VBE is approximately -2.2 mV/°C, and the temperature coefficient of a VTHERM component is approximately + 0.085 mV/°C. Therefore, the variable reference voltage generating unit can be generated by the following temperature-ratio analog type reference voltage generating unit, temperature-inverse ratio type reference voltage generating unit, and temperature-independent type reference voltage φ by adjusting the proportional constant K Any of the units. The tenth figure is a diagram of a case in which the concept of the variable reference voltage generating unit shown in FIG. 9 is applied to an actual circuit. In the tenth diagram, the variable reference voltage generating unit has the following structure. That is, the variable reference voltage generating unit includes a first transistor 51 and a first resistor R1 that connects one end to the emitter of the first transistor 51, and the second and third resistors R2 and R3. Connected to each other in series, and connected in parallel to the other end of the first resistor R1, a second transistor 52 having an emitter connected to the third resistor R3, and a comparator 53 having a non-inverting terminal + connected to A connection node at the other end of the first resistor R1 18 1303829, an emitter of the first transistor 51, and a reverse terminal are connected to the connection node of the second resistor R2 and the third resistor R3. The turn of the comparator 53 is fed back to the first resistor R1 and the second resistor R2. At this time, the reference voltage VREF_BASE is defined by the following Equation 2. [Expression 2] VREF_BASE = VBE + (1+ R2/R3)ln(n) * Vtherm In this example, the value of n of the second transistor 52 is referred to an emitter size and the first transistor 51. The ratio, and, (1 + R2/R3) ln(n), corresponds to the proportional constant 'κ' in Equation 1. Therefore, it is possible for the designer to adjust the values of 'R3' and 'n' using the following temperature_proportional type reference voltage to generate a single, ^-inverse-ratio type reference voltage generating unit and a temperature_independent type reference. Any one of the single το is generated to construct a reference voltage generating unit. Next, the internal voltage generating device according to each of the preferred embodiments of the present invention will be described with reference to the attached drawings. 11 is a circuit diagram of an internal voltage generator of a semiconductor product according to a first embodiment of the present invention, and a circuit diagram of a voltage generator of a semiconductor integrated circuit of a twelfth embodiment-specific embodiment 2 is a circuit diagram of an internal voltage generator of a semiconductor integrated circuit according to a third embodiment of the present invention. First Embodiment The structure of the first embodiment of the present invention is such that both the low-temperature condition 'cell voltage VC〇RE and an elevated voltage νρρ increase, and a base 19 • 1303829 plate bias voltage VBB decreases. As shown in Fig. 11, the internal voltage generator of the semiconductor body circuit according to the first embodiment of the present invention has the following structure. That is to say, the internal voltage generator of the second semiconductor integrated circuit includes a temperature_inverse ratio "> test voltage generating unit 60, which generates an increase-base reference voltage VREF_BASE1 when the temperature rises; a quasi-offset 61, the basin is convertible by the temperature-inverse ratio type reference voltage generating unit 60, the base φ, the reference voltage VREF_BASE1 becomes a cell voltage generating reference voltage and an elevated voltage generating a reference voltage vre" The bean (four) voltage generating unit 62 generates a cell voltage VCQRE and rises by using the cell voltage generating reference voltage W_C and the boosted voltage outputted by the first-level shifter 61 to generate the reference voltage VREF-P. Voltage--temperature-proportional type reference house generates a single $70, which produces a -lower basic reference voltage when the temperature is lowered; - second level offsets crying 71' which can be converted by the temperature proportional type reference The voltage generating unit 7 outputs a basic reference voltage VREF_BASE2 of φ to become a substrate bias voltage generating reference voltage VREF-B, and outputs it; and a second internal voltage generating unit 72' The substrate bias voltage VBB is generated by generating the reference voltage VREF-B using the substrate bias voltage outputted by the second level shifter 71. The temperature-inverse ratio type reference voltage generating unit 6 is used as shown in FIG. According to this configuration, in order to satisfy the characteristics of the temperature_inverse ratio type, the impedances of the second resistor R2 and the third resistor R3, and the emitter size n of the second transistor 52 are adjusted. The first internal voltage generating unit 62 includes a comparator 62-1 having a reverse terminal for receiving a cell voltage output by the first level shifter 61. A reference voltage VREF_C is generated; - a transistor 62-2 having a gate receiving the output of the comparator 62-1, and converting an external voltage VDD according to the gate level to output a cell voltage VCORE, while allowing the The cell voltage is fed back to the non-inverting terminal + of the comparator 62-1, and a boosted voltage detector 62-3 detects the generated voltage generated by the first level shifter 61. Reference voltage VREF_P level, and output a boosted voltage pump enable letter And a booster voltage pump 62-4 driven by the boosted voltage pump enable signal and extracting the boosted voltage VPP. The temperature-proportional type reference voltage generating unit uses the configuration as shown in FIG. According to this configuration, in order to satisfy the characteristic of the temperature-ratio type, the impedances of the second resistor R2 and the third resistor R3, and the emitter size η of the second transistor 52 are adjusted to have a positive temperature. The second internal voltage generating unit 72 includes a comparator 72-1 having a reverse terminal for receiving a substrate bias voltage generating reference voltage VREF_B outputted by the second level shifter 71; The transistor 72-2 has a gate receiving the output of the comparator 72-1, and it converts an external voltage VDD according to the gate level to output a converted voltage, and allows the converted voltage to be fed back. Returning to the non-inverting terminal of the comparator 72-1; a substrate bias voltage detector 72-3, which can detect the level of a voltage outputted by the transistor 72-2 and output a substrate bias An electric pump enable signal; and a substrate bias voltage pump 72-4 Substrate bias voltage pump drive enable signal, and extracting the substrate bias voltage VBB. 21 1303829 The operation of the internal voltage generator of the semiconductor integrated circuit according to the first embodiment of the present invention having the above structure is explained below. - First, when the temperature drops, the temperature-inverse ratio type reference voltage generating unit 60 outputs a basic reference voltage VREF BASE: 1 which is increased by the basic reference voltage before the temperature drops. The subsequent bit shifter 61 converts the basic reference voltage VREF_BASE1 into a cell voltage generating reference voltage vref_〇 and a rising voltage generating reference voltage VREF__P, and outputs it. At this time, since the basic reference voltage VREFJBASE1 is increased by an original basic reference voltage, the cell voltage generating reference voltage VREF_C and the boosting voltage generating reference voltage VREFJP are also increased in proportion to the base reference voltage which has been increased. Further, the internal voltage generating unit 62 generates a cell voltage VCORE and a boosted voltage VPP by generating the reference voltage VREF_C using the increased cell voltage and generating the reference voltage VREF_P. At this time, since the cell voltage generation reference voltage VREF-C and the boost voltage generation reference voltage VREFJP are both increased, the cell voltage VCORE and the boosted voltage vpp are also proportional to the increased cell voltage generation reference voltage VREF c and the boost voltage generation reference. The voltage VREF_P increases. At the same time, when the temperature drops, the temperature-ratio type reference voltage generating unit 70 outputs a basic reference voltage VREF_BASE2 which is lowered by the basic reference voltage before the temperature drops. Then, the second level shifter 71 converts the basic reference voltage VREF_BASE2 into a substrate bias voltage generating reference voltage 22 1303829 VREF_B, and outputs it. At this time, since the basic reference voltage VREF_BASE2 is lowered by an original basic reference voltage, the substrate bias voltage generation reference voltage VREF_B is also lowered in proportion to the fundamental reference voltage which has been lowered. Further, the second internal voltage generating unit 72 generates a substrate bias voltage VBB by generating the reference voltage VREF_B using the substrate bias voltage which has been lowered. I at this time 'the reference voltage VREF_B is lowered because the substrate bias voltage is lowered'. The substrate bias voltage VBB is also lowered in proportion to the already lower substrate bias voltage generating reference voltage VREFJB. Therefore, the current driveability of an NMOS transistor in a semiconductor integrated circuit cell is lowered under low temperature conditions. However, according to the first embodiment of the present invention, the cell voltage VCORE and the boosted voltage VPP increase, that is, a driving voltage is increased, so that the driving force of the NMOS transistor can be improved. Further, the substrate bias voltage VBB is lowered, that is, the threshold voltage of φ is lowered, so that the driving force of the NMOS transistor can be improved. Therefore, normal operation can be performed. Second Embodiment The second embodiment of the present invention is structured such that a cell voltage VCORE and a boosted voltage VPP are maintained at predetermined values irrespective of temperature changes, and a substrate bias voltage VBB is lowered. As shown in Fig. 12, the internal voltage generator of the semiconductor body circuit according to the second embodiment of the present invention has the following structure. That is 23 1303829

It is said that the internal voltage generator of a semiconductor integrated circuit includes a type of digital voltage generating unit 80' which can generate a constant basic reference voltage VREF_BASE without any change in temperature; the first level shifter 81' Converting the basic reference voltage VREF_BASm outputted by the temperature-independent type reference voltage generating unit (10) into a cell voltage generating reference voltage VREF-c and increasing the reference voltage p, and outputting the basin; - the first internal voltage is generated 2, which generates a reference voltage V10_C by using a cell voltage outputted by the first level shifter 81, and generates a reference voltage VREF_P to generate a cell voltage and a voltage VPP; a proportional type reference voltage generating unit 90 which generates a base reference voltage which is lowered when the temperature is lowered; a second level offset $91' which is converted by the temperature/ratio type reference voltage generating unit 90 - the basic reference voltage VREF_BASE2 becomes - the substrate bias voltage is generated, the test voltage VREF - B' is output and is output; and - the second internal voltage is produced early &< 92, which is used by the second level offset Biasing the substrate 91 outputted t VKEF-Β generates the substrate bias voltage. - The temperature-independent type reference voltage generating unit (9) uses the group evil as = in the tenth figure. According to this configuration, in order to satisfy the temperature-independent type characteristic, the impedances of the second resistor R2 and the third resistor R3, and the emitters of the second transistor ^ are all adjusted, thereby having a temperature coefficient 〇 . The first internal voltage generating unit 82 may have the same structure as the first internal electric generating unit 62 according to the tenth embodiment of the present invention. Therefore, the detailed description will be omitted. The temperature-ratio type reference voltage generating unit 9G uses the group of 24 1303829 VIII as shown in the tenth figure. According to this configuration, in order to satisfy the temperature-ratio mode, the impedance of the second resistor R2 and the third resistor R3, and the emitter size n of the second transistor 52 are adjusted to have a positive temperature coefficient. . A second internal voltage generating unit 92 may have the same structure as the second internal voltage generating unit 72' of the first embodiment of the present invention according to the eleventh drawing. Therefore, the detailed description thereof will be omitted. - The operation of the internal voltage generator of the semiconductor φ integrated circuit according to the second embodiment of the present invention having the above structure is as follows. First, the temperature-independent type reference voltage generating unit 8 outputs a predetermined basic reference voltage VREF_BASE1 regardless of the temperature change. Then, the first level shifter 81 converts the basic reference voltage VREF_BASE1 into a cell voltage generating reference voltage vREF-c and a rising voltage generating reference voltage VREF_p, and outputs it. At this time, since the basic reference voltage VREF-BASE1 is constant, regardless of the temperature change, the voltage of the cell voltage generation reference voltage VREF-C and the boosted voltage production reference voltage VREFjp are also maintained at a ratio proportional to the basic reference voltage. One of the predetermined output levels. Further, the first internal voltage generating unit 82 generates a cell voltage VCORE and a boosted voltage VPP by using the cell voltage generating reference voltage [VREF~C and the rising south voltage generating reference voltage VREFJP. At this time, since each of the voltages of the reference voltage VREF-C and the boosted voltage generating reference voltage VREF-P is determined, each of the cell voltage VCORE and the rising_vpp is maintained at a predetermined time. Output level. 25 1303829 Meanwhile, when the temperature is lowered, the temperature_proportional type reference voltage generating unit 90 outputs a basic reference voltage VREF_BASE2 which is lowered by the basic reference voltage before the temperature falls. Then, the second level shifter 91 converts the basic reference voltage VREF_BASE2 into a substrate bias voltage generation reference voltage - VREFJB, and outputs it. • At this time, since the basic reference voltage VREF_BASE2 is lowered by a raw reference voltage, the substrate bias voltage generation reference voltage VREFJB is also lowered in proportion to the fundamental reference voltage that has been lowered. Further, the second internal voltage generating unit 92 generates a substrate bias voltage VBB by generating the reference voltage VREF_B using the substrate bias voltage which has been lowered. At this time, since the substrate bias voltage generation reference voltage VREF B is lowered, the substrate bias voltage VBB is also lowered in proportion to the substrate bias voltage which has been lowered to generate the reference voltage VREFJB. Therefore, the current driveability of an NMOS transistor in a semiconductor integrated circuit cell is lowered under low temperature conditions. However, according to the second embodiment of the present invention, the substrate bias voltage VBB is lowered, that is, the threshold voltage is lowered, so that the driving force of the NMOS transistor can be improved, and normal operation can be performed. Third Embodiment The structure of the third embodiment of the present invention is such that a cell voltage VCORE and a boosted voltage VPP are increased under a low temperature condition, and a substrate 26 1303829 plate bias voltage VBB is maintained at a predetermined value. And nothing about temperature changes. As shown in Fig. 13, the internal voltage generator of the semiconductor body circuit according to the third embodiment of the present invention has the following structure. That is, the internal voltage generator of a semiconductor integrated circuit includes a temperature-inverse ratio type reference voltage generating unit 100, which generates an increased basic reference voltage VREF_BASE1 when the temperature drops; The shifter 101 converts the basic reference voltage VREF_BASE1 outputted by the temperature-inverse ratio type reference voltage generating unit 100 into a cell voltage generating reference voltage VREF_C and a boosting voltage generating reference voltage VREF_P, and outputs the same; The first internal voltage generating unit 102 generates the cell voltage VCORE and the boosted voltage VPP by using the cell voltage generated by the first level shifter 101 to generate the reference voltage VREF_C and the boosted voltage generating reference voltage VREFJP; An irrelevant type reference voltage generating unit 110 which generates a predetermined basic reference voltage irrespective of temperature change; a φ second level shifter 111 convertible by a temperature-independent type reference voltage generating unit A basic reference voltage VREF-BASE2 of the 110 output becomes a substrate bias voltage generating reference voltage VREFJB, and outputs it; and a second The internal voltage generating unit 112 generates the substrate bias voltage VBB using the substrate bias voltage generated by the second level shifter 111 to generate the reference voltage VREF_B. The temperature-inverse ratio type reference voltage generating unit 100 uses the configuration as shown in the tenth diagram. According to this configuration, in order to satisfy the temperature-inverse ratio characteristic, the impedances of the second resistor R2 and the third resistor R3, and the magnitude η of the emitter 27 1303829 of the second transistor 52 are adjusted to have a negative temperature coefficient. The first internal voltage generating unit 102 may have the same structure as the first internal voltage generating unit 62 according to the first embodiment of the present invention in the eleventh drawing. Therefore, the detailed description will be omitted. The temperature_independent type reference voltage generating unit 110 uses the configuration as shown in the tenth figure. According to this configuration, in order to satisfy the temperature-independent type characteristic, the impedances of the second resistor R2 and the third resistor R3, and the emitter size η of the second transistor 52 are adjusted to have a temperature coefficient of zero. The second internal voltage generating unit 112 may have the same structure as the second internal voltage generating unit 72 of the first embodiment of the present invention shown in the eleventh diagram. Therefore, the detailed description thereof will be omitted. The operation of the internal voltage generator of the semiconductor integrated circuit according to the third embodiment of the present invention having the above structure will be explained below. First, when the temperature drops, the temperature-inverse ratio type reference voltage generating unit 100 outputs a basic reference voltage VREF_BASE1 which is increased by the basic reference voltage before the temperature drops. Then, the first level shifter 101 converts the basic reference voltage VREF_BASE1 into a cell voltage generating reference voltage VREF-C and a rising voltage generating reference voltage VREFJP, and outputs it. At this time, since the basic reference voltage VREF_BASE1 is increased by the original basic reference voltage, the cell voltage generation reference voltage VREF_C and the boosted voltage generation reference voltage VREF_P are also increased in proportion to the base reference voltage which has been increased. Further, the first internal voltage generating unit 102 generates a cell voltage vc〇RE and a boosted voltage vpp by generating the reference voltage VREF_c and the boosted voltage generating reference voltage VREF_P using the cell voltage which has been increased by 28 1303829. At this time, since the cell voltage generating reference voltage VREF-c and the boosting voltage generating reference voltage VREF-P are both increased, the cell voltage Vc〇RE and the boosting voltage vpp are also proportional to the increased cell voltage to generate the reference voltage. It increases with the boost voltage generating the reference voltage VREF_p. At the same time, the temperature-independent type reference voltage generating unit 11 outputs a predetermined basic reference voltage VREFJBASE2 regardless of the temperature change. Then, the second level shifter m converts the basic reference voltage VREF_BASE2 into a substrate bias voltage generating reference voltage VREF_B, and outputs it. At this time, since the basic reference voltage VREFjBASE2 is constant irrespective of the temperature change, the substrate bias voltage generation reference voltage VREFjb can also be maintained at a predetermined level proportional to the basic reference voltage. Further, the second internal voltage generating unit 112 generates the substrate bias voltage VBB by generating the McCaw voltage VREFJB using the substrate bias voltage. At this time, since the substrate bias voltage generation reference voltage VREF_B is constant, the substrate bias voltage VBB can also be maintained at a predetermined level proportional to the substrate bias voltage generation reference voltage VREFJB. Therefore, the transistor driving force of an NMOS transistor in a semiconductor integrated circuit cell is lowered under low temperature conditions. However, according to the third embodiment of the present invention, both the cell voltage VCORE and the boosted voltage VPP are increased, that is, the driving voltage is increased, so that the driving force of the NMQS transistor can be improved. In addition, the substrate bias voltage Vbb can be prevented from increasing, that is, 29 1303829, the threshold voltage can be prevented from increasing, so that the driving force of the NMOS transistor can be improved, which allows a normal operation to be performed. It will be appreciated that various modifications and changes can be made by those skilled in the art without departing from the scope and spirit of the invention. Therefore, it should be understood that the specific embodiments described above are not limiting, but rather are illustrated in various aspects. The scope of the present invention is defined by the scope of the appended claims, and is not defined by the foregoing description, and all such changes and modifications are within the scope and scope of the scope of the claims. All are covered by the scope of these patent applications. In accordance with these embodiments of the present invention, an internal voltage generator of a semiconductor integrated circuit can independently control the boost voltage, the cell voltage, and the substrate bias voltage in accordance with temperature conditions. Therefore, the internal voltage generator of a semiconductor integrated circuit can achieve the following effects; first, it is possible to prevent the performance of the semiconductor integrated circuit from being lowered due to temperature variations. φ Second, it is possible to design a semiconductor integrated circuit that is immune to variations in component characteristics; that is, it can operate normally under severe environmental changes. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described with reference to the accompanying drawings, in which like numerals represent like elements, in which: FIG. 1 is a configuration diagram of a conventional memory cell structure; The ratio of the different voltages in the integrated circuit is 30 1303829. The third figure is a circuit diagram of an internal voltage generating circuit of the semiconductor integrated circuit according to the related art; the fourth figure is one of the ones shown in the third figure. Circuit diagram of the internal structure of the substrate bias voltage detector; Fig. 5 is a circuit diagram of the internal structure of one of the boosted voltage detectors shown in the third figure, and the sixth figure is in the reference voltage according to the related art. The pattern of the change; the seventh figure is a diagram of the internal voltage demand condition under a low temperature condition, and the eighth figure is an illustration of the concept of the internal voltage generator of the semiconductor integrated circuit according to an embodiment of the present invention. FIG. 9 is a circuit diagram illustrating a concept of a variable reference voltage generating unit shown in FIG. 8; FIG. 11 is a diagram showing a variable reference power shown in FIG. A circuit diagram for generating an internal structure of a unit Φ; FIG. 11 is a circuit diagram illustrating an internal voltage generator of a semiconductor integrated circuit according to a first embodiment of the present invention; and FIG. 12 is a second specific embodiment of the present invention A circuit diagram of an internal voltage generator of a semiconductor integrated circuit of an embodiment; and a thirteenth diagram is a circuit diagram illustrating an internal voltage generator of a semiconductor integrated circuit according to a third embodiment of the present invention. [Main component symbol description] 31 1303829 10 Reference voltage generating unit 11 First bit shifting device 12 Cell voltage generating unit 12-1 Comparator 12-2 Transistor 13 Substrate bias voltage generating unit 13-1 Comparator 13- 2 Transistor® 13-3 VBB detector 13-4 VBB pump 14 boost voltage generating unit 14-1 VPP detector 14-2 VPP pump 20 first variable reference voltage generating unit 21 first bit shift • 22 first internal voltage generating unit 22-1 comparator 22-2 transistor 22-3 detector 22-4 pump 30 second variable reference voltage generating unit 31 second level shifter 32 second internal Voltage generating unit 32-1 comparator 32 1303829

32-2 Transistor 32-3 Detector 32-4 Pump 41 Voltage Generation Unit 42 Multiplier 43 Transistor B JT 44 Adder 51 First Transistor 52 Second Transistor 53 Comparator 60 Temperature-Inverse Ratio Reference Voltage generating unit 61 first bit shifter 70 temperature_proportional type reference voltage generating unit 71 second level shifter 62 first internal voltage generating unit 62-1 comparator 62-2 transistor 62-3 VPP Detector 62-4 VPP pump 72 Second internal voltage generating unit 72-1 Comparator 72-2 Transistor 72-3 VBB detector 72-4 VBB pump 33 1303829 80 Temperature-independent type reference voltage generating unit 81 First quasi-offset 90 temperature-proportional type reference voltage generating unit 91 second level shifter 82 first internal voltage generating unit 82-1 comparator 82-2 transistor 82-3 VPP detector® 82-4 VPP pump 92 Second internal voltage generating unit 92-1 Comparator 92-2 Transistor 92-3 VBB detector 92-4 VBB pump

34

Claims (1)

1303829 Is the year? Revised this month, the patent application scope: 1. An internal voltage generator of a semiconductor integrated circuit, which uses a voltage generated by converting an external voltage into at least one internal voltage, and the internal voltage of the semiconductor integrated circuit is generated. The device includes: at least one variable reference voltage generating unit for generating an increased or decreased basic reference voltage obtained according to a change in temperature; at least one quasi-offset unit for converting the The basic reference voltage > becomes at least one reference voltage, and outputs the at least one reference voltage, wherein the basic reference voltage is output by the at least one variable reference voltage generating unit, the reference voltage is used to generate an internal voltage; and at least one An internal voltage generating unit configured to generate an internal voltage by the at least one reference voltage to generate an internal voltage output by the at least one quasi-offset unit. 2. The internal voltage production of a semiconductor integrated circuit according to claim 1, wherein the variable reference voltage generating unit is one of any one of the following, a temperature-proportional type reference voltage generating unit, a temperature-inverse ratio type reference voltage generating unit having an output level that rises according to a temperature rise, or an output level that is lowered according to a temperature rise, or a temperature-independent type reference voltage generating unit, It maintains a predetermined output level regardless of temperature changes. 3. An internal voltage generator of a semiconductor integrated circuit, which uses a cell voltage generated by converting an external voltage, a boosted voltage, and a substrate bias voltage 35 1303829 as an internal voltage, the semiconductor integrated circuit The internal voltage generator comprises: a temperature-inverse ratio type reference voltage generating unit for raising a first basic reference voltage generated based on the temperature drop; a first level shifting unit coupled to the temperature - An inverse type reference voltage generating unit, configured to convert the first basic reference voltage into a cell voltage generating reference voltage, and a boosting voltage to generate a reference voltage, wherein 'the first basic reference voltage is referenced by the temperature-inverse ratio type a voltage generating unit output; a first internal voltage generating unit coupled to the first level shifting unit for generating the cell voltage and the boosted voltage, wherein the cell voltage and the boosted voltage are Generating a reference voltage based on the cell voltage and generating the reference voltage to generate a reference voltage; a temperature-proportional type reference voltage generating unit, And a second base reference voltage for generating a decrease, wherein the reduced second basic reference voltage is generated according to a temperature drop; and a second level offset unit coupled to the temperature-proportional type reference a voltage generating unit for converting the second basic reference voltage into a substrate bias voltage generating reference voltage, wherein the second basic reference voltage is output by the temperature-ratio analog type reference voltage generating unit; and a second internal voltage a generating unit coupled to the second level shifting unit and configured to generate the substrate bias voltage, wherein the substrate bias voltage is generated based on the substrate bias voltage generating a reference voltage. 4. The internal voltage of the semiconductor integrated circuit of claim 3, wherein the temperature-inverse ratio type reference voltage generating unit comprises: a first transistor having an emitter; a resistor coupled to the emitter of the first transistor at a first connection node; second and third resistors coupled in series with each other at a second connection node, and coupled in parallel to the first resistor; a second transistor having an emitter coupled to the third resistor; 0 and a comparator having a non-inverting terminal, a reverse terminal, and an output terminal 'where the non-inverting terminal is engaged The first connection node, the reverse terminal is coupled to the second connection node, and the output terminal is coupled to the first resistor and the second resistor. 5. The internal voltage generator of the semiconductor integrated circuit of claim 4, wherein φ, the impedance of the second resistor and the third resistor is selected, and the size of the second transistor is 'this temperature' The inverse ratio type reference voltage generating unit has a negative temperature coefficient. 6. The internal voltage generator of the semiconductor integrated circuit of claim 3, wherein the temperature is proportional to the sad reference voltage generating element comprises: a first transistor having an emitter; a first resistor; It is coupled to the emitter of the first transistor at a first connection node, 37 1303829 second and third resistors, which are coupled in series with each other at a second connection node and coupled in parallel to the first resistor; a second transistor having an emitter coupled to the third resistor; and a comparator having a non-inverting terminal, a reverse terminal, and an output terminal, wherein the non-inverting terminal is coupled to the first connection The node, the reverse terminal is coupled to the second resistor and the second connection node of the third resistor, and the output terminal is coupled to the first resistor and the second resistor. 7. The internal voltage generator of the semiconductor integrated circuit of claim 6, wherein the impedance of the second resistor and the third resistor is selected, and the size of the second transistor is such that the temperature-proportional type The state reference voltage generating unit has a positive temperature coefficient. 8. The internal voltage generator of the semiconductor integrated circuit of claim 3, wherein the first internal voltage generating unit comprises: a comparator having a reverse terminal and a non-inverting terminal, and Receiving the cell voltage through the reverse terminal to generate a reference voltage to generate an output, wherein the cell voltage generating reference voltage is output by the first level shifting unit; a transistor having a gate and using Receiving an output of the comparator via the gate, and converting the external voltage according to a voltage level at the gate to output the cell voltage, and wherein the cell voltage provides 38 1303829 to the non-the comparator a reverse voltage terminal; a rising voltage detector, the handle is coupled to the first level shifting unit, and is configured to detect a level of the reference voltage generated by the boosted voltage, and output a boosted voltage pump An energy signal, wherein the level is output by the first level offset unit; and a boost voltage pump coupled to the boost voltage detector driven by the boosted voltage pump enable signal , The voltage increase for drawing. B. The internal voltage generator of the semiconductor integrated circuit of claim 3, wherein the second internal voltage generating unit comprises: a comparator having a reverse terminal, a non-inverting terminal, and a And outputting, by the reverse terminal, the substrate bias voltage to generate a reference voltage, wherein the substrate bias voltage generating reference voltage is output by the second level shifting unit; p—the transistor having a gate a gate coupled to the output of the comparator and configured to convert the external voltage and output the converted voltage, and wherein the converted voltage is provided to the non-inverting terminal of the comparator, wherein the external voltage The conversion is based on a voltage level at the gate; a substrate bias voltage detector coupled to the transistor and used to detect a level of the voltage to output a substrate bias a voltage pump enable signal, wherein the level is output by the first level shifting unit; and a substrate bias voltage pump coupled to the substrate bias voltage detecting 39 1303829, Enable signal is driven by the substrate bias voltage pump, and for drawing the substrate bias voltage. Ίο. An internal voltage generator of a semiconductor integrated circuit that uses a cell voltage, a boosted voltage, and a substrate bias voltage generated by converting an external voltage as an internal voltage, and an internal voltage of the semiconductor integrated circuit The generator comprises: a temperature-independent type reference voltage generating unit for generating a predetermined first reference voltage without a temperature change; B. - a first level shifting unit coupled to The temperature-independent type reference voltage generating unit is configured to convert the first basic reference voltage into a cell voltage generating reference voltage and a boosting voltage generating reference voltage, wherein the first basic reference voltage is determined by the temperature-independent type a state reference voltage generating unit output; a first internal voltage generating unit coupled to the first level shifting unit, and configured to generate a reference voltage using the cell voltage generating reference voltage and the boosted electric p voltage to generate the a cell voltage and the boosted voltage, wherein the cell voltage generates a reference voltage and the boosted voltage generates a reference voltage from the first level a shifting unit output; a temperature-ratio type reference voltage generating unit for generating a reduced second base reference voltage, wherein the reduced second base reference voltage is generated according to a temperature drop; An offset unit coupled to the temperature-proportional type reference voltage generating unit and configured to convert the second base reference voltage into a substrate bias voltage generating reference voltage, wherein 'the second basic 爹 40 13 03 829 , The temperature-proportional type reference power unit output; the second internal voltage generating unit of the second electrode is coupled to the second level by 7C, and the reference electric grind is generated by using the substrate repeatedly. The board voltage, wherein the substrate is generated by the second level shifting unit. = = internal electrical waste of the semiconductor integrated circuit of the patent range H): the temperature-ratio type reference electrical waste generating unit comprises: a transistor having an emitter, a first resistor, a first connection body of the emitter; a node _ in combination with the first electrical second and third resistors, in a second rotation, and coupled in parallel to the first resistor; Compensating for the series connection of the first connection node and the emitter of the resistor; a comparator having a non-inverting terminal, ~: a round-out terminal, wherein 'the non-inverting terminal is coupled to the second=: ", The reverse terminal is coupled to the second resistor and the connection, that is, the connection node, and the output terminal is coupled to the second resistor of the resistor, the resistor, and the second 12. The patent application is the nth item. a semiconductor product generator, an internal voltage of the I path, wherein 'selecting the second resistor and the third electroplate is resistant, and 41 1303829 the size of the second transistor is such that the temperature-proportional type reference voltage generating unit has Positive temperature coefficient 13. The internal voltage generator of the semiconductor integrated circuit of claim 10, wherein the temperature-independent type reference voltage generating unit comprises: a first transistor having an emitter; a first resistor Connected to the emitter of the first transistor at a first connection node; B second and third resistors coupled in series with each other at a second connection node and coupled in parallel to the first resistor; a second transistor having an emitter coupled to the third resistor; and a comparator having a non-inverting terminal, a reverse terminal, and an output terminal, wherein the non-inverting terminal is coupled to the first connection a node, the reverse terminal coupled to the second resistor and the second p-connection node of the third resistor, and the output terminal coupled to the first resistor and the second resistor. 14. A semiconductor according to claim 13 An internal voltage generator of the integrated circuit, wherein an impedance of the second resistor and the third resistor is selected, and a magnitude of a second transistor impedance of the second resistor and the third resistor, and The size of the second transistor is such that the temperature-independent type reference voltage generating unit has a zero temperature coefficient. 15. The internal voltage 42 1303829 generator of the semiconductor integrated circuit of claim 10, wherein the first The internal voltage generating unit includes: a comparator having a reverse terminal and a non-inverting terminal, and configured to receive the cell voltage through the reverse terminal to generate a reference voltage, and generate an output, wherein the cell voltage is generated The reference voltage is output by the first level shifting unit; a transistor having a gate. and receiving the output of the comparator via the gate, and converting the external voltage to output the battery B Pressing, and wherein the cell voltage is supplied to the non-inverting terminal of the comparator, wherein the conversion of the external voltage is based on a voltage level at the gate; a boosted voltage <detector 5 engaging in the first level shifting unit, and detecting a rising voltage to generate a reference voltage, and outputting a boosting voltage pump enabling signal, wherein the bit Outputted by the first level offset unit; and a p-rise voltage pump coupled to the boost voltage detector driven by the boosted voltage pump enable signal and used to extract the boost Voltage. The internal voltage generator of the semiconductor integrated circuit of claim 10, wherein the second internal voltage generating unit comprises: a comparator having a reverse terminal, a non-inverting terminal, and an output End, and receiving the substrate bias voltage via the reverse terminal to generate a reference voltage, wherein the substrate bias voltage generating reference voltage is output by the 4313303829 two-level offset unit; a transistor having a gate And coupled to the output of the comparator and configured to convert the external voltage according to a voltage level at the gate to output the converted voltage, and wherein the converted voltage is provided to the non-the comparator a reverse bias terminal; a substrate bias voltage detector coupled to the transistor and configured to detect a level of the voltage and output a substrate bias voltage pump enable signal, wherein the level is determined by the a transistor output; and a substrate bias voltage pump coupled to the substrate bias voltage detector driven by the substrate bias voltage pump enable signal and used for extraction Substrate bias voltage. 17. An internal voltage generator of a semiconductor integrated circuit, which uses a cell voltage generated by converting an external voltage, a boosted voltage, and a substrate bias voltage as internal voltages, and an internal voltage of the semiconductor integrated circuit The generator includes: a temperature-inverse ratio type reference voltage generating unit for generating a predetermined first reference voltage without a temperature change; a first level shifting unit coupled to the temperature An inverse ratio type reference voltage generating unit, configured to convert the first basic reference voltage into a cell voltage generating reference voltage and a boosting voltage generating reference voltage, wherein the first basic reference voltage is referenced by the temperature-inverse ratio type a voltage generating unit output; a first internal voltage generating unit coupled to the first level shifting unit, and configured to generate a reference voltage using the cell voltage and the boosting power 44 1303829 to generate a reference see m to generate the a cell voltage and the boosted voltage, wherein the cell voltage produces a reference electrical point, and the boosted electrical susceptibility reference is shifted by the first level a unit output; a temperature-independent type reference voltage generating unit for generating a reduced second basic reference turn, wherein the reduced second basic reference voltage is generated according to a temperature drop; a unit coupled to the temperature-independent type reference electrical occupation unit and configured to convert the second base reference to a substrate bias electrical reference voltage, wherein the second reference electrical a proportional type reference voltage generating unit output; and a second internal voltage generating unit coupled to the second level #私皂7L' and generating a reference voltage by using the substrate bias voltage: two reverse bias Voltage 'where the substrate bias voltage produces a reference electrical history output by the second level shifting unit. 18. The paste within the semiconductor integrated circuit of claim 17 wherein the temperature-inverse ratio type reference voltage generating unit comprises: a first transistor having an emitter; and a first resistor 'is in- The first is connected to the emitter of the node crystal; π is the second and third resistor of the second pen, which is lightly coupled in a first-to-far ,, W is coupled to the fresh-resistance point and is connected in series with each other. An emitter of the third resistor; 45 1303829 and a comparator having a non-inverting terminal, a reverse terminal, and an output terminal, wherein the non-inverting terminal is coupled to the first connecting node, the reverse The terminal is coupled to the second resistor and the second connection node of the third resistor and the output terminal is coupled to the first resistor and the second resistor. 19. The internal voltage generator of the semiconductor integrated circuit of claim 18, wherein the impedance of the second resistor and the third resistor is selected, and the temperature of the second transistor is such that the temperature is - The inverse ratio type reference voltage generating unit has a negative temperature coefficient. 20. The internal voltage generator of the semiconductor integrated circuit of claim 17, wherein the temperature-independent type reference voltage generating element comprises: a first transistor having an emitter; n a first a resistor coupled to the emitter of the first transistor at a first connection node, and second and third resistors coupled in series with each other at a second connection node and coupled in parallel to the first resistor; a second transistor having an emitter coupled to the third resistor; and a comparator having a non-inverting terminal, a reverse terminal, and an output terminal, wherein the non-inverting terminal is coupled to the first connection The node, the reverse terminal is coupled to the second resistor and the second resistor 46 1303829. The connection node and the output terminal are coupled to the first resistor and the second resistor. 21. The internal voltage generator of the semiconductor integrated circuit of claim 20, wherein selecting the impedance of the second resistor and the third resistor and the size of the second transistor make the temperature-independent type The sad reference voltage production unit has a zero temperature coefficient. 22. The internal voltage generator of the semiconductor integrated circuit of claim 17, wherein the first internal voltage generating unit comprises a comparator having a reverse terminal and a non-inverting terminal, and Receiving the cell voltage through the reverse terminal to generate a reference voltage, and generating an output, wherein the cell voltage generating reference voltage is output by the first level shifting unit; a transistor having a gate and using Receiving φ the output of the comparator via the gate, and converting the external voltage according to a voltage level at the gate to output the cell voltage, and wherein the cell voltage is provided to the non-reverse of the comparator a rising voltage detector coupled to the first level offset single: element and used to detect the boost voltage to generate a reference voltage, and " output a boost voltage pump An enable signal, wherein the level is output by the first level offset unit; and a boost voltage pump coupled to the boost voltage detector by the boosted voltage pump enable signal Drive, and Used to extract the boosted electricity 47 13〇3829 pressure. The internal internal voltage of the 17-member body is as follows: For example, the second internal voltage generating unit includes: a ratio (4) having a reverse terminal, a non-inverting terminal, and an output terminal. And receiving, by the reverse terminal, the substrate bias voltage to generate a reference voltage, wherein the substrate bias voltage generating reference voltage is output by the first-level offset unit; ........:奉 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该A substrate bias voltage is detected by the crying recognition, μ is coupled to the transistor, and depends on detecting a certain level of the voltage, and the output is a substrate bias voltage pump to cause paraplegia唬, wherein the level is rotated by the _ ^ tail ; body; and a substrate bias voltage pump, the initiator # ^ is recoupled to the substrate bias voltage swaying state 'it is biased by the substrate , ^ Earthpower S pump is driven by the signal, and the substrate is extracted by % Voltage.