TWI303541B - Electrically connecting method for blind holes of printed circuit board - Google Patents
Electrically connecting method for blind holes of printed circuit board Download PDFInfo
- Publication number
- TWI303541B TWI303541B TW94128331A TW94128331A TWI303541B TW I303541 B TWI303541 B TW I303541B TW 94128331 A TW94128331 A TW 94128331A TW 94128331 A TW94128331 A TW 94128331A TW I303541 B TWI303541 B TW I303541B
- Authority
- TW
- Taiwan
- Prior art keywords
- printed circuit
- circuit board
- conductive layer
- blind hole
- blind
- Prior art date
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
•1303541•1303541
【發明所屬之技術領域】 =發明係關於一種印刷電路板之盲孔導通方法,特別是 鳟罝在一印刷電路板之一盲孔利用電鍍方式,並藉由一保 -^之辅助遮蔽,以便在該盲孔内形成一電鍍導通體,並 乂 升盲孔導通品質之印刷電路板之盲孔導通方法。 【先前技術】 入驾用印刷電路板之盲孔導通方法,如第丨圖所示,其包 ^一絕緣層1及二導電層2。該絕緣層丨做為一基板,該導 :層2形成在該絕緣層1之二側。該二導電層2之絕緣層1係 _藉由f射鑽鑿形成一盲孔丨丨。該盲孔丨丨之孔壁首先利用濺 鍍或蒸鍍化學方式或其他化學氣相沉積方式預先形成一導 ,層1 2。接著’利用一般電鍍方式在該盲孔丨丨内及其開口 -端之,電層2上共同沉積形成一電鍍層21。在電鍍製程 ,上"亥導通層1 2可加速該盲孔11内之電鍵沉積效率,以提 升印聲電路板的製程效率。 然名’該盲孔11之開口端的導通層12常與該導電層2之 交界處相對形成較大電流匯集密度,因此使得該電鍍層21 以相對較快之速度沈積形成在該盲孔丨丨之開口處。結果, 该導通層1 2之設計反而造成該盲孔11内之填隙不完全,亦 #即該盲孔11内容易殘留形成一封閉孔洞22〔 v〇id〕。當印 刷電路板殘留過多之孔洞2 2時,其勢必影響該盲孔11的層 間導通品質,甚至降低其產品良率。基於上述原因,其確 貫仍有必要進一步改良上述印刷電路板之盲孔導通方法。 有鑑於此,本發明改良上述之缺點,其係利用一盲孔之TECHNICAL FIELD OF THE INVENTION The invention relates to a method for blind hole conduction of a printed circuit board, in particular, a blind hole in a printed circuit board is plated by an auxiliary method, and is shielded by an auxiliary shield. A method of forming a plated through-hole in the blind hole and raising the blind hole conducting method of the printed circuit board of the blind hole conduction quality is formed. [Prior Art] A blind hole conducting method for driving a printed circuit board, as shown in the figure, includes an insulating layer 1 and two conductive layers 2. The insulating layer is formed as a substrate, and the layer 2 is formed on both sides of the insulating layer 1. The insulating layer 1 of the two conductive layers 2 is formed by drilling a blind hole. The walls of the blind holes are first formed into a conductive layer 12 by sputtering or vapor deposition chemistry or other chemical vapor deposition. Then, a plating layer 21 is formed by common deposition on the electric layer 2 in the blind via and its open end. In the electroplating process, the upper layer 12 can accelerate the deposition efficiency of the key in the blind hole 11 to improve the process efficiency of the printed circuit board. The conduction layer 12 of the open end of the blind hole 11 often forms a large current collection density with respect to the interface of the conductive layer 2, so that the plating layer 21 is deposited at a relatively fast speed in the blind hole. The opening. As a result, the design of the conductive layer 12 causes the interstitial in the blind via 11 to be incomplete, and the closed via 22 is easily formed in the blind via 11 . When the printed circuit board has too many holes 2 2 remaining, it is bound to affect the interlayer conduction quality of the blind holes 11 and even reduce the yield of the product. For the above reasons, it is still necessary to further improve the blind hole conduction method of the above printed circuit board. In view of the above, the present invention improves the above disadvantages by utilizing a blind hole
C:\Logo-5\Five Continents\PK9781. ptd 第8頁 .1303541 五、發明說明(2) 封閉端的一導電層做為電鍍製程之電極,並藉由一保護罩 適當覆蓋該盲孔之開口端外緣的另一導電層。藉此,可確 保該保護罩控制形成一電鍍導通體,且可選擇使該電鍍導 通體形成凸塊,以做為焊塾或輸入/輸出端子。因此,本 發明確實可省略習用導通層成型步驟,以供有效減少盲孔 形成不良孔洞之機率,進而提升盲孔之層間導通品質及簡 化導電端子製程。 【發明内容】 本發明之主要目的係提供一種印刷電路板之盲孔導通方 >法’其利用一盲孔之封閉端的一導電層做為電鍍製程之電 極’以便該盲孔由該導電層開始電鍍沈積形成一電鍍導通 體’使本發明具有提升盲孔之層間導通品質之功效。 本發明之次要目的係提供一種印刷電路板之盲孔導通方 法,其利用一盲孔之封閉端的一導電層做為電鍍製.程之電 極’ #藉由一保護罩適當覆蓋該盲孔之開口端外緣的另_ 導電I,以便該保護罩控制形成一電鍍導通體,使本發明 具有提升盲孔之層間導通品質之功效。 本發明之另一目的係提供一種印刷電路板之盲孔導通方 法,其利用一盲孔之封閉端的一導電層做為電鍍製程之電 極,並藉由一保護罩適當覆蓋該盲孔之開口端外緣的另一 導電層,以便該保護罩控制形成一電鍍導通體,並選擇 該電鍍導通體製成一凸塊,以做為焊墊或輸入/輸出端. 〔I/O〕,使本發明具有簡化導電端子製程之功效。 根據本發明之印刷電路板之盲孔導通方法,其包含步C:\Logo-5\Five Continents\PK9781. ptd Page 8.1303541 V. INSTRUCTIONS (2) A conductive layer at the closed end is used as the electrode of the electroplating process, and the opening of the blind hole is appropriately covered by a protective cover Another conductive layer on the outer edge of the end. Thereby, it is ensured that the protective cover controls the formation of a plating via, and the plating via can be selected to form a bump as a solder or an input/output terminal. Therefore, the present invention can indeed omit the conventional conduction layer forming step for effectively reducing the probability of blind holes forming poor holes, thereby improving the interlayer conduction quality of the blind holes and simplifying the process of the conductive terminals. SUMMARY OF THE INVENTION The main object of the present invention is to provide a blind via conducting method for a printed circuit board, which utilizes a conductive layer of a closed end of a blind via as an electrode of an electroplating process so that the blind via is formed by the conductive layer Initiating electroplating deposition to form an electroplated via body' has the effect of improving the inter-layer conduction quality of the blind via. A secondary object of the present invention is to provide a blind via conduction method for a printed circuit board, which utilizes a conductive layer of a closed end of a blind via as an electrode for electroplating. # By properly covering the blind via a protective cover The other end of the open end is electrically conductive I so that the protective cover controls the formation of an electroplated conductive body, so that the present invention has the effect of improving the interlayer conduction quality of the blind via. Another object of the present invention is to provide a blind via conduction method for a printed circuit board, which utilizes a conductive layer of a closed end of a blind via as an electrode of an electroplating process, and appropriately covers an open end of the blind via with a protective cover Another conductive layer on the outer edge, so that the protective cover controls to form a plated through body, and the plated through body is selected to form a bump as a pad or an input/output terminal. [I/O], The invention has the effect of simplifying the process of the conductive terminal. A blind hole conducting method for a printed circuit board according to the present invention, comprising steps
C:\Logo-5\Five Continents\PK9781.ptd * 1303541 五、發明說明(3) 屛夕^结^、表層之一第一側形成一第一導電層,在該絕緣 I ^ _ 一側貫穿形成至少一盲孔;在該絕緣層之第二侧 ^一第二導電層及一保護罩,以覆蓋該第二導電層在該 道^之開口緣以外的區域;利用該絕緣層之第一側的第一 杰為電極,並進行電鍍製程,以便在該盲孔内沈積 時,二Ϊ鍍導通體;及當該電鍍導通體累積至填滿該盲孔 士 ’移除,保護罩;選擇研磨方式將電鍍導通體整平或製 描=塊。藉此,該盲孔利用該電鍍導通體形成一層間導通 稱造。 【實施方式】 且ί了讓本發明之上述及其他目&、特徵、優點能更明顯 易随,下文將特舉本發明較佳實施例,並配合所附圖式, 作詳細說明如下。 請參照第2及SA至Μ圖所示,本發明第一印刷 電路季之盲孔導通方法包含步驟: 〔1〕、在一絕緣層1之一第一侧及一第二側分別具有一 導電層2及2’ ,在該絕緣層!之第二側貫穿該導電層2,,以 形成至少一盲孔11 ; 、〔2〕、在該絕緣層i之第二側另設一保護罩3,以覆蓋 ►該導電層2’在該盲孔11之開口緣以外的區域; 〔3〕、利用該絕緣層i之第一側的導電層2做為電極, 並進行電鍍製程,以便在該盲孔丨丨内沈積形成一電鍍導通 體4 ; 〔4〕、當該電鍍導通體4累積至填滿該盲孔丨丨之開口端C:\Logo-5\Five Continents\PK9781.ptd * 1303541 V. Description of invention (3) The first side of one of the surface layers forms a first conductive layer, which runs through the side of the insulation I ^ _ Forming at least one blind hole; forming a second conductive layer and a protective cover on the second side of the insulating layer to cover the region of the second conductive layer outside the opening edge of the channel; using the first layer of the insulating layer The first side of the side is an electrode, and an electroplating process is performed to deposit a conductive body in the blind hole; and when the electroplated conductive body accumulates to fill the blind hole, the 'protection cover is removed; The grinding method flattens or forms the plated conductor. Thereby, the blind via uses the electroplated via to form an interlayer conduction. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent and obvious. Referring to FIGS. 2 and SA to FIG. 2, the blind hole conducting method of the first printed circuit of the present invention comprises the steps of: [1] having a conductive layer on one of the first side and the second side of the insulating layer 1, respectively. 2 and 2' in the insulation layer! The second side penetrates the conductive layer 2 to form at least one blind hole 11; [2], and a protective cover 3 is disposed on the second side of the insulating layer i to cover the conductive layer 2'. a region other than the opening edge of the blind hole 11; [3] using the conductive layer 2 on the first side of the insulating layer i as an electrode, and performing an electroplating process to deposit a plating via in the blind via 4; [4], when the plating via 4 is accumulated to fill the open end of the blind hole
1303541 五、發明說明(4) 後,移除覆蓋該導電層2’之保護罩3 ;及 〔5〕、選擇研磨方式將該電鍍導通體4整平或製成一凸 料40,藉此該盲孔11利用該電鍍導通體4導通該絕緣層1二 側的導電層2及2’ 。 請參照第2、3A及3B圖所示,本發明第一實施例之印刷 " 電路板之盲孔導通方法第一步驟係:在該絕緣層1之第一 側及第二側分別預製形成該導電層2及2,,以形成一基 板。在該絕緣層1之第二侧以雷射或機械鑽馨形成該盲孔 11。該絕緣層1及導電層2及2’係屬印刷電路板之習用構 •造’該絕緣層1較佳係可選自聚亞醯胺(p 〇 1 y i m i d e, PI〕、聚酯〔P 〇 1 y e a s t e r,P E T〕、聚對萘二甲酸乙二酯 〔Polyethylene naphtha late,PEN〕、液晶聚合物 ,〔Liquid Crystal Polymer,LCP〕或鐵氟龍〔Tef lon, 、等材質。該導電層2及2’係由適當導電金屬製成, 佳為銅箔層。該絕緣層1及導電層2及2 ’共同組成具有 一雙層銅箔基板。該絕緣層1之第二側(上側)係較隹藉 由雷射鑽鑿形成該盲孔11,該盲孔11較佳係呈寬口窄底之 倒梯形型態,即該盲孔較佳形成喇叭狀,以利後續進行電 鍍沈積。 鲁請參照第2及3C圖所示,本發明第一實施例之印刷電路 板之盲孔導通方法第二步驟係:在該絕緣層1之第二側另 設該保護罩3,以覆蓋該導電層2’在該盲孔11之開口緣以 外的區域。該保護罩3較佳係選自可重複回收使用之非金 «濟罩板,或可選自由光阻塗佈或乾膜壓著之方式製成。不1303541 5. After the invention description (4), the protective cover 3 covering the conductive layer 2' is removed; and [5], the plating method is selected to be flattened or made into a convex material 40, thereby The blind via 11 turns on the conductive layers 2 and 2' on both sides of the insulating layer 1 by the plating via 4. Referring to FIG. 2, FIG. 3A and FIG. 3B, the first step of the method for printing the blind hole of the printed circuit board according to the first embodiment of the present invention is: prefabricating on the first side and the second side of the insulating layer 1, respectively. The conductive layers 2 and 2 are formed to form a substrate. The blind hole 11 is formed on the second side of the insulating layer 1 by laser or mechanical drilling. The insulating layer 1 and the conductive layers 2 and 2' are conventional structures of the printed circuit board. The insulating layer 1 is preferably selected from the group consisting of polyamidoamine (PI) and polyester [P 〇 1 yeaster, PET], polyethylene naphtha late (PEN), liquid crystal polymer, [Liquid Crystal Polymer, LCP] or Teflon, Teflon, etc. The conductive layer 2 and 2' is made of a suitable conductive metal, preferably a copper foil layer. The insulating layer 1 and the conductive layers 2 and 2' are combined to have a double-layer copper foil substrate. The second side (upper side) of the insulating layer 1 is The blind hole 11 is formed by laser drilling, and the blind hole 11 is preferably an inverted trapezoidal shape with a wide mouth and a narrow bottom, that is, the blind hole is preferably formed into a trumpet shape for subsequent electroplating deposition. Referring to FIGS. 2 and 3C, the second step of the blind via conducting method of the printed circuit board according to the first embodiment of the present invention is: providing the protective cover 3 on the second side of the insulating layer 1 to cover the conductive layer. 2' is outside the opening edge of the blind hole 11. The protective cover 3 is preferably selected from recyclable Use non-gold «yu cover plate, or optional free photoresist coating or dry film pressing method. No
C:\Logo-5\F i ve Cont i nents\PK9781. ptd 第11頁 1303541 五、發明說明(5) 種架構,該保護罩3皆可用以有效覆蓋該導電層 =目孔11之開口緣以外的區域。同時,該保護罩3對 f 3孔:1形成至少-電鍍窗口31,以便裸露該導電層2, 在泫盲孔1 1之開口緣,以剎 請參照第2、30及3£圖:後,電鍵沈積。 電路板之盲孔導通方法第不牛/㈣第-貫施例之印刷 孔η内沈積形成該電錄導以仃 將該銅箱基板〔即該絕iy4道在進行電鑛製” ’先 ^第一側〔下側〕的導if適二。士接著’將該絕緣層1之 以做為電極,進而促使;屬適:子連接電解槽之負電電源, 二由内而外逐漸電鑛沈積形成該電鑛導 纏的ΛΊ 4在進行電鍍製程前,該第-側〔下 的導電層2較佳亦可選擇 仅吃ϋ摇 塗佈-保護漆〔未緣示〕如覆^另一保4罩3,或遥擇 侧〕的導雪厗?拟占夕 如此可以防止該第一側〔下 側U導電層2形成多餘的電鍍 请參照第2、3F及3G圖所示,士女 電路板之盲孔導通方法第四牛驟f明第一實施例之印刷 >積至填滿該= ^ Ϊ :當該電鍵導通體4累 u電,程期間,該電鍍導通體4藉由電鍍之方式逐 f儿積形成於該盲孔11内’其厚度隨時間之增長而增加, f至填滿該盲孔11並覆蓋該第二側〔上側〕的導電層2,未 受該保護罩3保護裸露在該盲孔丨丨内之部分。亦即,該電C:\Logo-5\F i ve Cont i nents\PK9781. ptd Page 11 1303541 V. Description of the Invention (5) The protective cover 3 can be used to effectively cover the conductive layer = the opening edge of the eye opening 11 Outside the area. At the same time, the protective cover 3 forms at least a plating window 31 for the f 3 hole: 1 so as to expose the conductive layer 2, at the opening edge of the blind hole 1 1 , for reference, refer to the figures 2, 30 and 3: , electric bond deposition. The blind hole conduction method of the circuit board is not deposited in the printing hole η of the first embodiment, and the electric recording is formed to 仃 the copper box substrate (that is, the iy4 channel is in the electric ore system). The first side [lower side] of the guide if appropriate. Secondly, 'the insulating layer 1 as an electrode, and then promote; is suitable: sub-connected to the electrolytic cell negative power supply, two gradually from the inside out of the electric deposit The conductive layer 2 forming the electric ore guide is subjected to the electroplating process, and the first side [the lower conductive layer 2 is preferably selected to be only coated with a coating-protective paint [not shown] such as 4 cover 3, or remote selection side of the snow guide? It is planned to prevent the first side [the lower U conductive layer 2 forms redundant plating, please refer to the 2nd, 3rd and 3G diagrams, the female circuit The blind via conduction method of the board is described in the fourth embodiment. The printing of the first embodiment is completed until the filling is completed. ^ ^ Ϊ : When the key conducting body 4 is discharged, the plating via 4 is plated. The method is formed in the blind hole 11 and its thickness increases with time, f to fill the blind hole 11 and cover the second side [upper side] Layer 2, the protective cover 3 protects exposed in the blind bore of the portion not affected by Shushu. That is, the electrical
13035411303541
五、發明說明(6) 鍍導通體4延伸至該肓孔丨丨之開口端,並形成一凸料4〇。 ,再參照第2及3H圖所示,本發明第一實施例之印刷電 導ίΐΛ:孔工導通方法第五步驟係:選擇研磨方式將該電鑛 ^體4正平,即將該電鍍導通體4之凸料4〇整平,該研磨 雷11選擇機械、電解或雷射研磨,藉此該盲孔11利用吱 ίϊ ϋ4導通該緣絕層1二側的導電層2。如上所述厂 寂j ^間早利用該盲孔11之封閉端的導電層2做為電鍍製 外续66 Ϊ Φ並藉 '該#護罩3適當遮罩該f孔1 1之開口 ‘ 電铲、户藉】f 2 β藉此’即可確保該盲孔U由内而外直接 該電鍍導通體4。相較…本發明可省略 S用導通層成型步驟〔如第】 _ . , ' · 盲孔11形成不良孔洞之機f f510 ’並可有㈣少該 通品質入 機率,進而提升該盲孔11之層間導 : Ϊ2:』Α至4E圖所示’本發明第二實施例之印刷 w板之盲孔導通方法係包含步驟: 刷 導電V2及2在:緣層1之—第一側& -第二側分別具有-形成至少一盲孔u ;、,層1之第二侧貫穿該導電層2,,以 〔2〕、在該絕緣層] 丄 _該導電層2,在該盲孔〗! 一側另設一保護罩3,以復蓋 Γ…、利用該絕以I;緣Γ — 並進行電鍍製程,以便在側的導電層2做為電極, 體4 ; 在β亥盲孔11内沈積形成一電鍍導通 〔4〕、當該電鍍導诵 又导通體4累積至填滿該盲孔丨丨之開〇端V. INSTRUCTION DESCRIPTION (6) The plating body 4 extends to the open end of the pupil and forms a projection. Referring to FIGS. 2 and 3H, the printing conductance of the first embodiment of the present invention is the fifth step of the hole conducting method: selecting the grinding method to level the electric ore body 4, that is, the electroplating conducting body 4 The projection 4 is flattened, and the polishing rod 11 is selected for mechanical, electrolytic or laser polishing, whereby the blind hole 11 conducts the conductive layer 2 on both sides of the edge layer 1 by means of 吱ίϊ ϋ4. As described above, the conductive layer 2 of the closed end of the blind hole 11 is used as an external plating 66 Ϊ Φ and the opening of the f hole 1 1 is appropriately covered by the 'shield 3' The household borrowing] f 2 β thereby ensures that the blind via U directly directs the electroplated conductor 4 from the inside out. Compared with the present invention, the step of forming the conductive layer for S can be omitted (for example, the first hole, the blind hole 11 forms a machine for the defective hole f f 510 ' and can have (4) the quality of the pass through, and the blind hole 11 is improved. The interlayer conduction method is as follows: Ϊ2: Α to 4E shows that the blind hole conduction method of the printing w plate of the second embodiment of the present invention comprises the steps of: brushing the conductive electrodes V2 and 2 at: the edge layer 1 - the first side & - the second side has - forming at least one blind via u;, the second side of the layer 1 extends through the conductive layer 2, to [2], in the insulating layer, the conductive layer 2, in the blind via 〗! A protective cover 3 is additionally provided on one side to cover the crucible, and the electroplating process is performed to make the electroconductive layer 2 on the side as an electrode, the body 4; in the beta blind hole 11 Depositing to form an electroplating conduction [4], when the electroplating guide and the conduction body 4 accumulate to fill the open end of the blind hole
C:\Logo-5\Five Continents\PK9781.ptd 第13頁 .1303541 五、發明說明(7) 後,移除覆蓋該導電層2,之保護罩3 ;及 〔5〕、該盲孔11利用該電鍍導通體4導通該緣絕層1二 側6纟導電層2及2 ’’且該電鍍導通體4之頂部形成一凸塊 41 ’將該凸塊41用以做為印刷電路板之焊墊〔pa(i〕及輸 入/輸出端子〔I/O〕。 、相較於第一實施例,第二實施例之第五步驟係藉由適當 增加該電鍍導通體4之沉積厚度,其沉積厚度最多可實質 ,滿該保護罩3之電鍍窗口 31,而與該保護罩3實質形成等 兩。如此,該電鍍導通體4之凸塊4 1的凸出高度將高於該 .第二導電層2’ ,因此可做為印刷電路板之焊墊及輸入/輸 出端子’以供連通其他電子產品〔如封裝IC〕之錫球、焊 墊或引腳,進而達到簡化導電端子製程之目的。 參照第5A至5D圖所示,本發明第三實施例之印刷電路 盲孔導通方法係包含步驟: 〔1〕、在一絕緣層丨之一第一側形成一導電層2,在該 絕緣層1之一第二側貫穿形成至少一盲孔丨丨; 〔2〕、在該絕緣層!之第—側的導電層2外另設一保護 罩3’ ,以覆蓋該導電層2 ; 〔3〕、利用該絕緣層1之第_側的導電層2做為電極, >並進行電鍍製程,以便在該盲孔丨」内沈積形成一電鍍導通 體4 ; 〔4〕、該電鍍導通體4累積至填滿該盲孔11之開口端 後,移除該保護罩3,;及 ' (5 )、該電鍍導通體4之頂部形成〆凸塊41,該凸塊41C:\Logo-5\Five Continents\PK9781.ptd Page 13.1303541 5. After the invention description (7), the protective cover 3 covering the conductive layer 2 is removed, and [5], the blind hole 11 is utilized. The plating via 4 is electrically connected to the two sides of the edge layer 1 and 6 纟 conductive layers 2 and 2 ′′ and a top portion of the plating via 4 is formed with a bump 41 ′ for the soldering of the printed circuit board. Pad [pa] and input/output terminal [I/O]. Compared with the first embodiment, the fifth step of the second embodiment is deposited by appropriately increasing the deposition thickness of the electroplated via 4. The thickness of the plating cover 31 of the protective cover 3 is substantially equal to the thickness of the protective cover 3, so that the protruding height of the bump 4 1 of the plating conductive body 4 will be higher than the second conductive. The layer 2' can be used as a solder pad and an input/output terminal of the printed circuit board for connecting solder balls, pads or pins of other electronic products (such as packaged ICs), thereby simplifying the process of the conductive terminal. Referring to Figures 5A to 5D, the method for blind hole conduction of a printed circuit according to a third embodiment of the present invention comprises the steps of: 1] forming a conductive layer 2 on a first side of an insulating layer, and forming at least one blind via in a second side of the insulating layer; [2], in the first layer of the insulating layer a protective cover 3 ′ is additionally disposed on the side of the conductive layer 2 to cover the conductive layer 2 ; [3], the conductive layer 2 on the _ side of the insulating layer 1 is used as an electrode, and an electroplating process is performed, so as to Depositing a plating via 4 in the blind via; [4], after the plating via 4 is accumulated to fill the open end of the blind via 11, the protective cover 3 is removed; and '(5) The top of the plating via 4 forms a bismuth bump 41, and the bump 41
第14頁 C:\Logo-5\Five Continents\PK9781. ptd .1303541 五、發明說明(8) "" ' 用乂做為印刷電路板之焊塾〔pad〕及輸入/輸出端子 〔I/O 〕 。 相較於第一及二實施例,第三實施例係應用在單層銅箔 基板領域’因而該絕緣層1之第二側〔上側〕可省略原先 「設置保護罩3〔如第3C圖所示〕覆蓋該盲孔11之開口緣 =外的區域」之步驟。另一方面,在進行電鍍製程前,該 第一側〔下侧〕的導電層2較佳亦可選擇覆蓋另一保護罩 3 ’或選擇塗佈一保護漆〔未繪示〕,如此可以防止該第 一側〔下側〕的導電層2形成多餘的電鍍沈積層。 φ 再者’適當控制增加該電鍍導通體4之沉積厚度,該電 鑛導通體4之凸塊41的凸出高度將高於該絕緣層1之第二·側 的平面’因此該凸塊4 1可做為印刷電路板之導電微球〔類 -似BGA封裝用之錫球〕、焊墊或輸入/輸出端子,以供連通 • 電子產品〔如封裝IC〕之錫球、焊塾或引腳,進而達 匕導電端子製程之目的。 如上所述,相較於習用之印刷電路板之盲孔導通方法先 在該盲孔11之孔壁形戍該導通層1 2,再利用電鍍形成該電 鍍層22填入該盲孔u,因而容易在該盲孔11内部形成該孔 洞22,進而降低層間導通良率之缺點。第2圖之本發明藉 •由利用該盲孔11之封閉端的導電層2做為電鍍製程之電 極,並藉由該保護罩3適當遮罩該盲孔11之開口端外緣的 另一導電層2 ’ 。藉此,不但可確保該盲孔11由内而外直接 電鍵沈積形成該電鐘導通體4,且亦可選擇使該電鍍導通 •體4形成一凸塊41,以做為焊墊或輸入/輸出端子。因此,Page 14 C:\Logo-5\Five Continents\PK9781. ptd .1303541 V. Invention Description (8) "" 'Used as a soldering pad [pad] and input/output terminal for printed circuit boards [I /O 〕. Compared with the first and second embodiments, the third embodiment is applied to the field of a single-layer copper foil substrate. Thus, the second side [upper side] of the insulating layer 1 can omit the original "setting of the protective cover 3 [as shown in FIG. 3C. The step of covering the opening edge of the blind hole 11 = the outer region is shown. On the other hand, before the electroplating process is performed, the conductive layer 2 of the first side (lower side) preferably also covers another protective cover 3' or is selectively coated with a protective lacquer (not shown), thus preventing The first side [lower side] of the conductive layer 2 forms an excess electroplated deposit. φ Further, 'appropriate control increases the deposition thickness of the electroplated via 4, and the convex height of the bump 41 of the electrowinning conductor 4 will be higher than the plane of the second side of the insulating layer 1. Therefore, the bump 4 1 can be used as a conductive microsphere for printed circuit boards (such as solder balls for BGA packages), solder pads or input/output terminals for communication • solder balls, solder pastes or leads for electronic products (such as packaged ICs) The foot, in turn, achieves the purpose of the conductive terminal process. As described above, the blind via conduction method of the conventional printed circuit board first forms the via layer 12 in the hole wall of the blind via hole 11, and then the plating layer 22 is formed by plating to fill the blind via hole u. The hole 22 is easily formed inside the blind hole 11, thereby reducing the disadvantage of interlayer conduction quality. The invention of FIG. 2 is made of an electroconductive layer 2 using the closed end of the blind via 11 as an electrode of the electroplating process, and another conductive layer which appropriately shields the outer edge of the open end of the blind via 11 by the protective cover 3 Layer 2 '. Thereby, not only the blind hole 11 can be directly formed by internal and external key bond formation to form the electric clock conductor 4, but also the plating conduction body 4 can be selected to form a bump 41 as a pad or input/ Output terminal. therefore,
C:\Logo-5\Five Continents\PK9781.ptdC:\Logo-5\Five Continents\PK9781.ptd
1303541 五、發明說明(9) 本發明確實可有效減少該盲孔11形成不良孔洞2 2之機率, 進而提升該盲孔11之層間導通品質及簡化導電端子製程。 雖然本發明已利用前述較佳實施例詳細揭示,然其並非 用以限定本發明,任何熟習此技藝者,在不脫離本發明之 精神和範圍内,當可作各種之更動與修改,因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 _ «1303541 V. INSTRUCTION DESCRIPTION (9) The present invention can effectively reduce the probability of the blind hole 11 forming a poor hole 2 2 , thereby improving the interlayer conduction quality of the blind hole 11 and simplifying the process of the conductive terminal. While the present invention has been described in detail with reference to the preferred embodiments of the present invention, it is not intended to limit the scope of the invention. The scope of the invention is defined by the scope of the appended claims. _ «
C:\Logo-5\Five Continents\PK9781.ptd 第16頁 1303541 圖式簡單說明 【圖式簡單說明】 第1圖:習用之印刷電路板之盲孔導通方法之剖視示意 圖。 第2圖:本發明第一實施例之印刷電路板之盲孔導通方 法之流程方塊圖。 第3A及3B圖:本發明第一實施例之印刷電路板之盲孔導 通方法第一步驟之剖視示意圖。 第3C圖:本發明第一實施例之印刷電路板之盲孔導通方 法第二步驟之剖視示意圖。 第3D及3E圖··本發明第一實施例之印刷電路板之盲孔導 P通方法第三步驟之剖視示意圖。 第3F及3G圖:本發明第一實施例之印刷電路板之盲孔導 通方法第四步驟之剖視示意圖。 圖··本發明第一實施例之印刷電路板之盲孔導通方 步驟之剖視示意圖。 第4A、4B、4C、4D及4E圖:本發明第二實施例之印刷電 路板之盲孔導通方法之剖視示意圖。 第5A、5B、5C及5D圖:本發明第三實施例之印刷電路板 之盲孔導通方法之剖視示意圖。 主要元件符號說明】 12 導通層 21 電鍍層 3’ 保護罩 1 絕緣層 11 盲孔 2 導電層 2’ 導電層 22 孔洞 3 保護罩C:\Logo-5\Five Continents\PK9781.ptd Page 16 1303541 Schematic description of the drawing [Simple description of the drawing] Fig. 1: Schematic diagram of the blind hole conduction method of the conventional printed circuit board. Fig. 2 is a flow block diagram showing a blind via conduction method of a printed circuit board according to a first embodiment of the present invention. 3A and 3B are cross-sectional views showing the first step of the blind via conducting method of the printed circuit board according to the first embodiment of the present invention. Fig. 3C is a cross-sectional view showing the second step of the blind via conduction method of the printed circuit board of the first embodiment of the present invention. 3D and 3E are schematic cross-sectional views showing a third step of the blind via conduction P-channel method of the printed circuit board according to the first embodiment of the present invention. 3F and 3G are schematic cross-sectional views showing a fourth step of the blind via conduction method of the printed circuit board according to the first embodiment of the present invention. Fig. is a cross-sectional view showing the step of blind hole conduction of the printed circuit board of the first embodiment of the present invention. 4A, 4B, 4C, 4D and 4E are schematic cross-sectional views showing a blind via conducting method of a printed circuit board according to a second embodiment of the present invention. 5A, 5B, 5C and 5D are schematic cross-sectional views showing a blind via conducting method of a printed circuit board according to a third embodiment of the present invention. Main component symbol description] 12 conduction layer 21 plating layer 3' protective cover 1 insulating layer 11 blind hole 2 conductive layer 2' conductive layer 22 hole 3 protective cover
C:\Logo-5\Five Continents\PK9781.ptd 第17頁 1303541C:\Logo-5\Five Continents\PK9781.ptd Page 17 1303541
C:\Logo-5\Five Continents\PK9781. ptd 第18頁C:\Logo-5\Five Continents\PK9781. ptd Page 18
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW94128331A TWI303541B (en) | 2005-08-19 | 2005-08-19 | Electrically connecting method for blind holes of printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW94128331A TWI303541B (en) | 2005-08-19 | 2005-08-19 | Electrically connecting method for blind holes of printed circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200709746A TW200709746A (en) | 2007-03-01 |
TWI303541B true TWI303541B (en) | 2008-11-21 |
Family
ID=45070737
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW94128331A TWI303541B (en) | 2005-08-19 | 2005-08-19 | Electrically connecting method for blind holes of printed circuit board |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI303541B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8779292B2 (en) | 2009-12-30 | 2014-07-15 | Au Optronics Corp. | Substrate and substrate bonding device using the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103796434B (en) * | 2014-01-17 | 2016-09-07 | 杨秀英 | A kind of ultrathin FPC method for processing blind hole |
-
2005
- 2005-08-19 TW TW94128331A patent/TWI303541B/en active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8779292B2 (en) | 2009-12-30 | 2014-07-15 | Au Optronics Corp. | Substrate and substrate bonding device using the same |
Also Published As
Publication number | Publication date |
---|---|
TW200709746A (en) | 2007-03-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100550355C (en) | Semiconductor chip mounting substrate and manufacture method thereof and semiconductor module | |
CN101764113B (en) | Metal protruding block structure on connecting pad of circuit surface of semiconductor element and forming method | |
US8835302B2 (en) | Method of fabricating a package substrate | |
CN1236659C (en) | Printed circuit board with built-in passive device, its mfg. method and used substrate | |
JP4508193B2 (en) | Mounting board, mounting body and electronic device using the same | |
CN102468186A (en) | Substrate manufacturing method and semiconductor chip packaging method | |
JP4054269B2 (en) | Electronic component manufacturing method and electronic component | |
TWI333250B (en) | ||
CN103906370B (en) | Chip packaging structure, circuit board having embedded component and manufacturing method thereof | |
TWI303541B (en) | Electrically connecting method for blind holes of printed circuit board | |
CN206525017U (en) | Adhesive-spill-preventing circuit board | |
US9295163B2 (en) | Method of making a circuit board structure with embedded fine-pitch wires | |
JP5069449B2 (en) | Wiring board and manufacturing method thereof | |
JP2007173439A (en) | Substrate with built-in capacitor | |
US20120160549A1 (en) | Printed circuit board having embedded electronic component and method of manufacturing the same | |
TWI360214B (en) | Package substrate and method for fabricating the s | |
JP2020181949A (en) | Wiring board and manufacturing method therefor | |
CN205984970U (en) | Multilayer electron bearing structure | |
CN110167254A (en) | Printed circuit board and semiconductor package part including the printed circuit board | |
CN205944063U (en) | Package substrate | |
CN104332465B (en) | 3D packaging structure and technological method thereof | |
CN107230640A (en) | Have radiating seat and the heat-dissipating gain-type semiconductor subassembly and its preparation method of double build-up circuitries | |
CN102931165B (en) | The manufacture method of base plate for packaging | |
CN107305849A (en) | Encapsulating structure and preparation method thereof | |
US11049781B1 (en) | Chip-scale package device |