TWI303434B - Method and apparatus for testing operation of semiconductor memory device - Google Patents

Description

1303434 * a Japanese material

436, ...... J IX, invention description: [Technical Field] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having enhanced test capability for discovering a body group insertion mode An error in the operation of the semiconductor memory device. [Prior Art] A semiconductor memory device includes a plurality of memory cells. If any of the cell elements in the device exceeds the operational sequence, the semiconductor device is unusable. After the semiconductor memory device fabrication process, a test program is needed to find the cells in the semiconductor memory device. Generally, the semiconductor memory device has an additional area for testing the cell when the semiconductor device is at a high speed. However, it takes a lot of time and effort to test the cells of the semiconductor device in accordance with the increase in the integration of the semiconductor device, and to develop the semiconductor device. Therefore, in order to save time in testing the semiconductor device, a compression type is used. In this compression test mode, data is input to all banks included in the semiconductor via a portion of the input/output pins DQs, rather than via the input/output pins DQs. The data used to confirm the output from each unit cell is not output from all the memory banks via all the inputs 7 at the same time, and these are many gates, such as gates or NOR gates, each of which is Corresponding to each input/output pin about one in memory in the semi-conducting memory device, all of the 瑕 test powers here, in this case to test the test mode is synchronized with the memory component, each foot DQs buckle AND DQs are used by 1303434. Figure 1 is a block diagram showing a test block used in a conventional semiconductor memory device. As shown, the test block includes an internal memory bank address generator 1 一, a read decoding block 20, a compression control block 30, a data compression block 40, and a write decoding. Block 50, a write control block 60 and a write drive block 70. The internal memory bank address generator 1 converts a memory bank address such as B A0 and BA1 to become a plurality of internal memory group addresses, such as a, /a, b5 /b, c, / c,d, /d. The plurality of internal memory bank addresses such as a, /a, b, /b, c, /c, d, /d are all input to the read decoding block 20. The read decoding block 20 decodes a plurality of internal memory group addresses such as a, /a, b, /b, e, /c, d, /d, thereby generating a plurality of read memory group operation signals rdbankO, Rd_bankl, rd_bank2 and rd_bank3 respond to the latch signal AL0 of the attached port. The compression control block 30 is for controlling the data compression block 40 in response to a plurality of read memory group operation signals rd_bank0, rd_bank1, rd_bank2 and rd_bank3. The data compression block 40 has a plurality of DQ output buffers, for example, the DQ output buffer 36 is used to compress the data output of each memory bank. In addition, a portion of the plurality of internal memory bank addresses such as a, /a, b, /b are input to the write decoding block 50. The write decoding block 50 decodes a plurality of internal memory group addresses such as a, /a, b, /b, thereby generating a plurality of write memory group operation signals wt__bank0, wt-bank1, wt_bank2. Wt_bank3. The write control block 60 is used to control the write drive block 70 1303434 year and month strips in response to the write start signal WTen and a plurality of write memory group numbers wt-bankO, wt-bankl, wt_bank2, The wt-bank3 write block 70 is stored in the data input by the cell array array 80 included in each memory group. In addition, the internal memory bank address generator 10 includes a buffer-latch block and a routing block. The buffer block includes two buffers, such as a buffer 12, each of which is configured to receive a first bit group address ΒΑ0 and a second bit memory group address BA1 with a first bit memory group. The address ΒΑ0 and the second bit memory group become internal memory group addresses such as ba 0 _ add, ba 0 _ addb , ba 1 _ bal_addb, and each buffer corresponds to the first bit memory group bit and The second bit memory group address is BA 1. The latch block includes two devices, such as a latch 14 , each of which is controlled by a compression test to transfer internal memory bank addresses such as ba0_add, ba bal_add and bal_addb to a routing block such as a partial majority. The inner body group addresses a, / a, b, / b. The routing block also includes two router routers 16. Each router is used to delay a portion of a plurality of internal group addresses such as a, /a, b, /b, thereby generating other majority internal addresses such as c, /c , d, / d. More specifically, the compression control block 30 includes a read control area to select a communication number generation block 34. The read control block 3 2 includes a multi-fetch controller, each controller is controlled by a read start signal RD en to read and read the memory group operation signal; the selected communication number generation block 3 4 is selected by a number of communication number generators Each selected communication number generator is used to generate the operation input driver [] (cell block, area, instance memory and conversion address BA 1 add and address ΒΑ 0 latches ^ tp ara 0_addb, part memory, such as memory memory The body group 32 and several readings: the system includes the majority of the 1303434 day and day correction replacement page ΠΒ 1! 1. I_ selected communication number, such as iostb. Here, each read controller, each selection The communication number generator H output buffers are individually associated with each of the memory groups included in the conventional half device. In addition, each buffer, each and each router is in the internal memory bank address generator 1 〇 corresponds to the bit of each memory group address. After that, one of the semiconductor memory devices is described as the test torque test signal tpara is activated. First, the internal memory bank address generator 1 does not care. Addressing should be compressed back The test signal tpara starts the internal addresses such as a, /a, b, /b, c, /c, d, /d. Then, the read memory group operation signal rd __ bank 0 is read and decoded. The write group operation signals wt_bank, 0, wt_bank1, wt_bank2 are outputted by rd_bank1 and rd__bank3, and written to the decoding block 50. If the write start signal WTen is started, the block is activated. 60 and the write drive block 70 are activated and then transferred to the cell array 80. Further, if the read enable signal RDen is output, a plurality of data LI00<0:15> output from the cell array 80 are compressed and outputted. In addition, the method of operating the test block, that is, the method for decoding and compressing the output data, is carefully described. In the conventional memory device, each memory bank has one resource to receive four data at a time. The data is treated as (BUNCH); and the four data strings constitute a 16-bit data. Each DQ conductor memory is latched individually. When the memory group is in the memory group, the bit color block is 20 rd_bank2. Into the memory wt_b ank3 the write control is entered Started, LI<0: 1 5> Compresses the data pad, using a data string. In the write 1303434 I---! In the operation, the same 16-bit data is input to each memory group. In the read operation, 16-bit data is input to each memory group of the four classified data strings; each data (datum) is input via the same data pad, and each data string is input. The four data sheets are compared to each other. The comparison result is then output via a data pad corresponding to each memory group. Here, if a logic state of the signal output via the data pad is a high logic level, the semiconductor memory device does not have a cell; however, the semiconductor memory device has at least one cell. Lu 2 is a structural circuit diagram for describing the latch included in the latch block 14 in Fig. 1. - As shown, the latch includes a first inverter 11, a first latch_cell 14a, a second latch cell 14b, a first NAND gate ND1 and a second NAND gate ND2. . Here, the first and second latch cells 14a and 14b are formed by two sets of circuits connected to the inverter. The inverter-inverter 11 is used to invert the compression test signal t p a r a . The first latch cell 14a is used to latch an inverted internal memory bank address, such as ba0_addb; the second latch cell 14b is used to latch an internal memory bank address, for example baO-add. The first NAND gate ND 1 is coupled to the first latch cell 14a and the first inverter 11, and receives an inverted state of the inverted internal memory bank address, that is, internal memory. The body group address and the inverted compression test signal are used to generate a result signal of a NAND operation such as the first internal memory bank address a. Furthermore, the second NAND gate ND2 is coupled to the second latching cell 14b and the first inverter 11 receives an inverted state of the internal memory address of the 1303434 memory group, that is, the inverted internal phase. The memory bank address, and a reverse phase compression test signal to generate a NAND gate operation, a result signal such as a first internal memory bank address /a. Fig. 3 is a structural circuit diagram for describing a router included in the routing block 16 in Fig. 1. As shown, the router includes a latch and delay block 177, a second inverter 12, a third NAND gate ND3 and a fourth NAND gate ND4.

The latch and delay block 17 receives the first internal memory bank address, that is, a, and the first inverted internal memory group address, that is, /a, and outputs a delay signal from the latch output. To the third NAND gate. The second inverter 12 is used to invert the compression test signal tpara. The third NAND gate ND3 is coupled to the latch and delay block 17 and the second inverter 12 receives a self-latching and delay block 17 output signal, and an inverted compression test signal is generated as a third internal One of the NAND operations of the memory bank address c is the result signal. Furthermore, the second NAND gate ND2 is coupled to the first inverter II to receive the third internal memory group address, that is, c and an inverted compression test signal to generate a third inversion memory group position. One of the result signals of the NAND operation of the address /c. Referring to these examples, each latch has the same architecture as each router; therefore, a detailed description of the latch and router is omitted. Fig. 4 is a circuit diagram for reading the decoding block 20 in Fig. 1. As shown, the read decode block 20 includes a control signal generator 21 and a plurality of decoders 22, 24, 26 and 28. The control signal generator 21 generates control signals such as AL Ob and ALOd in response to the additional delay signal -10 1303434 kiiig ALO. Each decoder receives two internal memory bank addresses and selects one of the two internal memory bank addresses in response to a control signal such as ALOb and ALOd ' to generate an inverted selection address as a read memory bank operation Signal.

More specifically, the control signal generator 2 1 includes a third inverter 13 for inverting the compression test signal, and a fifth NAND gate ND5 for generating the result of the additional delay signal AL0, the test signal and the inverse compression test. The signal and a fourth inverter 14 are used to invert a first control signal ALOb, that is, a signal output by the fifth NAND gate ND5, thereby generating a second control signal AL 0 d. Each decoder includes two NAND gates, two transmission gates and an inverter. One of each of the two NAND gates receives two internal memory bank addresses and produces a result signal of one of the NAND operations; one of each of the two transmission gates transmits the result signal in response to the first and second control signals ALOb With ALOd. Then, the inverter outputs the output of the two transmission gates.

The signal conversion 'is used to generate an inverted signal of the output signal as a read memory group operation signal. Referring to Figure 4, the read decoding block 2 〇 includes four decoders. Most of the internal memory group addresses, namely a, /a, b, /b, c, /c, d, /d, are classified into four groups, each of which includes four internal memory groups. Address · (/a' /b' /c, /d), (a, /b, c, /d), (/a, b, /c, d), (a,b,c,d) 〇 Here, each decoder, such as decoder 2 2, decoder 24, decoder 26 and decoder 28, decodes the latch block to output a group of non-delay-11-1303434

Year 3 Correction Replacement Sell I | τ 11.1 .1.. One £-L-, one.. "*·<>*--" Internal memory group address, ie a, /a, b , /b, and the delayed internal memory bank address of the routing block output, that is, c, /c, d, /d, in response to the first and second control signals ALOb and ALOd. In conventional memory devices, a RAS to CAS delay tRCD is required, and the tRCD is supplied with a row of start signals for a minimum time to supply a row of start signals. However, if an additional delay is introduced to increase the operating speed of one of the semiconductor memory devices, the row start signal is supplied before the RAS to C AS delay tRCD after the column start signal is supplied. That is, according to this additional delay, the timing for supplying the line start signal can be adjusted. If the additional delay signal AL0 is not activated, for example, the additional delay signal is 2 or 3, the line start signal is input before the RAS to C AS delay tRCD, and then there is a lot of time margin for storing. Take the data in response to the line start signal. In this example, because there is a lot of time margin, the internal memory bank address is delayed, that is, c, /c, d, /d, which is decoded in the read decoding block 20 and is routed through the block 1. 6 delay. In addition, if this additional delay signal AL0 is activated, for example, the additional delay is 〇, the line start signal is input after the RAS to C AS delay tRCD and then there is a lot of time margin for accessing the data in response to the start of the line. Signal contact data. In this example, the non-delayed internal memory bank address, i.e., a, /a, b, /b, is decoded in the read decoding block 20 because of some time margin. Fig. 5 is a circuit diagram of a DQ output buffer included in the data compression block 40 according to Fig. 1. As shown in the figure, 'this DQ output buffer is included in the data compression block 40 -12 - 1303434 year-and-month correction replacement page Ωβ II ί β, this data compression block 40 includes a gate control generator 42' Block 4 4 and a gate drive block 46. In addition, it is shown here that a G10 driver includes two 〇 S transistors ΡΜ1 and ΝΜ1 connected in series between a supply voltage and ground. The strobe control generator 42 receives the compressed test signal tpara and the selected communication number iostb of the selected communication number generator included in the signal generating block, thereby generating a first and a second data selection communication number iostb2 and iost2b. The comparison block 44 receives each of the data output by the cell array 80 for compression into 16-bit data. Finally, the strobe driving block 46 outputs a compressed data output from the comparison block 44 to the GI0 driver to respond to the first and second data selection communication numbers i〇stb2 and iostb2b. As described above, the conventional semiconductor memory device can quickly test all of the cell units by using this compression test mode. However, this test mode included in the semiconductor memory device cannot test a memory group interleaving mode because all of the memory groups included in the semiconductor memory device are simultaneously activated. In fact, the semi-conductor memory device operates in this gS memory group insertion mode to increase the speed of a shot. In the memory group insertion mode, data collides or deviates. "... occurs when the data is arbitrarily read and written between each memory group. Therefore, 'to test a semiconductor memory device in the memory bank insertion mode, the 'data cannot be compressed', so the result The time required for the test can be very long. [Invention] Therefore, the present invention proposes an advanced mode semiconductor memory device-13-

1303434 Look for errors in the memory bank insertion mode (i n t e r 1 e a v i n g m o d e ) operation of the semiconductor memory device to reduce the test time. From the perspective of the present invention, the present invention proposes a method of testing the operation of a semiconductor memory device having a plurality of memory banks in a compression test mode, comprising the following steps; (A) simultaneously starting a plurality of memory banks To test the semiconductor memory device (B), the semiconductor memory device is tested by randomly starting a plurality of memory banks. In another aspect of the present invention, the present invention provides an apparatus for testing the operation of a semiconductor device having a plurality of memory banks in a compression test mode, including an internal address generator for receiving an external memory bank Addressing and generating an internal memory bank address in response to a memory bank insertion test signal; a read operation test block for receiving an internal memory bank address and a read operation in the test semiconductor memory device Responding to the memory bank insertion test signal; a write operation test block for receiving an internal memory bank address and a write operation of the test semiconductor memory device. [Embodiment] Hereinafter, a semiconductor memory device according to the present invention will be described in detail based on the accompanying drawings. Figure 6 is a diagram showing a test block used in a semiconductor memory device in accordance with the present invention. As shown, the test block includes an internal address generator 100, a read operation test block and a write operation test block. The internal address generator 100 receives an external memory bank address such as ΒΑ0 and generates internal memory group addresses such as a and /a in response to a memory bank insertion. 14-1303434 mu: the test signal iocomp. The read operation test block is configured to receive an internal memory bank address such as a and /a and to test a read operation of the semiconductor memory device to respond to the §2 memory group insertion test signal i 〇c 〇mp . The write operation test block is configured to receive internal memory bank addresses such as a and /a, and to test a write operation of the semiconductor memory device. Here, the read operation test includes a read decoding block 200, a compression control block 300 and a data compression block 400; and a write operation S-block 'including a * write The decoding block 500, a write control block 60 and a write drive block 700. More specifically, the internal memory bank address generator 1 0 0 converts a memory bank address, such as ΒΑ0 and BA1, to become a plurality of internal memory bank addresses, that is, a, /a, b, /b,c,/c,d,/d, in response to a compression test signal tpara and the memory group insert test signal iocomp. Here, the internal memory group address, that is, a, /a, b, /b, c, /c, d, /d, is classified as a non-delayed internal memory group address, that is, a, / a, b, /b, and delayed internal memory group addresses, ie c, /c, d, /d. The plurality of internal memory bank addresses such as a, /a, b, /b, c, /c, d, /d are input to the read decoding block 200. The read decoding block 200 decodes a plurality of internal memory group addresses, that is, a, / a, b, / b, c, / c, d, / d, thereby generating a plurality of read memory groups. The operation signals rd - bankO, rd - bankl, rd - bank2 and rd_bank3 are in response to an 'additional delay signal AL 0' and the memory bank insertion test signal i 〇c 〇mp. The compression control block 300 is used to control the data compression block 400 to respond to the read memory group operation signals rd bankO, rd__bank1, rd_bank2 and rd_bank3. This data compression -15 - 1303434 day I positive replacement page block 400 has a plurality of DQ output buffers for compressing the data outputted by each memory group, thereby outputting a test result signal in response to the compression test signal tpara and one The memory group is not activated signal Xedb_ba. In addition, the non-delayed internal memory bank address, that is, a, /a, b, /b, is input to the write decoding block 500. The write decode block 500 decodes a portion of the internal memory bank address a, /a, b, /b, thereby generating a plurality of write memory bank operation signals wt_bank0, wt_bank1, wt_bank2 and wt_bank3. The write control block 600 controls the write drive block 700 in response to a write enable signal WTen and a plurality of write memory bank operation signals wt_bankO, wt_bankl, wt_bank2 and wt_bank3〇 write drive blocks 700 is used for storing input to the cell array 8 00 included in each memory group. In addition, the internal memory bank address generator 1 includes a latch controller 1 800, a buffer block, and a buffer block. Latch block, a routing block. The latch controller 180 is configured to receive the compression test signal tpara and the memory bank insertion test signal iocomp and to control a latch control signal. The buffer block includes two buffers, such as a buffer 120, each buffer for receiving a first bit record group address ΒΑ0 and a second bit memory group address BA1, and converting the first The bit memory group address ΒΑ0 and a second bit memory group address BA1 become internal memory group addresses such as ba0_add, ba0_addb, bal_add, and bal_addb, each corresponding to the first bit memory The body group address ΒΑ0 and the second bit memory group address BA1. The latch block includes two latches, such as latches 140, each of which is controlled by a latch control signal to transmit an internal address such as ba0_addd, -16-

1303434 ba0_addb, bal_add and bal_addb to the routing block as non-delay internal memory group addresses such as a, / a, b, / b. The routing block also includes two routers, such as router 160, each of which delays a portion of a plurality of internal memory bank addresses such as a, /a, b, /b, thereby generating a delayed internal memory bank address. Such as c, /c, d, /d.

More specifically, the compression test block 300 includes a read control block 320 and a select communication number generation block 340. The read control block 3 20 includes a plurality of read controllers, each of which is controlled by a read enable signal RDen to receive the read memory bank operation signal and the output memory bank non-interpolation signal such as Xedb_ba to data compression. Block 400; and select communication number generation block 3 40 includes a plurality of selected communication number generators, each of which selects a plurality of selected communication numbers, such as iostb.

Here, each of the read controllers, each of the selected communication number generators and each of the DQ output buffers are individually associated with each of the memory banks included in the conventional semiconductor memory device. In addition, each buffer, each latch, and each router individually corresponds to each bit of each memory bank address in the internal memory bank address generator. Next, the test operation of the semiconductor memory device when the compression test signal tpara is activated will be described. First, the internal memory bank address generator 1 initiates these internal memory group addresses such as a, /a, b, /b, c, /c, d, /d in response to these memory group addresses. Compress test signal tpara. Then, the read memory bank operation signals rd_bank0, rd_bank1, rd_bank2 and rd_bank3 outputted by the decoding block 200 and the write 174-! 6 1303434 output memory written by the decoding block 500 are read. The group operation signals wt_bank0, wt__bank1, wt_bank2, and wt_bank3 are all started. If the write enable signal WTen is enabled, the write control block 600 and the write drive block 70 are enabled, and then the data is input to the cell array 800. In addition, if the read enable signal RDen is activated in response to the additional delay signal AL0 and the memory bank insertion test signal iocomp, the data output from the plurality of cell arrays 800 is LI00<0:15> to LI<〇: 1 5> It is then compressed and output. At this time, other memory group addresses, such as the memory group that is not selected, output a logic high level signal to replace the test result signal in response to the memory group non-start signal such as Xedb_ba. Here, if the logic state of the signal output via the data pad is high, the semiconductor memory device does not have a cell; however, the semiconductor memory device has at least one cell. ^ Fig. 7 is a circuit diagram showing the latch 1404 and the latch controller 180 of the latch block shown in Fig. 6. As shown, the latch controller 180 includes a fifth inverter 15 and a sixth NAND gate ND6; the latch 140 includes a first latch cell 142 and a second latch cell 144. , a seventh NAND gate ND7 and an eighth NAND Φ gate ND2. Here, the first and second latch cells 142 and 144 are constructed by two circuit set connection inverters. In the latch controller 180, the fifth inverter 15 is for inverting the memory bank insertion test signal iocomp. The sixth NAND gate receives the output signal output by the fifth inverter 15 and the compression test signal tpara to generate a result signal of the NAND operation. The first latch cell 1 42 is used to latch an inverting internal memory bank -18- 1303434 96.11. 1 6 site 'such as ba 0 _a ddb ; and the second latch cell 1 4 4 is used To latch an internal memory bank address such as baO — add. The seventh NAND gate ND7 receives an output signal from the lock controller 1880 and an inverted internal memory group address 'that is, an internal memory bank address and an inverted compression test signal to generate a NAND operation. The resulting signal acts as a first internal memory bank address. Moreover, the eighth NAND gate ND8 receives the output signal output by the latch controller 180 and the inverted compression test signal to generate a result signal of a NAND operation as the first inverted internal memory group address /a. Fig. 8 is a circuit diagram showing the read decoder shown in Fig. 6. As shown in the figure, the read decoding block 200 includes a control signal generator 2 1 0 and a plurality of decoders 2 2 0, 2 4 0, 2 6 0 and 2 8 0. The control signal generator 210 is configured to generate first and second control signals, such as ALOb and AL 0 d, in response to the attached delay signal AL 0, the compression test signal tpara, and the memory group insertion test signal i〇 Comp. Each decoder receives two memory bank addresses in response to the first and second control signals, such as AL 0 b and ALOd, and selects one of the two internal memory bank addresses to generate an inversion. The address is selected as the read memory group operation signal. In this case, each decoder is identical to the structure of each of the conventional decoders in Fig. 4, and therefore, a detailed description about each decoder is omitted. More specifically, the control signal generator 2 1 0 includes a first NOR gate NR 1 for performing the operation of the compression test signal tpara and the memory bank insertion test signal i 〇c 〇mp, a ninth NAND gate The ND 9 is used to generate a result signal of the additional delay signal AL0 and the output signal of the first NOR gate NR1 in the NAND operation, and a sixth inverter 16 is used to invert a -19-(four) if positive replacement page 1303434. The control signal ALOb, that is, the signal output from the ninth NAND gate ND9, generates a second control signal ALOd. Figure 9 is a circuit diagram showing the DQ output buffer of the data compression block shown in Figure 6. As shown, the DQ output buffer, such as buffer 360, is included in a data compression block 400, which includes a gate control generator 420, a comparison block 440, and a strobe. The drive block 460 is coupled to an output controller 480. In addition, a GI0 driver is shown here, including two MOS transistors PM2 and NM2 connected in series between the supply voltage and ground. The strobe control generator 420 receives the compressed test signal tpara and the memory group non-activated signal Xedb_ba and the selected communication number iostb of the selected communication number generator output included in the signal generating block 3 40, thereby generating an output control signal tgiob. First and second data selection communication numbers iostb2 and iostb2b. The comparison block 440 receives each of the data LI00<0:15> to LI03<0:15> outputted by the cell array [] 800 to compress the 16-bit data as a test result signal. Moreover, the strobe driving block 460 outputs a compressed data outputted by the comparison block 440 to the GI0 driver in response to the first and second data selection communication numbers i〇stb2 and iostb2b. Finally, the output controller 408 includes two N AND gates for selectively outputting the test result signal and a logic high level signal in response to the output control signal tgiob. Here, if the memory group non-start signal such as Xedb_ba is activated, the corresponding note: the body group will output a logic high level signal. This is because a memory bank outputs a logical low-level signal. Thus, the memory bank has at least one cell. If one of the memory groups that have not been selected outputs one -20- 1303434; the year bow C] Xiuqiu-Tieian. 196.1L-16 „.一.... Logic low-level signal, in the selected It is possible to find an error in the memory bank. Fig. 10 is a circuit diagram showing the write decoding block shown in Fig. 6. As shown, the write decoding block 500 includes four NAND gates, each of which A NAND gate is used to receive the non-delayed internal bank address, thereby generating a write memory bank operation signal, such as wt_bank0. Here, the write decode block 500 only receives the non-delayed internal memory bank location because The latch of the write operation is typically one clock cycle shorter than its read operation for the semiconductor memory device. As described above, the test block tests the memory bank insertion in the semiconductor memory device by using the compression test mode. In addition, the semiconductor memory device can quickly test all cell units by using a compression test _ mode. Here, although the internal memory bank address used in this test is used in the present invention Additional delay is controlled, but this The test can be performed without concern for additional delays. Therefore, in the memory bank insertion mode for testing the operation of the semiconductor memory device®, the compression test mode can be performed, and the required test time is significantly reduced. The application department is related to the patents of Korean Patent No. 20 04- 1 8 9 1 9 and No. 2004-0 1824. The above patent applications were filed at the Korean Patent Office on March 19, 2004 and January 10, 2004, respectively. The entire contents are hereby incorporated by reference to these examples. The present invention is hereby incorporated by reference to the particular embodiments of the present invention, and the present invention is associated with -21 - 1303434 - s y t >, 11 *· | - tj. There are various differences in the art of the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention, and the scope of the invention is subject to the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a test block used in a conventional semiconductor memory device; Fig. 2 is a view for describing the structure of a latch included in the latch block in Fig. 1. Circuit diagram 3 is used to describe the structural circuit diagram of the router included in the routing block in FIG. 1; FIG. 4 is only a circuit diagram for reading the decoding block as described in FIG. 1; FIG. 5 is a diagram according to FIG. The data compression block includes a circuit diagram of the DQ output buffer; FIG. 6 shows a test block diagram used in the semiconductor memory device according to the present invention; and FIG. 7 depicts the latch shown in FIG. Circuit diagram of the latch of the block; Fig. 8 is a circuit diagram of the router of the routing block shown in Fig. 6; Fig. 9 is a diagram showing the DQ output buffer of the data compression block shown in Fig. 1. Circuit diagram; Fig. 10 is a circuit diagram for writing a decoding block in Fig. 6. Component Representation Symbol 10 > 100 Internal Memory Group Address Generator -22 - 1303434 9 § 言 f 正 Positive Replacement Page 20 , 200 Read Decode Block 21 Control Signal Generator 22 , 24 , 26 , 28 Decoder 30 Compression control block 32, 320 read control block 34, 340 select communication number generation block 36' 360 DQ output buffer 40, 400 data compression block 42, 420 gate control generator 44, 440 comparison block 46 460 gate drive block 480 output controller 50, 500 write decode block 60, 600 write control block 70, 700 write drive block 80, 800 cell array BAO first bit memory group Address BA1 second bit memory bank address 12, 120 buffer 14, 140 latch 16, 160 router 11 first inverter 14a, 142 first latch cell

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14b, 144 ND1 ND2 ND3 ND4 ND5 ND6 ND7 ND8 ND9 PM1, NM1 a, /a, b, /b iocomp tpara 11 12 Second latch cell first NAND gate second NAND gate third NAND gate fourth NAND gate Fifth NAND gate sixth NAND gate seventh NAND gate eighth NAND gate ninth NAND gate M0S transistor internal memory group address memory group insertion test signal compression test signal first inverter second inverter

-twenty four-

Claims (1)

I) G 4 4 ^________ j Year Month Day Correction Replacement Bao 07 K.3 0____ No. 93 1 1 9 5 20 "Methods and Devices for Testing the Operation of Semiconductor Memory Devices" Patent Case (Amended in May 2008) X. Patent Application Range: 1 · A method for testing the operation of a semiconductor memory device having a plurality of memory banks in a compression test mode, the method comprising the following steps: (A) by simultaneously activating the plurality of memories Testing the semiconductor memory device by the body group; and (B) testing the semiconductor memory device by selectively activating the plurality of memory banks, wherein the test signal is selected by the memory bank in the compression test mode One of step (A) and step (B). 2. The method of claim 1, wherein each of the plurality of memory groups includes a data pad for inputting and outputting data. 3. The method of claim 2, wherein the step (B) comprises the step (B-1) of supplying general status information to a plurality of data pads, each of the data pads corresponding to the activated memory. Each of the unactivated memory groups other than the group is used to avoid such unactivated memory groups being considered as memory banks. 4. The method of claim 1, further comprising the step (C) of delaying a memory group address, the memory group address being used to activate each of the groups of memory, according to the addition Delay to test the operation of the semiconductor memory device. Ι3Ό3434 5—a device for testing the operation of a semiconductor memory device having a plurality of memory banks in a compression test mode, the device comprising: an internal address generator for receiving an external memory bank address and based on The external memory group address generates a plurality of internal memory group addresses to respond to the compression test signal and the memory group insertion test signal; and a read operation test block for receiving the internal memory group position And testing a read operation of the at least one memory bank selected by the internal memory bank addresses in response to the additional delay signal, the compression test signal, and the memory bank insertion test signal; and a write operation a test block for receiving the internal memory bank address and a write operation of the selected memory group, wherein in the compression test mode, a plurality of memory groups are simultaneously activated or selectively activated In response to the memory group inserting the test signal. 6. The device of claim 5, wherein the internal memory group address is divided into a plurality of non-delayed internal memory group addresses and a plurality of delayed internal memory group addresses. 7. The device of claim 6, wherein the internal address generator comprises: a latch controller for receiving the compression test signal and inserting a test signal with the memory bank and controlling a latch control signal a buffer block for converting the external memory group address into the internal memory group address; 1303434 a. 971:5...3. 0 one, - one" a latch block, Controlled by the latch control signal for latching the internal memory bank addresses, thereby outputting the internal memory bank addresses as the non-delayed internal memory bank addresses; and a routing block, The non-delayed internal memory bank address output by the latch block is delayed to generate the delayed internal memory group address. 8. The device of claim 7, wherein the buffer block comprises a plurality of buffers, each of the buffers corresponding to each bit of the external memory bank address. 9. The device of claim 8 wherein the latch block comprises a plurality of latches controlled by the latch control signal, each of the latches corresponding to the external memory bank address Every bit of it. 1 0. The device of claim 9, wherein the routing block comprises a plurality of routers, each of the routers corresponding to each bit of the external memory bank address. The apparatus of claim 6, wherein the read operation test block comprises: a read decoding block, and the test signal is inserted based on the additional delay signal, the compression test signal, and the memory group, Decoding the non-delay internal memory group address and one of the delayed internal memory group addresses, thereby generating a plurality of read memory group operation signals; a compression control block is read by Initiating signal control for receiving the plurality of read memory group operation signals and generating a plurality of strobes 1303434 t---I • I year, month, material, H, yrZ_5wJi-〇.. signal; and a data The compressed block is configured to compress a plurality of outputted by the array of cells to select a plurality of memory groups and generate a test result signal to return the test signal and the plurality of selected communication numbers. The device of claim 11, wherein the read decoding block comprises: a control signal generator for receiving the additional delay signal, the compression test signal, and the memory group insertion test signal And generating a plurality of first and second control signals; and a plurality of decoders, each of the decoders for decoding the non-delayed internal memory group address and the delayed internal memory group address, so as to wait for the first The second control signal, wherein each of the decoders corresponds to each of the plurality of memory groups. 1 3 - The apparatus of claim 12, wherein the data compression block comprises a plurality of DQ output buffers, each of the DQ output buffers corresponding to each of the plurality of memory groups Body group. 14. The device of claim 13, wherein each of the DQ output buffers comprises: a gate control generator for generating an output control signal, first and second data selection communication numbers, Responding to the general type information signal, the compression test signal and the selected communication number; a comparison block for receiving a plurality of data and generating the test result *1303434 r-一一^——一—". TI 1 kg r.; r? ../.: .Ά attack β · ί • · a .'η q7. ^ ! signal; ~ strobe drive block 'to output the test result signal, to return should wait And an output controller for outputting the test result signal to output the control signal. 1 5 · The device of claim 6 wherein the write operation test block The method includes: a write decoding block for decoding the non-delayed internal memory group address, thereby generating a plurality of write memory group operation signals; and a write control block controlled by a write start signal, To receive the majority of the writes The memory group operates on the signal and generates a plurality of write drive signals; and a data compression block for storing the input data into the array of cells of the selected memory group, so as to wait for a plurality of write drive signals.