1303317 九、發明說明： 【發明所屬之技術領域】 • 本發明提供一種電路測試裝置，尤指一種應用於骨牌互補金氧 半‘體邏輯電路(domino CMOS logic)的暫存電路以及掃描暫存電 路。 【先前技術】 § 為丁要提高電路的操作速度，設計者利用動態電路(dynamic circuit)取代靜態電路(static drcuit)已成為現今數位邏輯電路的趨 勢，其中動態電路包含有骨牌互補金氧半導體邏輯電路、差動式 串接電壓擺幅邏輯電路(Differential cascade v〇ltage swing 1〇gic)等 冬以月牌互補金氧半導體邏輯電路為例，其利用了一個虛擬N 型場效電晶體(pseudo NMOS)的架構來實現其邏輯電路，若與靜態 電路比較，這樣做會大大減少其所需的電晶體個數，而且，骨牌 籲互補金氧半導體邏輯電路在做動態的操作時具有較小的充電延遲 (P Up如1吵)以及可被忽略的短路電流(sh〇rt>circuit current)效 應/因此，以骨牌互補金氧半導體邏輯電路來實現一動態邏輯電 路將會成為現今積體電路設計較具競爭力做法。 日s』而’事貫上骨牌互補金氧半導體邏輯電路所面對的最大問 題疋曰曰片元紐的測試部份，而在習知技術巾所揭露的測試方法 均假設骨牌互補金氧半導_輯電路是由純組合骨牌邏輯閘 (purely combinational D〇mino gate)^^^ , f 6 1303317 :7: Γ 卿“: 牌邏輯閘(Sequential Domino logic)並不適用，因此，現今大部份設 計者仍以動態電路結合靜態電路的組合方式來設計。1303317 IX. Description of the Invention: [Technical Field] The present invention provides a circuit test apparatus, and more particularly to a temporary storage circuit and a scan temporary storage circuit applied to domino CMOS logic . [Prior Art] § In order to improve the operating speed of the circuit, the designer has replaced the static circuit with a dynamic circuit (static drcuit), which has become the trend of today's digital logic circuits. The dynamic circuit includes domino complementary MOS logic. For example, the circuit, differential cascade voltage swing logic circuit (Differential cascade v〇ltage swing 1〇gic), etc., is a case of a winter N-type complementary MOS logic circuit, which utilizes a virtual N-type field effect transistor (pseudo) NMOS) architecture to achieve its logic circuit, if compared with static circuits, this will greatly reduce the number of transistors required, and, dominoes complementary MOS logic circuits have a smaller dynamic operation Charging delay (P Up as 1 noise) and negligible short circuit current (sh〇rt > circuit current) effect / Therefore, using a domino complementary MOS logic circuit to implement a dynamic logic circuit will become the current integrated circuit design More competitive approach. The s s 』 』 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The _ _ circuit is composed of purely combinational D 〇 gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate gate The designer is still designed in a combination of dynamic circuits and static circuits.
依據美國專利第6，108,805號所揭露之”DOMINO SCAN ARCHITECTURE AND DOMINO SCAN FLIP-FLOP FOR THE TESTING OF DOMINO AND HYBRID CMOS CIRCUITS，，中的教 導可得知其具有三項缺點：第一，由於該習知技術的骨牌掃描單 _ 元是利用多個輸出級所組成，因此一輸入資料從輸入至產生一輸 出資料的時間變長了；第二，由於該習知技術在操作的過程中利 用了兩個控制時脈，即系統時脈和骨牌時脈，因此若要得到正確 的結果，必需精準地控制系統時脈和骨牌時脈之間的時序關係； 第二，由於該習知技術所需利用的系統時脈和骨牌時脈的工作週 期(Duty cycle)不一致，因此便增加了實作上的困難度。 【發明内容】 _ 口此本叙明的主要目的之一在於提供一種暫存電路以及掃描 暫存電路，以解決上述問題。 依據本發明之實施例，其提供一種暫存電路。該暫存電路包含 有y閃鎖電路，用來關—輸人資料產生-輸出資料；-輸入訊 號選擇電路’分難接於—非測試資料與-測試資料，用來選擇 性地輸出該非測試資料或該測試資料來作為該輸人資料；-控制 電路’轉接於—·鶴時脈，絲依據馳動時脈來㈣該閃鎖電 1303317 路是否可閂鎖該輸入資料來決定該輸出資料；以及一掃描電路， 耦接於該驅動時脈與該閂鎖電路，用來依據該驅動時脈掃描該閂 , 鎖電路所輸出之該輸出資料以產生一掃描資料；其中當該驅動時 脈由一第一邏輯準位轉變至一第二邏輯準位時，該控制電路會允 井该閃鎖電路閃鎖該輸入資料來決定該輸出資料，以及該掃描電 路會掃描該輸出資料以產生該掃描資料，以及當該驅動時脈由該 第二邏輯準位轉變至該第一邏輯準位時，該控制電路不允許該閂 鎖電路閃鎖該輸人資料來決定該輸出:#料，以及該掃描電路會維 • 持該掃描資料。 •【實施方式】 立請參考第1圖，第1圖為本發明暫存電路1〇〇之一實施例的示 意圖。暫存電路1GG包含# : _電路1G2、—輸人訊號選擇電 路辦、-控制電路以及一掃描電路1〇8。_電路收用來 閃鎖:輸入資料V,產生一輸出資料Q (請注意，另一輸出資料 QB係為輸出資料Q的互補訊號’耻可依據電路設計需求來選 擇使用輸出資料Q或輸出資料QB)。輸入訊號選擇電路⑽分別 3=測_ Din與一測試資料Tin ’用來選擇性地輸出非 =式貝料Din或測試資料Tin來作為暫存電路觸所處理的輸入資 财X控制電路106係摘於一驅動時脈Vck，用來依據驅動時 =:控軸電請是否可入資料Vin以決繼資料 h電路108係雛於驅動時脈％與_電路搬，用來依 據驅_ \掃描_路搬所輸出之輪出資料q以產生一 8 1303317 掃描資料SCAN—Q。於本實施例中，當驅動時脈Vck由一低邏輯 準位VlQW轉變至一高邏輯準位Vhigh時，控制電路1〇6會允許閃鎖 電路102閂鎖輸入資料vin來決定輸出資料Q，以及掃描電路108 會掃描輸出資料Q以產生掃描資料SCAN—Q ;然而，當驅動時脈 vck由高邏輯準位Vhigh轉變至低邏輯準位vbw時，控制電路ι〇6 不允許閂鎖電路102閂鎖輸入資料Vin來決定輸出資料q，以及掃 描電路108會維持住掃描資料SCAN_Q。 鲁 如第1圖所示，控制電路106係由一 N型場效電晶體μ〗來加 以實作，而N型場效電晶體M〗係辆接於輸入訊號選擇電路1〇4 與一第一預定電壓準位Vgnd之間，用來依據驅動時脈Vck來選擇 .性地連接輸入訊號選擇電路辦與第一預定電壓準位Vgnd。閂鎖 電路102係依據輸入訊號選擇電路1〇4之一第一資料輸出端N〇utl 與一第二資料輸出端Nc^2所接收之輸入資料Vin (非測試資料Din 或測試資料丁in)來決定輸出資料Q。本實施例中，輸入訊號選擇 • 電路1〇4包含有一第一切換開關1〇42、一第二切換開關1044以及 -第二切換開關1G46。第—切換開關麗包含有—N型場效電 曰體M2 N型場效電晶體M3以及一反相器1〇48，因此第一切 換開關1042係選擇性地依據一選擇訊號狐將控魏路腸減 ;第輸出端N】或一第二輸出端& ;第二切換開關1〇44包含 有N型场效電晶體％、一 n型場效電晶體％以及一反相器 〇欠用來依據非測試資/料丁Μ選擇性地將第一輸出端％減於 胃料輸出端或第二資料輸出端队‘第三切換開關1〇46According to the teachings of "DOMINO SCAN ARCHITECTURE AND DOMINO SCAN FLIP-FLOP FOR THE TESTING OF DOMINO AND HYBRID CMOS CIRCUITS" disclosed in U.S. Patent No. 6,108,805, it is known that it has three disadvantages: first, due to the The domino scanning unit of the known technology is composed of multiple output stages, so the time from input to output of an input data becomes longer; secondly, because the prior art utilizes two in the course of operation Control the clock, that is, the system clock and the domino clock, so to get the correct result, it is necessary to accurately control the timing relationship between the system clock and the domino clock; Second, due to the use of the prior art The system clock and the domino clock have inconsistent Duty cycle, thus increasing the difficulty of implementation. [Invention] _ mouth One of the main purposes of this description is to provide a temporary storage circuit and The temporary storage circuit is scanned to solve the above problem. According to an embodiment of the present invention, a temporary storage circuit is provided, and the temporary storage circuit includes a y flash lock circuit for off Input data generation-output data; - input signal selection circuit 'different to--non-test data and-test data, for selectively outputting the non-test data or the test data as the input data; - control circuit 'Transferred to - crane clock, the wire is based on the moving clock (4) whether the flash lock 1303317 can latch the input data to determine the output data; and a scanning circuit coupled to the driving clock and The latch circuit is configured to scan the latch according to the driving clock, and output the output data to generate a scan data; wherein the driving clock transitions from a first logic level to a second logic level When the bit is in position, the control circuit allows the flash lock circuit to flash the input data to determine the output data, and the scan circuit scans the output data to generate the scan data, and when the drive clock is used by the second logic When the level shifts to the first logic level, the control circuit does not allow the latch circuit to flash the input data to determine the output: and the scan circuit maintains the scan data. • [Embodiment] Please refer to Fig. 1, which is a schematic diagram of an embodiment of the temporary storage circuit 1 of the present invention. The temporary storage circuit 1GG includes #: _ circuit 1G2, - input signal selection circuit, - Control circuit and a scanning circuit 1〇8. _ Circuit receiving flash lock: input data V, generate an output data Q (please note that another output data QB is a complementary signal of the output data Q 'shame can be based on the circuit Design requirements to choose to use the output data Q or output data QB). Input signal selection circuit (10) respectively 3 = _ Din and a test data Tin 'used to selectively output non-type shell material Din or test data Tin as a temporary The input wealth control circuit 106 processed by the memory circuit is extracted from a driving clock Vck for use according to the driving time =: the control axis is required to input the data Vin to determine the data h circuit 108 is driven when driving The pulse % and _ circuit are used to generate an 8 1303317 scan data SCAN-Q according to the round output data q of the drive_scan_road. In this embodiment, when the driving clock Vck transitions from a low logic level V1QW to a high logic level Vhigh, the control circuit 1〇6 allows the flash lock circuit 102 to latch the input data vin to determine the output data Q. And the scan circuit 108 scans the output data Q to generate the scan data SCAN_Q; however, when the drive clock vck transitions from the high logic level Vhigh to the low logic level vbw, the control circuit ι6 does not allow the latch circuit 102 The input data Vin is latched to determine the output data q, and the scan circuit 108 maintains the scan data SCAN_Q. As shown in Fig. 1, the control circuit 106 is implemented by an N-type field effect transistor μ, and the N-type field effect transistor M is connected to the input signal selection circuit 1〇4 and a first A predetermined voltage level Vgnd is used to selectively connect the input signal selection circuit to the first predetermined voltage level Vgnd according to the driving clock Vck. The latch circuit 102 is based on the input data Vin received by the first data output terminal N〇ut1 and the second data output terminal Nc^2 of the input signal selection circuit 1〇4 (non-test data Din or test data) To determine the output data Q. In this embodiment, the input signal selection circuit 1〇4 includes a first switching switch 1〇42, a second switching switch 1044, and a second switching switch 1G46. The first-switching switch includes an N-type field effect electric body M2 N-type field effect transistor M3 and an inverter 1〇48, so the first switching switch 1042 is selectively controlled according to a selection signal fox The path of the intestine is reduced; the first output terminal N] or a second output terminal & the second switching switch 1〇44 includes an N-type field effect transistor %, an n-type field effect transistor %, and an inverter owing It is used to selectively reduce the first output terminal % to the gastric material output end or the second data output end team according to the non-testing material/drilling device's third switching switch 1〇46
Q 1303317 係包含有一N型場效電晶 相态1052，用來依據測試 於第一資料輪出端或 、-Ν型場效電晶體Μ7以及一反 貝料Tin選擇性地將第二輸出端Ν2麵接 第二資料輪出端NMt2。 此外，閂鎖電路1〇2包含 刪以及—電晶體m8，复中反相器、一第二反相器 預定電壓準位Vdd反相器⑽2係絲依據一第二Q 1303317 includes an N-type field effect crystal phase 1052 for selectively selecting the second output according to the first data wheel output or the - - - type field effect transistor Μ 7 and an anti-baked material Tin. Ν2 is connected to the second data wheel output NMt2. In addition, the latch circuit 1〇2 includes a deletion and a transistor m8, a complex inverter, a second inverter, a predetermined voltage level, and a Vdd inverter (10).
決定獅料所敝輸人帆 來依據第二預定W位？係用 入資料w決定其輸出端N=tr触端i所接收之輸 6斤產生之輸出資料vout2;以及電晶體 1= 91細於第：_壓準位V-⑽其兩端分別 〇σ ; 第—貝料輸出端N〇uti、Nout2。如圖所示，第，反相 器口刪之輸出端係輕接於第二反相器趣之輸入端，而第二反 相器腦之輸出端係搞接於第一反相器贈之輸入端。 本實施例中，掃描電路1〇8包含有一 p型場效電晶體M9、一 p 型場效電㈣m1g、以及複數個反及曝AND Gate)觀以及 1084。P型場效電晶體Μ9係依據驅動時脈vck來選擇性地將第二 預定電壓準位Vdd輸入反及閘1082之一輸入端n3 ; P型場效電晶 體M1G係依據驅動時脈％來選擇性地將第二預定電壓準位〜輸 入反及閘1084之一輸入端n4 ;以及反及閘1082之輸出端係用來 輸出掃描資料SCAN_Q，請注意，反及閘1084之輸出與反及閘 1082之輸出係互補，因此可依據電路設計需求而自反及閘1〇84 10 1303317 之輸出端輸綺描資料SCAN—Q的互補峨。另—方面，如第】 °斤示本^月暫存電路1〇〇另包含二位準調整電路麵接於閃鎖 電路102，其分別由二反相器11〇、112構成，用來分別將輸出端 N5所產生之輸出資料V_與輸出端N6所產生之輸出資料ν_轉 換為輸出資料Q與輸出資料QB。 Μ >考第2圖’第2圖為第i圖所示之暫存電路励的操作時 序圖。為方便說明暫存電路綱的運作，暫存電路謂之初始條 件以第2圖中T。時為起始。當驅動時脈％由％⑽切換至〜卜時， ^型場效電晶體Ml開始導通；由於τ。時選擇訊號肌為低電壓 準位vlow，因此可得知目前暫存電路1〇〇是操力於一非測試模式， 亦即非，試資料％係作為暫存電路1〇〇所處理的輸入資料Vin， 為方便說明，假設測試資料Tin和非測試資料％係相同。此時， 第-切換開關1042 _的N型場效電晶體M3導通和N型場效電曰 體m2關職使得N型場效電晶體⑽、M3、第均換開關= 電路！02形成通路的狀態，且在τ〇時非測試資料％為 回電壓準位vWgh，造成N型場效電晶體M6導通而n型場效電晶 體M7關閉，因此一第一放電電流^會從第一資料輸出端^ = 接地端(vgnd)進行放電，而此放電動作會迫使閃鎖電路啲之如第一Deciding that the lions will lose the sails according to the second predetermined W position? The data w is used to determine the output data vout2 generated by the input N=tr contact i received by the input terminal 6; and the transistor 1=91 is finer than the:_pressure level V-(10) ; The first - shell output terminals N〇uti, Nout2. As shown in the figure, the output end of the inverter port is lightly connected to the input end of the second inverter, and the output end of the second inverter brain is connected to the first inverter. Input. In this embodiment, the scanning circuit 1A8 includes a p-type field effect transistor M9, a p-type field effect device (4) m1g, and a plurality of inverse and exposure gates and 1084. The P-type field effect transistor Μ9 selectively inputs the second predetermined voltage level Vdd to the input terminal n3 of the gate 1082 according to the driving clock vck; the P-type field effect transistor M1G is based on the driving clock % Optionally, the second predetermined voltage level is input to the input terminal n4 of the gate 1084; and the output of the gate 1082 is used to output the scan data SCAN_Q. Please note that the output of the gate 1084 is reversed. The outputs of the gates 1082 are complementary, so the complementary outputs of the SCAN-Q can be transposed from the output of the gate 1〇84 10 1303317 according to the circuit design requirements. In another aspect, the first temporary storage circuit 1 is further included, and the two-position adjustment circuit is connected to the flash lock circuit 102, which is respectively composed of two inverters 11〇 and 112, respectively for respectively The output data V_ generated by the output terminal N5 and the output data ν_ generated by the output terminal N6 are converted into an output data Q and an output data QB. Μ > Test Figure 2' Figure 2 is an operational timing diagram of the temporary circuit excitation shown in Figure i. In order to facilitate the operation of the temporary storage circuit, the initial condition of the temporary storage circuit is T in Figure 2. The time is the start. When the drive clock % is switched from % (10) to ~ Bu, the ^ field effect transistor M1 starts to conduct; due to τ. When the signal muscle is selected as the low voltage level vlow, it can be known that the current temporary storage circuit 1 is operating in a non-test mode, that is, the non-test data % is used as the input processed by the temporary storage circuit 1 The information Vin, for convenience of explanation, assumes that the test data Tin and the non-test data % are the same. At this time, the N-type field effect transistor M3 of the first-switching switch 1042_ is turned on and the N-type field effect transistor m2 is turned off to make the N-type field effect transistor (10), M3, and the average switching switch = circuit! 02 forms the state of the path, and when τ〇, the non-test data % is the return voltage level vWgh, causing the N-type field effect transistor M6 to be turned on and the n-type field effect transistor M7 to be turned off, so a first discharge current ^ will be The first data output terminal ^ = ground terminal (vgnd) discharges, and this discharge action forces the flash lock circuit to be as good as the first
反相器1022中輸出端〜的電塵下降，再加上驅動時脈V 時’掃描電路⑽之P型場效電晶體M9、Miq為不導通二: 了輸出端N5之電壓的下降。由於第—反相器· 接於第二反相器順之輸入端， 如係耦 弟一反相益1024之輪出端n6 1303317 係搞接於第-反相器1022之輸入端，因此輸出端&之電壓就會 被放電至ον ’因此本發明暫存電路100之反相器11〇的輸出資料 Q的電壓為vdd;另一方面，輸出端队之電壓就會同時被鎖住為 -而電壓準位，同樣地，本發明暫存電路励之反相器112的輸 出貧料QB的電壓為ον。同時，掃描電路1〇8之反及閘1〇82以 及反及閘1084會刀別輕合輸出端之低電壓準位和輸出端队之 高電壓準位而使得輸出掃描資料SCAN—Q之電壓準位會和輸出資 料Q樣，由於反及閘1082和反及閘1〇84之接法與習知閂鎖技 術一樣，因此其掃描資料SCAN—Q的操作於此便不加贅述。 接著，於τ〗時.，驅動時脈Vck由切換至Vi〇w，因此N型 場效電晶體从切換為不導通狀態，表示㈣型場效電晶體％、 Μ3第一切換開關1046以及閃鎖電路1〇2戶斤才冓成的電流路徑為開 路；同時，掃描電路1〇8之Ρ型場效電晶體Μ9、⑷則切換成導 通狀態而開始對輸出端Ns和輸出端\進行充電，因此會造成輪 出端Ns和Ν6之輸出電壓V〇utl和v〇ut2都是高電壓準位，亦即兄^ j 掃描電路1〇8之反及閘1〇82以及反及閘1〇84會分職合輸出^ Ns之高電壓準位和輸出端&之高電壓準位而使得輸出掃描資料 SCAN—Q維持（hold)在1〇和Τ】時的輸入準位，如第2圖中^ 至丁2的時段所示。同時，由於輸出端和队之輸出電壓^如和 Vout2都是高電壓準位，因此會強迫輸出資料q與輸出資料均 為0V。其餘時脈間Din改變由Vhigh切換至Vl〇w時工作原理與以上 相同’因此泮細運作不加贅述。 1303317 明參考第3圖，第3圖為本發明掃描暫存電路2⑻之-實施例 的不思圖。掃描暫存電路施係以串接方式連結複數個暫存電路， 凊注思’在不影響本發明技術揭露之τ，第3圖巾麵示出四個 暫存電路202a、202b、202c、202d，其中每-暫存電路2〇2a、202b、 202c 202d的結構與運作均與第！圖所示之暫存電路獅相同， 亦即每一替電路耻、獅、施、2_均包含有第丨圖所示 的門鎖電路102、輸人訊號選擇電路1()4、控制電路iQ6以及掃描 電路108。μ注意’除了第—個暫存電路观&之外，每一暫存電 路之掃描電路係输於τ —暫存電路之輸人訊賊㈣路，用來 將所產生之掃&雜S CAN—Q輸人下—暫存電如χ作為其測試資 料Tin。由於本發明掃描暫存電路2〇〇中每一暫存電路施、鳩、 臟、删的内部結構和其梯作方法均已在第i圖所示的實施例 中詳細描述’故在此不加魏。另—方面，每—暫存電路施、 02b 202e 2G2d之控制電路均#接於—共同的驅動時脈Vck，因 此本發明掃描暫存電路·由單—驅動時脈％來控制其運作。 當本發明掃描暫存電路勘要做正常的電路操作時，每個暫存電 路騰、202b、施、施内之第一切換開關（例如第】圖所示 之第刀換開關1042)之選擇訊號弧將會是低電壓準位而將非 測試資料Din做為輸人資料&，且每個暫存電路施、鳩、施、 2〇2d内之附貞電路（例如第！圖所示之閃鎖電路卿的輸出資 料Q會依據電路設計而傳遞至特定的運算電路純、鳩、職、 测來進行後續資料處理，例如運算電路撕〜綱d可以是骨牌 1303317 互補金氧半導體邏輯電路(D〇mino CMOS Logic)。請參考第3圖之 運算電路204a，其係由n個串接之骨牌邏輯電路趣⑴〜施⑻ 所組成，而且該n個串接之骨牌邏輯電路2〇4a(1)〜2〇4a(n)共用該 驅動時脈Vek。 當本發明掃描暫存電路2〇〇要做測試掃描動作時，每一個暫存 電路202a、202b、202c、202d内之第-切換開關（例如第】圖所 示，第-切換關1G42)的選擇訊號舰將會是高電壓準位而將 測4貝料Tin做為輸人資料vin。請參考第4圖，第4圖為第3圖 所不之掃&暫存電路200的操作畴圖。為方便說明掃描暫存電 路200的運作’掃描暫存電路2〇〇之初始條件以第4圖中τ。為起 始此時，驅動時脈vck從u換至vhigh，測試資料Tin的輸入 f料為τ!，因此暫存電路施讀取㈣料開始賴τ】，而其掃描 =貝料SCAN—Q亦開始變成Tl。於Τι時，驅動時脈％再次從I 切換至vhigh，此時測試資才斗Tb的輸入資料為A，因此暫存電路 2〇2b讀取的資料開始變成Τ2，且其掃描資料父颜―q亦開始變成 T2 ;而如第4圖所示，暫存電路施在τ丨時剛好讀取到暫存電路 2〇2a的掃描資料SCAN—Q。以此類推，熟習此項技藝者將可以輕 易瞭解本發明掃描暫存電路2_需單—個驅動時脈％即可完成 測試掃描操作。相較於習知技術，使用單一個軸時脈％不僅可 以不需受顺另—驅_脈她之間的限制，而且本身驅動時脈 vck的時脈相位平_Gekbalanee)亦可自由調整；另—方面，样 明掃描暫存電路200分別將輪出資料Q和掃描資料SCAN Q使用 1303317 的運作更適合應用於動態電路 在正常的電路操作和測試掃描動作 架構中。 【圖式簡單說明】 第1圖為本發明暫存電路之—實施例的示意圖。 第2圖為第1圖所示之暫存電路的操作時序圖。 第3圖為本發明掃描暫存電路之一實施例的示意圖。 第4圖為第3圖所示之掃描暫存電路的操作時序圖。 【主要元件符號說明】 1.00、202a〜202d 暫存電路 ~ 102 閂鎖電路 —~ 104 輸入訊號 106 控制電路 ^ ^ 108 掃描電路 ~~ 110、112、1022、1024、1048、1050、 1052 200 掃描暫存量瓦 204a〜204d 運算電路~ ' 204a(l)〜204a(n) 骨牌邏輯泰系^~~~~~~ ——__ 1303317 1042、1044、1046 切換開關 1082 、 1084 反及閘The electric dust of the output terminal of the inverter 1022 is lowered, and when the driving clock V is applied, the P-type field effect transistors M9 and Miq of the scanning circuit (10) are non-conducting: the voltage of the output terminal N5 is lowered. Since the first inverter is connected to the second inverter and is connected to the input end of the first inverter, the output is connected to the input terminal of the first inverter 1022. The voltage of the terminal &amplifier is discharged to ον'. Therefore, the voltage of the output data Q of the inverter 11 of the temporary storage circuit 100 of the present invention is vdd; on the other hand, the voltage of the output terminal is simultaneously locked. - The voltage level, and likewise, the voltage of the output lean QB of the inverter 112 excited by the temporary circuit of the present invention is ον. At the same time, the anti-gate 1〇82 and the anti-gate 1084 of the scanning circuit 1〇8 will lightly combine the low voltage level of the output end and the high voltage level of the output end group to output the voltage of the scan data SCAN-Q. The level will be the same as the output data Q. Since the connection of the anti-gate 1082 and the anti-gate 1〇84 is the same as the conventional latching technique, the operation of the scanning data SCAN-Q will not be described here. Then, at τ〗, the driving clock Vck is switched to Vi〇w, so the N-type field effect transistor is switched from the non-conducting state, indicating (four) type field effect transistor %, Μ3 first switching switch 1046 and flashing The current path of the lock circuit 1〇2 is only an open circuit; at the same time, the 场-type field effect transistor Μ9, (4) of the scanning circuit 1〇8 is switched into an on state to start charging the output terminal Ns and the output terminal\ Therefore, the output voltages V〇utl and v〇ut2 of the wheel terminals Ns and Ν6 are both high voltage levels, that is, the gates of the scanning circuit 1〇8 and the gates 1〇82 and the gates 1反84 will divide the high voltage level of the output ^ Ns and the high voltage level of the output & and make the output scan data SCAN-Q maintain the input level at 1〇 and Τ, as in the 2nd The period from ^ to D is shown in the figure. At the same time, since the output voltage of the output terminal and the team, such as Vout2, and the Vout2 are both high voltage levels, the output data q and the output data are forced to be 0V. When the rest of the clock changes from Vhigh to Vl〇w, the working principle is the same as above. Therefore, the operation is not described here. 1303317 Referring to FIG. 3, FIG. 3 is a diagram of an embodiment of the scanning temporary storage circuit 2 (8) of the present invention. The scanning temporary storage circuit is configured to connect a plurality of temporary storage circuits in series, and the present invention does not affect the τ disclosed in the technical disclosure of the present invention. The third drawing shows four temporary storage circuits 202a, 202b, 202c, and 202d. The structure and operation of each of the temporary storage circuits 2〇2a, 202b, 202c 202d are the same! The temporary circuit lion shown in the figure is the same, that is, each circuit shame, lion, Shi, 2_ includes the door lock circuit 102 shown in the figure, the input signal selection circuit 1 () 4, the control circuit iQ6 and scanning circuit 108. μ Note that in addition to the first temporary storage circuit view, the scanning circuit of each temporary storage circuit is input to the input thief (four) road of the τ-temporary circuit, which is used to generate the sweeping & S CAN—Q loses people—temporary storage of electricity such as χ as its test data Tin. Since the internal structure of each temporary storage circuit in the scanning temporary storage circuit 2 of the present invention, the internal structure of the dirty, the deleted, and the ladder method thereof have been described in detail in the embodiment shown in the first embodiment, Plus Wei. On the other hand, the control circuit of each temporary storage circuit, 02b 202e 2G2d is connected to the common driving clock Vck, so the present invention scans the temporary storage circuit and controls the operation of the single-drive clock. When the scanning temporary storage circuit of the present invention is to perform normal circuit operation, the selection of the first switching switch (for example, the first knife changing switch 1042 shown in the first drawing) of each temporary storage circuit, 202b, and application The signal arc will be the low voltage level and the non-test data Din will be used as the input data & and each temporary circuit will be applied, 鸠, 施, 2贞2d in the attached circuit (for example, as shown in the figure! The output data Q of the flash lock circuit will be transmitted to the specific operation circuit according to the circuit design, such as pure, 鸠, job, and measurement for subsequent data processing. For example, the operation circuit tearing can be a domino 1303317 complementary MOS logic circuit. (D〇mino CMOS Logic). Please refer to the operation circuit 204a of FIG. 3, which is composed of n serially connected domino logic circuits (1) to (8), and the n serially connected domino logic circuits 2〇4a (1) ~2〇4a(n) shares the driving clock Vek. When the scanning temporary storage circuit 2 of the present invention performs a test scanning operation, the first in each temporary storage circuit 202a, 202b, 202c, 202d - Toggle switch (for example, the first diagram, the first - switch off 1G42) The ship will be at a high voltage level and will measure 4 Bein Tin as the input data vin. Please refer to Figure 4, and Figure 4 is the operational domain diagram of the sweep & temporary memory circuit 200 of Figure 3. To facilitate the description of the operation of the scan temporary storage circuit 200, the initial condition of the scan temporary storage circuit 2 is shown as τ in Fig. 4. At this time, the drive clock vck is changed from u to vhigh, and the input of the test data Tin is input. f material is τ!, so the temporary circuit is read (four) material starts to τ], and its scan = shell material SCAN-Q also begins to become Tl. In Τι, the drive clock % is switched from I to vhigh again, this When the input data of the test capital Tb is A, the data read by the temporary storage circuit 2〇2b starts to become Τ2, and the scan data parent-q also starts to become T2; and as shown in FIG. 4, the temporary storage When the circuit is applied to τ丨, it just reads the scan data SCAN_Q of the temporary storage circuit 2〇2a. By analogy, those skilled in the art can easily understand that the scan temporary storage circuit 2_ requires a single drive. The pulse scan can complete the test scan operation. Compared with the prior art, the use of a single axis clock pulse can not only be subject to The _ pulse between her, and the clock phase of the driving clock vck itself _Gekbalanee) can also be freely adjusted; on the other hand, the sample scanning temporary storage circuit 200 will rotate the data Q and scan data SCAN Q The use of 1303317 is more suitable for dynamic circuits in normal circuit operation and test scan action architectures. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing an embodiment of a temporary storage circuit of the present invention. Fig. 2 is a timing chart showing the operation of the temporary storage circuit shown in Fig. 1. FIG. 3 is a schematic diagram of an embodiment of a scan temporary storage circuit of the present invention. Fig. 4 is a timing chart showing the operation of the scanning temporary storage circuit shown in Fig. 3. [Main component symbol description] 1.00, 202a~202d Temporary circuit ~ 102 Latch circuit -~ 104 Input signal 106 Control circuit ^ ^ 108 Scanning circuit ~~ 110, 112, 1022, 1024, 1048, 1050, 1052 200 Scanning Storage tile 204a~204d Operation circuit ~ '204a(l)~204a(n) Domino logic Thai system ^~~~~~~ __ 1303317 1042, 1044, 1046 Switch 1042, 1084