1303066 九、發明說明： 【發明所屬之技術領域】 [0001]本發_陳轉體記憶體元件，更碰的說，是 包括一個輔助電荷的半導體記憶體元件。 【先前技術】 [0002]傳統的電性可程式化唯讀記憶邮pR〇M)隧道 化層(ETOX)快閃έ己憶體單元和傳統的氮化的唯讀記憶體單元 文限於因為執行程式化操作所需的大電流的低效率程式化。 ΕΤΟΧ㈣記讎和氮化的唯讀記憶體單元是㈣道熱電子 (CHE)注入，以將該單元程式化至高電壓的方式被程式化。熱 電=是在一個半導體元件中的一個很強的電場區域被加迷= 獲得非常高的動能的電子，例如ΕΤ〇χ或氮化的唯讀記憶體半 導體το件。通道熱電子注人發生在當閘極和汲極電壓相當 源極電壓。 、 [0003] 由源極行進至汲極的通道載子有時候會因很高的 閘極電[在匕們到達汲極之前被驅至閘極。沒有被閘極氧^匕層 捕獲的注人載子會魏雜電流。通道熱電子敝人效率是^ 小的’而朋通道熱電子注人雜式化需要很大的料化電流 ’因此，相對於浪費的電流，通道熱電子注入是沒有效率的t [0004] 另一種§己憶體單元，一個phjnbs記憶體單元 ，帶對帶熱電洞(BTBHH)注人’以將該單元程式化至低電壓。 母「個PHINES記讎單元，能夠儲存兩個位元。一個位元能 夠被儲存在電晶體的源極端，以及—個位元能夠被儲存在電晶 1303066 體的及極。在這些$憶體單元，每—個位元能夠有兩個狀態 ，二個，電流狀態，代表著邏輯”r，，和—個低電流狀態，代 表著邏輯0。記顏單元的每—邊藉由檢酿職單元的電 流和決定是否該電流高或低於一個門檻值來被讀取。 ’ _5]被抹除單元的帶對帶電流是締擁式化的帶對 • 帶電流。因為這個理由，每—個單元每-邊的狀態，被程式化 的或疋未被転式化的’能夠藉由比對流經每一個單元每一邊的 電流和服絲被決定，例如，—個閘極纽極或閘極至源極 • 電流門檻值。 [0006]在一個PHINES記憶體元件，儲存在氮化物層的電 荷月b夠被一個稱為佛羅諾德漢(F〇wier-N〇rdheim)注入的步驟 所抹除。在一個抹除週期中，抹除電壓被加到源極，汲極，閘 極’和電㉟體的基底，導致電？雜〇N()層的底部氧化層障 • 礙進入氮化物層。這些電子可以補償在程式化中注入氮化物層 的電洞。該底部氧化層的穿隧，可以發生在，電晶體抹除電壓 的應用，所產生的高電場，而且是一種量子機械穿隧的形式。 _ [0007]被帶對帶熱電洞注入所程式化可能還是太慢，而且 對某些應用可能要求太長的程式化時間。 【發明内容】 [0008] 個辅助電荷記憶體單元包含一個電晶體其包含 例如、個P型基底以及在p型基底植入n+源極區域和n+ 汲極區域。一個閘極電極被形成在基底以及部分源極和汲極區 域上。該閘極電極包含一個捕捉層。 [0009] 在個特徵，該捕捉層在電性上被認為被分成兩邊 1303066 。一邊被當成輔助電荷端，藉由捕捉電子在該層中，可以被固 定在一個高電壓。該電子被當成是輔助電荷。另一邊可以被用 來儲存資料，是被當成資料端。介於輔助電荷端和資料端之間 的陡峭的電場，可以促進程式化效率。 [0010]本發明的這些和其它面貌，特徵，和實施例，會在 下列實施方式的章節中被描述。 【實施方式】 • [0024]第一圖是依在此描述的系統和方法的實施例，所配 置輔助電荷記憶體元件100的圖示。輔助電荷記憶體元件100包 括一個包含矽基底102的電晶體。矽基底1〇2可以成為其餘記憶 體元件100在上面製造的一個基部材料。兩個n+區域1〇4和106 能夠由摻雜矽基底102所產生。這些區域1〇4和1〇6能夠分別當 - 成電晶體的源極和汲極。一個ΟΝΟ層1〇8能夠被置於矽基底1〇2 之上和η+區域104和106之間。一個多晶矽層(未示於此)能夠被 置於ΟΝΟ層108之上，以形成該電晶體的閘電極。 _ [0025]ΟΝΟ層108包括一個夾於兩個氧化層之間可以捕 捉電荷的氮化物層110。例如，向上行進穿越底部氧化層被捕獲 在氮化物層中的電子。這些電子可以形成一個輔助電荷，或被用 來儲存資料’如下更進一步描述。 [0026]捕捉層108可以，例如，被分成兩邊。一邊可以被 當成輔助電荷端112。輔助電荷端112可以，藉由捕捉在氮化物 層110中的輔助電荷，被固定在一個高電壓。另一邊可以被當成 是資料端116，而且可以被用來儲存資料。該資料可以由儲存在 資料端116的電位來表示，而且將會更加詳細描述如下。 1303066 [0027] 個介於辅助電荷端112和資料端μ之間陡山肖的 電场區域118會獅成。該㈣的電場區域，跟據該實施例，藉 由限制程式化賴或降健式化咖，可啸升程式化的效率。 例如’在獅電荷邊112的高賴，可以關在熱電子程式化中 的程式化電流，將會參照第2A圖描述如下。 [0028] 第2A圖疋描述一個範例輔助 子程式化賴示，例如第―财所描述，與在此描述的系統和方 法的實施例-致。在-個傳統的記憶體單元，閘極的正電壓吸引 從P型基底來電子。這些電子被吸引至接近至石夕表面，源極和汲 極間的電晶體區域。這個區域就是所知的通道。麵始通道是一 個非傳導區域；然而，當閘極電壓變的得更多的正電壓，足夠的 電子被從P型基錄進通道，贿立極和汲姻被充電的 路徑。電子從源極經電晶體通道流至汲極，其中這些電子經由 ΟΝΟ層108白勺底層氧化層注入氮化物電荷捕捉層11〇。假如〇 伏，或很低的電壓’被施加在閘極上，沒有電子，或至少非常少 ，被吸引至通道，源極和汲極被有效的切斷，很少或沒有電流流 經通道。結果，將會是很少的電子被捕捉在氮化物層11〇。 [0029] 輔助電荷記憶體元件1〇〇的辅助電荷端112是被捕 捉電子114,在層1〇〇中的輔助電荷，固定在一個高％。辅助電 荷電子114減少被拉進辅助電荷端112下方通道的區域2〇2電子 的數目，因為這些電子的負電荷排斥在區域2〇2的電子。這個可 以限制在熱電子程式化的過程中的程式化電流，以減少需要的程 式化功率。 [0030] 如第2Α圖所描述，當施加正確的程式化電壓，辅 助電荷電子114已出現，電子200將從源極1〇4朝汲極1〇6流動 1303066 ,電子的w動’如上所描述，可以被限制在辅助電荷端⑴中的 電子114。依這個方式，傳統元件所需要的大程式化電流，在某 些應用上能夠被減少。當電子2⑻從源極ω4行進至汲極廳， 它將會行經位於辅助電荷端112和資料端116間晴的電場。某 -電子例如電子2〇〇 ’將會穿越底部氧化層進入資料端116的 電荷捕捉氮化物層110。 [0031]在程式化的期間，程式化電壓被施加至閑極和沒極 電極’當源極電極是接地，或是接至0伏特。例如，源極和 閘極108接至5伏特。可以了朗是，獨的電歸被用於不同 的應用上。 。[0032]第2Β圖是描述一個範例辅助電荷記憶體單元抹除 操作的圖示，例如第―圖中所描述，與在此描述的系統和方法的 實施例一致。當抹除辅助電荷記讎元件1GG，電洞從汲極廳 行進至閘極，而且補償被捕捉在氮化物層11〇中的電子。抹除電 壓可以被施加在閘極，汲極，和源極，以產生電壓差，以導致電 洞250從汲極1〇6，經氧化層130，流至氮化物層11〇。電洞25〇 可以補償電子200以移除資料端116的電荷。許多的記憶體單元 月b夠被整塊，或整頁，或整區塊的抹除。依這個方式，可以避免 較慢的帶對帶熱電洞的限制，因為很多單元能夠被一次抹除。 [0033] 當抹除辅助電荷記憶體元件1〇〇，源極ι〇4接地， 及極106接至4.5伏特，而閘極接至伏特。可以了解的是，這 些是可能被使用的電壓值的範例。 [0034] 第3圖是描述一個範例輔助電荷記憶體單元3〇2， 304，306，308，310，312，314，和 316 的陣列 300 的圖示。輔 助電荷記憶體單元 302，304，306，308，310，312，314，和 316 1303066 可以配置成如第-和第二圖所描述。單元3G2，3〇4，3G6，施 310 312，314，和316 ’可以被安排在’例如本範例4χ2陣 列結構’的_結射。但是其他包括财歧較少的單元的陣 列結構也是可能的。 [0035] 辅助電荷記憶體每一個單元如2，3〇4，306，和308 的^極端連接至字元線(版几㈣私，而辅助電荷記憶體每一 個單元310，312，314，和316的閘極端連接至字元線(w〇rd Lme)灰乙^。依這個方式，一個電壓可以同時施加在陣列中許多 單元的閘極。更進一步，每一個單元302，304，306，和308可 以被連接’使得從-解元的雜端連接至另—解元的汲極端 〇 [0036] 例如，單元302的汲極與單元3〇4的源極相接在連 接點318。連接點318也連接至位元線(Bit Line)氣n，见 ’万h+1 ’和见…如圖所示，有相似的連接方式。依這個方式， 電，可以加至每-個單元3〇2，3〇4，郷，和篇的閘極和沒極 。單το 310 ’ 312，314，和316有相似的連接方式。藉由位元線 和字元線的連接，電壓可以被施加至單元3〇2，3〇4，3〇6，3〇8 ’ 310 ’ 312 ’ 314和316，以程式化或抹除單元3〇2，3〇4，3〇6 ’ 308 ’ 310，312，314 和 316。程式化和抹除單元 3〇2，3〇4 , 306 ’ 308 ’ 310 ’ 312，314和316，將會參照第4-11圖更進一步 描述如下。 [0037]第4圖是一個描述陣列3〇〇的圖示，其中一個辅助 電荷是被儲存在陣列300中的每一個輔助電荷記憶體單元中。參 照第1，2A，2B圖所描述，電晶體302，304，306，308，310 ，312，314和316每-個都有一個輔助電荷端和一個資料端。 13〇3〇66 該輔助電荷端包含-個電子，或電子術，綱，概，侧，4i〇 412 ’ 414 ’和416。通常很多電子可以被用來在輔助電荷邊產 生-個被充負電的區域。該電子的數目將依不同的應用而有所不 同例如’在某些實施例，比較小的單元需要比較少的電子。 _ [⑻38]在—個實施例中，-個單元的輔助電荷端被連接到 ，壁單元的輔助電荷端。例如，單元搬和單元有辅助電荷 端^)2和4〇4，被安排相互連接。在這個例子，單元3〇2的辅助 電，端是在單元302的汲極端，然而，單元的辅助電荷端是 在單元304的源極端。單元3〇2驗極被連接到單元3〇4的源極 ’如^描述’整頁/整區塊的抹除可以被執行。此整頁/整區塊的 抹除操作可以，例如，抹除整個元件，參照第6圖描述如下，或 是該整頁/整區塊的抹除操作可以抹除某些部分。 一 [_]第5圖是描述一個程式化陣列300的範例方法的圖 不’與在此描述的系統和方法的實施例一致。在陣列3〇〇中的輔 助電荷記憶體單元可以被單獨馳式化，藉由施加不同的電壓至 f確的字元線和位元線。辅助電荷記憶體單元3〇4可以，例如， 藉由施=0伏特至U伏特至I，和5伏特至既被程式 化、。依個方式，單元3〇4將會有〇伏特的源極電壓以及5伏特 的汲極電壓。參照第2A圖所描述，電子5〇2將從源極流至汲極 ，以及一些電子502將會穿越底部氧化層，進入在單元3〇4資料 端的電荷捕捉層。 、 >…[0040]在-個程式化操作的期@，其它的位元線可以被允 許洋接’而且0伏特會被加到其它的字元線上。因此，例如，沒 有電流會流進電晶體302，306，308，310，312，314，和316 ’當單元304被程式化。因此，在陣列3〇〇中的其它單元被允許 1303066 - ’例如’轉未被程式化，或轉在前-倾程式化的值。 [0041] 上述所提及的例子，以及第6_8，⑴·12 _例子， 不於圖中每一個位元線的電壓被認為是-個沒極t壓，Vd。可以 I解的是’在第3_5圖中的範例，一個單元的及極端，依據特別 • 陣列結構的應用，可以被連接至其它單元的源極端。此外，依據 一 記憶體疋件的大小’較多或較少的單元可以組成該陣列架構。 [0042] 第6 ®是贿第3圖_的歸·區塊抹除的一 個範例方法的圖示，與在此描述的系統和方法的實施例一致。在 • 陣f 中的辅助電荷記憶體單元，能夠被整頁或整區塊抹除， 也就是’-次料的位元’藉由施加不同的電驗正確的字元線 和位元線。輔助電荷記憶體單元3〇2，3〇4，3〇6，3〇8，3i〇，312 ’ 314和316可以’例如，藉由使用第6圖所描述的方法，被一 ' 次抹除。 - [0043]例如’第6圖所示，施加〇或4.5伏特到正確的位 元線，以及施加-8伏特到適當的字元線，如第6圖所示，每一個 輔助電荷記憶體單元302，304，306，308，310，312，314和 • 316 ’將會有一個0伏特的源極電壓，一個5伏特的汲極電壓， 和-個-8伏特的閘極電壓’與第2B圖的輔助電荷記憶體元件ι〇〇 相同。這些單元的源極和閘極電壓差是8伏特，以及汲極和閘極 電壓差疋12.5伏特。在汲極和閘極的大電壓差，電洞從沒極流 到閘極。電洞能夠補償儲存在輔助電荷記憶體單元的資料端的電 子0 [0044]第7圖是描述讀取陣列3〇〇的一個範例方法的圖示 ，與在此描述的系統和方法的實施例一致。藉由施加特定的電壓 至適當的字元線和位元線，能夠讀取個別的單元，相似於參照第 -12- 1303066 5-6 “圖所精触式彳冰抹除树論 ― 頊取的單元的源極或沒極可以被允許 圖中所示，尚未被 [0045]例如，用呢 記憶體單元3〇2。在一個實施例以讀取，獅電荷 3伏特，源極電_@ j 6 _ ^302的間極電壓可以是 依這個方式，當單特’和可以是〇伏特。 、田早το 302的貧料端沒有儲 ，當單元3_資料打又存電何，電流可以流動 電流产動了、有存了’觀有流動，或是很少 電_動。可以了解的是，真正用 助電荷端的電荷數量，會影響這些電昼要求。 早兀、 狀能個實施例’很少或沒有電流可以指示一個邏辑 二的電流可以指示另—個邏辑狀態。在這樣一個 ^列赛在母-個記憶體單元中，可以儲存兩種狀態。此外，在 -士固广例$同的電解位可以指示儲存在每—個記憶體單 凡中的f重邏輯準位。例如，藉由儲存不同的電荷準位在單元 302的貧料端，不同的邏輯狀態可以被儲存。 [0047] 第8圖是描述輔助電荷記憶體單元的一個範例陣列 800的圖示，與在此描述的系統和方法的實施例一致。陣列簡 相似於陣列300 ’除了在位元線兩邊的辅助電荷，是交錯排列。 正如第9-11圖所示，程式化，抹除，和讀取，可以依第5，6， 和7圖，相似的方式執行。 [0048] 第9圖是描述程式化陣列8〇〇的一個範例方法的圖 示，與在此描述的系統和方法的實施例一致。在陣列⑽〇中的輔 助電荷記憶體單元，藉由施加特定的電壓至正確的字元線和位元 線’能夠被個別的程式化。輔助電荷記憶體單元902可以，例如 -13- ⑧ 1303066 ’口藉由施加=伏特至l，5伏特至亂，和5伏特至鼠，被 程式化。依這個方式，輔助電荷記憶體單元902將會有-個0伏 ，的源極電壓’-個5伏特的汲極電壓，和—個5伏特的閘極電 壓，與第2A圖的辅助電荷記憶體元件1〇〇相同。參照第2a圖 所描述，電子900可以開始由源極流向沒極，以及一些電子9⑻ 將會牙越第-氧化層，進人在單元的資料端電荷捕捉層。 [0049] 其它的位元線可以被允許浮接，以及〇伏的電壓將 會被施加在其它字元線上，所以，在程式化單元3〇4期間，在其 匕單元中，將會很少或沒有電流流動。依這個方式，其它單元維 持未被程式化，或維持在前一個被程式化的值。 [0050] 第1〇圖是描述執行一個整頁/整區塊抹除，近似於 上述第6圖之一個範例方法的圖示。因此，輔助電荷記憶體單元 902 ’ 904 ’ 906和908可以，例如，如第1〇圖所示，藉由施加〇 或4.5伏特至正確的位元線，以及，亦如第1〇圖所示，藉由施 加_8伏特至正確的字元線，被抹除。每一個辅助電荷記憶體單元 902 ’ 904 ’ 906和908將會有一個〇伏特的源極電壓，一個4 5 伏特的汲極電壓，和一個-8伏特的閘極電壓，與第2B圖的輔助 電射記憶體元件100相同。源極和閘極電壓差是8伏特，以及汲 極和閘極電壓差是12.5伏特。在汲極和閘極的大電壓差，將會 導致電洞從汲極流到閘極，其中電洞能夠補償儲存在辅助電荷記 憶體單元902，904，906和908資料端的電子。 [0051] 第11圖是描述讀取陣列800的一個範例方法的圖示 ’與在此描述的系統和方法的實施例一致。藉由施加特定的電壓 至正確的字元線和位元線’能夠讀取個別的單元。如第11圖中 所示，沒有被讀取的單元，其源極和汲極將可以被允許浮接。 -14- I3〇3〇66 ^ [0052]因此，用吸，亂】，和见可以讀取，辅助電荷 ，憶體單元9G2。單元9G2的閘極電壓可以是3伏特，源極電壓 可以是1.6伏特，和汲極電壓可以是〇伏特。依這個方式，當單 元902的負料端沒有儲存電荷，電流可以流動，當元件的資料端 ，儲存電荷，則沒有電流流動，或是很少電流流動。可以了解的 疋，真正用來讀取一個特定單元的源極，汲極，和閘極電壓，將 會依應用而不同，例如，儲存在單元輔助電荷端的電荷數量。 [0053]本發明的特定實施例已經在上面被描述，可以了解 的是，該被描述的實施例僅只是用於說明的範例而已。因此，本 發明應該不被限制於所描述的實施例。當然，在此所描述的本發 月的範圍，只月b依隨後的請求項和以上的描述以及伴隨的繪圖， 來限制。 【圖式簡單說明】 [0011] 為了更完整了解本發明，以及它的優點，下列描述 伴隨繪圖以供參考，其中： [0012] 第1圖是描述與一個實施例一致的範例輔助電荷記 憶體元件的圖示； [0013] 第2A圖是描述一個程式化第一圖的辅助電荷記憶 體單元的方法的圖示，與一個實施例一致； [0014] 第2B圖是描述一個範例第一圖的輔助電荷記憶體 單元的抹除方法的圖示，與該實施例一致； [0015] 第3圖是描述一個範例輔助電荷記憶體單元的陣列 的圖示； [0016] 第4圖是描述一個在每一個輔助電荷記憶體單元中 -15-1303066 IX. Description of the invention: [Technical field to which the invention pertains] [0001] The present invention is a semiconductor memory device including an auxiliary charge. [Prior Art] [0002] Traditional Electrically Programmable Read-Only Memory Posts pR〇M) Tunneling Layer (ETOX) Flash Flash Memory Units and Traditional Nitrided Read-On Memory Units are limited to execution Low-efficiency stylization of large currents required for stylized operations. The 唯 (4) 雠 and nitrided read-only memory cells are (iv) hot electron (CHE) implants that are programmed to program the cell to a high voltage. Thermoelectric = is a strong electric field region in a semiconductor component that is fascinated = electrons that obtain very high kinetic energy, such as germanium or nitrided read-only memory semiconductors. Channel hot electron injection occurs when the gate and drain voltages are equivalent to the source voltage. [0003] Channel carriers that travel from the source to the drain are sometimes driven to the gate by a very high gate [before we reach the bungee. The injected carrier that is not captured by the gate oxygen layer will have a mixed current. The efficiency of channel hot electrons is small. 'But channel hot electron injection requires a large amount of materialization current. Therefore, channel hot electron injection is inefficient compared to wasted current. [0004] § Recalling the unit, a phjnbs memory unit with a pair of thermoelectric holes (BTBHH) to program the unit to a low voltage. The mother "a PHINES recording unit can store two bits. One bit can be stored at the source end of the transistor, and one bit can be stored in the sum of the body of the crystal 1303066. In these $ recall Units, each bit can have two states, two, current states, representing logic "r,, and - a low current state, representing a logic zero. Each edge of the face unit is read by checking the current of the brew unit and determining whether the current is high or below a threshold. ’ _5] The strip-to-band current of the erased unit is the associated pair of strips • current. For this reason, the state of each side of each cell, stylized or untwisted, can be determined by comparing the current and the wire that flows through each side of each cell, for example, a gate. Kink or gate to source • Current threshold. [0006] In a PHINES memory component, the charge b stored in the nitride layer is erased by a step called F〇wier-N〇rdheim implantation. During an erase cycle, the erase voltage is applied to the source, drain, gate, and substrate of the 35-body, causing electricity? The bottom oxide layer of the hybrid N() layer • hinders entry into the nitride layer. These electrons compensate for the holes in the nitride layer that are implanted in the stylization. The tunneling of the bottom oxide layer can occur in the application of the transistor erase voltage, the high electric field generated, and is a form of quantum mechanical tunneling. _ [0007] Stylized with hot hole injection may be too slow, and may require too long stylized time for some applications. SUMMARY OF THE INVENTION [0008] An auxiliary charge memory cell includes a transistor including, for example, a P-type substrate and an n+ source region and an n+ drain region implanted in the p-type substrate. A gate electrode is formed on the substrate and a portion of the source and drain regions. The gate electrode includes a capture layer. [0009] In one feature, the capture layer is electrically considered to be split into two sides 1303066. One side is regarded as an auxiliary charge terminal, and by trapping electrons in the layer, it can be fixed at a high voltage. This electron is considered to be an auxiliary charge. The other side can be used to store data and is used as a data source. A steep electric field between the auxiliary charge terminal and the data terminal can promote stylized efficiency. These and other aspects, features, and embodiments of the present invention are described in the sections of the following embodiments. [Embodiment] [0024] The first figure is an illustration of an auxiliary charge memory element 100 configured in accordance with an embodiment of the system and method described herein. The auxiliary charge memory element 100 includes a transistor comprising a germanium substrate 102. The ruthenium substrate 1 〇 2 can be a base material on which the remaining memory element 100 is fabricated. Two n+ regions 1〇4 and 106 can be produced by the doped germanium substrate 102. These regions 1〇4 and 1〇6 can be used as the source and drain of the transistor, respectively. A ruthenium layer 1 〇 8 can be placed over the ruthenium substrate 1 〇 2 and between the η + regions 104 and 106. A polysilicon layer (not shown) can be placed over the germanium layer 108 to form the gate electrode of the transistor. ΟΝΟ [0025] The germanium layer 108 includes a nitride layer 110 sandwiched between two oxide layers to capture charge. For example, electrons that travel upward through the bottom oxide layer are trapped in the nitride layer. These electrons can form an auxiliary charge or be used to store data as described further below. The capture layer 108 can, for example, be divided into two sides. One side can be regarded as the auxiliary charge terminal 112. The auxiliary charge terminal 112 can be fixed at a high voltage by trapping the auxiliary charge in the nitride layer 110. The other side can be thought of as data side 116 and can be used to store data. This information can be represented by the potential stored at data terminal 116 and will be described in more detail below. 1303066 [0027] An electric field region 118 between the auxiliary charge terminal 112 and the data terminal μ will be formed. The (4) electric field region, according to this embodiment, can be ramped up by stylized efficiency by limiting the stylized or reduced-style coffee. For example, the stylized current that can be turned off in the thermal electronic stylization of the lion's charge side 112 will be described below with reference to Figure 2A. [0028] FIG. 2A depicts an example auxiliary sub-programming, such as the first description of the system, and the embodiments of the systems and methods described herein. In a conventional memory cell, the positive voltage of the gate attracts electrons from the P-type substrate. These electrons are attracted to the area of the transistor close to the surface of the stone, the source and the drain. This area is the known channel. The surface start channel is a non-conducting area; however, when the gate voltage becomes more positive, enough electrons are recorded from the P-type base into the channel, bribing the pole and the charged path. Electrons flow from the source through the transistor channel to the drain, wherein the electrons are implanted into the nitride charge trapping layer 11 via the underlying oxide layer of the germanium layer 108. If a volt, or a very low voltage, is applied to the gate, no electrons, or at least very little, are attracted to the channel, the source and drain are effectively cut, with little or no current flowing through the channel. As a result, very few electrons will be trapped in the nitride layer 11〇. [0029] The auxiliary charge terminal 112 of the auxiliary charge memory element 1 is the trapped electron 114, and the auxiliary charge in the layer 1 is fixed at a high %. The auxiliary charge electrons 114 reduce the number of electrons in the region 2〇2 that are pulled into the channel below the auxiliary charge terminal 112 because the negative charge of these electrons repels the electrons in the region 2〇2. This limits the stylized current during the thermal electronics stylization to reduce the amount of power required. [0030] As described in FIG. 2, when the correct stylized voltage is applied, the auxiliary charge electrons 114 have appeared, and the electrons 200 will flow from the source 1〇4 toward the drain 1〇6, 1303066, and the electrons move as above. Description, electrons 114 that can be confined in the auxiliary charge terminal (1). In this way, the large stylized current required by conventional components can be reduced in some applications. As the electron 2(8) travels from the source ω4 to the bungee hall, it will travel through the electric field between the auxiliary charge terminal 112 and the data terminal 116. An electron, such as electron 2, will pass through the bottom oxide layer into the charge trapping nitride layer 110 of the data terminal 116. [0031] During the stylization period, the stylized voltage is applied to the idle and the electrodeless electrodes' when the source electrode is grounded or connected to 0 volts. For example, the source and gate 108 are connected to 5 volts. It can be said that the unique electricity is used in different applications. . [0032] Figure 2 is a diagram depicting an exemplary auxiliary charge memory cell erase operation, such as described in Figure 1, consistent with embodiments of the systems and methods described herein. When the auxiliary charge memorizing element 1GG is erased, the hole travels from the bungee hall to the gate, and the electrons trapped in the nitride layer 11〇 are compensated. The erase voltage can be applied to the gate, drain, and source to create a voltage difference to cause the hole 250 to flow from the drain 1 〇 6 through the oxide layer 130 to the nitride layer 11 〇. The hole 25 〇 can compensate the electron 200 to remove the charge of the data terminal 116. Many memory cells are blunted enough, or the entire page, or the entire block. In this way, the slower band-to-spot thermocouple limitation can be avoided because many cells can be erased at once. [0033] When the auxiliary charge memory element 1 is erased, the source ι 4 is grounded, and the pole 106 is connected to 4.5 volts, and the gate is connected to volts. It can be understood that these are examples of voltage values that may be used. [0034] FIG. 3 is a diagram depicting an array 300 of exemplary auxiliary charge memory cells 3〇2, 304, 306, 308, 310, 312, 314, and 316. The auxiliary charge memory cells 302, 304, 306, 308, 310, 312, 314, and 316 1303066 can be configured as described in the first and second figures. The units 3G2, 3〇4, 3G6, 310s 312, 314, and 316' may be arranged in the _-ejection of, for example, the 4 χ 2 array structure of the present example. However, other array structures including cells with less fiscal differences are also possible. [0035] Each of the auxiliary charge memories, such as 2, 3 〇 4, 306, and 308, is connected to the word line (version (4) private, and the auxiliary charge memory is used for each unit 310, 312, 314, and The gate terminal of 316 is connected to the word line (w〇rd Lme). In this manner, a voltage can be simultaneously applied to the gates of many cells in the array. Further, each cell 302, 304, 306, and 308 can be connected 'so that the miscellaneous end of the de-union is connected to the other - de-element of the de-element [0036] For example, the drain of cell 302 is connected to the source of cell 3〇4 at connection point 318. 318 is also connected to the bit line gas n, see '10,000 h+1' and see... as shown, there is a similar connection. In this way, electricity can be added to each unit 3〇 2,3〇4,郷, and the gate and the pole. The single το 310 ' 312, 314, and 316 have similar connections. By the connection of the bit line and the word line, the voltage can be applied to Units 3〇2,3〇4,3〇6,3〇8 '310 '312 '314 and 316 to stylize or erase units 3〇2,3〇4,3〇6 ' 30 8 '310, 312, 314 and 316. Stylized and erased units 3 〇 2, 3 〇 4, 306 ' 308 ' 310 ' 312, 314 and 316, which will be further described below with reference to Figures 4-11. Figure 4 is a diagram depicting an array of 〇〇3, in which an auxiliary charge is stored in each of the auxiliary charge memory cells in array 300. Referring to Figures 1, 2A, 2B, the transistor Each of 302, 304, 306, 308, 310, 312, 314, and 316 has an auxiliary charge terminal and a data terminal. 13〇3〇66 The auxiliary charge terminal contains - an electron, or an electron, an outline, , side, 4i 〇 412 ' 414 ' and 416. Usually many electrons can be used to generate a negatively charged region at the auxiliary charge side. The number of electrons will vary depending on the application, eg 'in some In the embodiment, relatively small cells require relatively few electrons. _ [(8) 38] In an embodiment, the auxiliary charge terminals of the - cells are connected to the auxiliary charge terminals of the wall cells. For example, the cell transfer and the cells are auxiliary. The charge terminals ^) 2 and 4 〇 4 are arranged to be connected to each other. In this example, the auxiliary of cell 3 〇 2 is at the 汲 terminal of cell 302, however, the auxiliary charge terminal of cell is at the source terminal of cell 304. The cell 3〇2 is connected to the source of the cell 3〇4 as described. The erase of the entire page/full block can be performed. This entire page/full block erase operation can, for example, erase the entire component, as described below with reference to Figure 6, or the entire page/full block erase operation can erase certain portions. A [_] FIG. 5 is a diagram depicting an exemplary method of a stylized array 300 that is 'in accordance with embodiments of the systems and methods described herein. The auxiliary charge memory cells in array 3 can be separately driven by applying different voltages to the exact word lines and bit lines. The auxiliary charge memory unit 3〇4 can be programmed, for example, by applying volts to U volts to I, and 5 volts. In one way, cell 3〇4 will have a source voltage of 〇volts and a bucker voltage of 5 volts. Referring to Figure 2A, electrons 5〇2 will flow from the source to the drain, and some of the electrons 502 will traverse the bottom oxide layer into the charge trapping layer at the data terminal of unit 3〇4. >...[0040] During the period of a stylized operation @, other bit lines may be allowed to be connected and 0 volts will be added to other word lines. Thus, for example, no current will flow into the transistors 302, 306, 308, 310, 312, 314, and 316' when the unit 304 is programmed. Therefore, other units in the array 3 are allowed to pass 1303066 - ', for example, 'unprogrammed, or forward-tilted stylized values. [0041] The above-mentioned examples, and the 6th-8th, (1).12_example, the voltages of each bit line not in the figure are considered to be - a stepless voltage, Vd. What can be solved is that the example in Figure 3_5, a unit and an extreme, can be connected to the source terminals of other units depending on the application of the particular array structure. In addition, more or less units depending on the size of a memory element can form the array architecture. [0042] Section 6 is an illustration of an exemplary method of bridging block 3, which is consistent with embodiments of the systems and methods described herein. The auxiliary charge memory cells in array f can be erased by the entire page or the entire block, that is, the bits of the '-subsequent' by applying different syndromes to the correct word line and bit line. The auxiliary charge memory cells 3 〇 2, 3 〇 4, 3 〇 6, 3 〇 8, 3 i 〇, 312 ' 314 and 316 can be erased one by one, for example, by using the method described in FIG. . - [0043] For example, as shown in FIG. 6, apply 〇 or 4.5 volts to the correct bit line, and apply -8 volts to the appropriate word line, as shown in Figure 6, each auxiliary charge memory cell 302, 304, 306, 308, 310, 312, 314 and • 316 'will have a source voltage of 0 volts, a 5 volt drain voltage, and a -8 volt gate voltage' and 2B The auxiliary charge memory elements of the figure are the same. The source and gate voltage differences of these cells are 8 volts, and the drain and gate voltage differences are 12.5 volts. In the large voltage difference between the drain and the gate, the hole flows from the pole to the gate. The hole is capable of compensating for electrons stored at the data side of the auxiliary charge memory unit. [0044] FIG. 7 is a diagram depicting an exemplary method of reading the array 3〇〇, consistent with embodiments of the systems and methods described herein. . By applying a specific voltage to the appropriate word line and bit line, individual cells can be read, similar to reference to -12-1303066 5-6 "The fine touch ice erasing tree theory" The source or the pole of the cell can be allowed to be shown in the figure, not yet [0045] for example, using the memory cell 3〇2. In one embodiment to read, the lion charge is 3 volts, the source is _@ The inter-electrode voltage of j 6 _ ^302 can be in this way, when the mono-' and can be 〇 volt., the poor end of Tian Zao το 302 is not stored, when the unit 3_ data is saved and stored, the current can The flowing current is generated, there is a 'viewing flow, or little electricity_moving. It can be understood that the amount of charge actually used to help the charge terminal will affect these electric enthalpy requirements. 'There is little or no current to indicate that a logic two current can indicate another logic state. In such a memory cell, two states can be stored in the parent memory cell. In addition, in -Shigu The same number of electrolysis bits can indicate the f stored in each memory. Logical levels. For example, different logic states can be stored by storing different charge levels at the lean end of cell 302. [0047] Figure 8 is a diagram depicting an exemplary array 800 of auxiliary charge memory cells. The embodiment is consistent with the embodiments of the systems and methods described herein. The array is similar to the array 300' except that the auxiliary charges on both sides of the bit line are staggered. As shown in Figures 9-11, stylized, erased And reading can be performed in a similar manner according to Figures 5, 6, and 7. [0048] Figure 9 is a diagram depicting an exemplary method of a stylized array 8A, and the system and system described herein Embodiments of the method are consistent. The auxiliary charge memory cells in the array (10) can be individually programmed by applying a specific voltage to the correct word line and bit line '. The auxiliary charge memory unit 902 can, For example, -13 - 13 1303066 'port is stylized by applying = volts to 1,5 volts to chaos, and 5 volts to the mouse. In this way, the auxiliary charge memory unit 902 will have - 0 volts. Source voltage '- 5 volts The drain voltage, and a gate voltage of 5 volts, are the same as the auxiliary charge memory component 1A of Figure 2A. As described with reference to Figure 2a, the electron 900 can begin to flow from the source to the pole, and some electrons 9(8) will be the tooth-oxide layer, entering the charge trapping layer of the data terminal of the cell. [0049] Other bit lines can be allowed to float, and the voltage of the stagnation will be applied to other word lines. Therefore, during the stylized unit 3〇4, there will be little or no current flow in its unit. In this way, other units remain unprogrammed or remain at the previous programmed value. 0050] Figure 1 is a diagram depicting an example method for performing a full page/full block erase, similar to the above Figure 6. Thus, the auxiliary charge memory cells 902 ' 904 ' 906 and 908 can, for example, as shown in FIG. 1 , by applying 〇 or 4.5 volts to the correct bit line, and as also shown in FIG. , is erased by applying _8 volts to the correct word line. Each of the auxiliary charge memory cells 902 ' 904 ' 906 and 908 will have a 〇 volt source voltage, a 4 5 volt drain voltage, and a -8 volt gate voltage, with the aid of FIG. 2B The electro-optic memory elements 100 are identical. The source and gate voltage difference is 8 volts and the gate and gate voltage difference is 12.5 volts. The large voltage difference between the drain and the gate will cause the hole to flow from the drain to the gate, where the hole can compensate for the electrons stored at the data terminals of the auxiliary charge memory cells 902, 904, 906 and 908. 11 is a diagram depicting an exemplary method of reading array 800 consistent with embodiments of the systems and methods described herein. Individual cells can be read by applying a specific voltage to the correct word line and bit line '. As shown in Figure 11, the cell and drain that are not being read will be allowed to float. -14- I3〇3〇66 ^ [0052] Therefore, with suction, chaos, and see can read, auxiliary charge, memory unit 9G2. The gate voltage of cell 9G2 can be 3 volts, the source voltage can be 1.6 volts, and the drain voltage can be volts. In this way, when the negative terminal of unit 902 does not store charge, current can flow. When the data terminal of the component stores charge, no current flows, or little current flows. It can be understood that the source, drain, and gate voltages that are actually used to read a particular cell will vary depending on the application, for example, the amount of charge stored at the auxiliary charge side of the cell. The specific embodiments of the present invention have been described above, and it is understood that the described embodiments are merely illustrative examples. Therefore, the invention should not be limited to the described embodiments. Of course, in the scope of the present month described herein, only month b is limited by the subsequent claims and the above description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0011] For a more complete understanding of the present invention, and its advantages, the following description is accompanied by drawings for reference, wherein: [0012] FIG. 1 is a diagram illustrating an exemplary auxiliary charge memory consistent with one embodiment. [0013] FIG. 2A is a diagram depicting a method of stylizing an auxiliary charge memory cell of a first figure, consistent with an embodiment; [0014] FIG. 2B is a first diagram illustrating an example An illustration of an erase method of an auxiliary charge memory cell is consistent with this embodiment; [0015] FIG. 3 is a diagram depicting an array of exemplary auxiliary charge memory cells; [0016] FIG. 4 depicts a In each auxiliary charge memory unit - 15 -
1303066 儲存有辅助電荷的第3圖的陣列圖示； [0017] 第5圖是描述程式化第3圖的陣列的一個範例方法 ，與一個實施例一致，的圖示； [0018] 第6圖是描述一個整頁或整區塊抹除第3圖的陣列 的一個範例方法，與一個實施例一致，的圖示； [0019] 第7圖是描述第3圖的陣列的一個整頁或整區塊抹 除的範例，與一個實施例一致，的圖示； [0019] 第7圖是描述讀取第3圖的陣列的一個範例方法， 與一個實施例一致，的圖示； [0020] 第8圖是描述輔助電荷記憶體單元的一個範例陣列 的圖示，與在此描述的系統和方法的實施例一致； [0021] 第9圖是描述程式化第8圖的陣列的一個範例方去 ，與一個實施例一致，的圖示； [0022] 第10圖是描述執行一個整區塊或整頁抹除第8圖的 陣列的一個範例方法，與一個實施例一致，的圖示；以及 [0023] 第11圖是描述讀取第8圖的陣列的一個範例方法， 與一個實施例一致的圖示。 -16- 1303066 【主要元件符號說明】 100 :輔助電荷記憶體元件 102 :基底 104、106 : n+區域 一 108: ΟΝΟ 層 110 :氮化物層 112 :辅助電荷端 • 114 :電荷 116 :資料端 118 :陡峭電場區域 130、132 ··氧化物層 ‘ 200、402、404、406、408、410、412、414、416、502、900 - :電子 202 :輔助電荷下方通道的區域 250、602、604、606、608、610、612、614、616、1000、1002 籲 、1004、1006 :電洞 300、800 :輔助電荷記憶體陣列 302、304、306、308、310、312、314、316、902、904、906 、908 :辅助電荷記憶體單元 318 :連接點 WL:字元線 BL:位元線 -17-1303066 Array diagram of FIG. 3 storing auxiliary charge; [0017] FIG. 5 is a diagram illustrating an exemplary method of stylizing the array of FIG. 3, consistent with an embodiment; [0018] FIG. Is an exemplary method for describing an entire page or an entire block of the array of FIG. 3, consistent with an embodiment; [0019] Figure 7 is a full page or whole of the array depicting Figure 3. An example of block erasing, consistent with an embodiment; [0019] FIG. 7 is a diagram depicting an exemplary method of reading the array of FIG. 3, consistent with an embodiment; [0020] Figure 8 is a diagram depicting an exemplary array of auxiliary charge memory cells consistent with embodiments of the systems and methods described herein; [0021] Figure 9 is a diagram depicting an exemplary embodiment of the array of Figure 8 BRIEF DESCRIPTION OF THE DRAWINGS [0022] FIG. 10 is a diagram depicting an exemplary method of performing an entire block or a full page erase of the array of FIG. 8, consistent with an embodiment; And [0023] FIG. 11 is an example of describing the array of reading FIG. Method, an illustration consistent with one embodiment. -16- 1303066 [Description of main component symbols] 100: Auxiliary charge memory component 102: Substrate 104, 106: n+ region-108: ΟΝΟ Layer 110: nitride layer 112: auxiliary charge terminal • 114: charge 116: data terminal 118 : steep electric field regions 130, 132 · oxide layers '200, 402, 404, 406, 408, 410, 412, 414, 416, 502, 900 - : electrons 202: regions 250, 602, 604 of auxiliary charge lower channels , 606, 608, 610, 612, 614, 616, 1000, 1002, 1004, 1006: holes 300, 800: auxiliary charge memory arrays 302, 304, 306, 308, 310, 312, 314, 316, 902 , 904, 906, 908: auxiliary charge memory unit 318: connection point WL: word line BL: bit line -17-