TWI301657B - Flip-chip semiconductor device and method for fabricating the same - Google Patents

Flip-chip semiconductor device and method for fabricating the same Download PDF

Info

Publication number
TWI301657B
TWI301657B TW095103437A TW95103437A TWI301657B TW I301657 B TWI301657 B TW I301657B TW 095103437 A TW095103437 A TW 095103437A TW 95103437 A TW95103437 A TW 95103437A TW I301657 B TWI301657 B TW I301657B
Authority
TW
Taiwan
Prior art keywords
flip
chip
mod mod
semiconductor device
wafer
Prior art date
Application number
TW095103437A
Other languages
English (en)
Other versions
TW200729425A (en
Inventor
Yih Jenn Jiang
Han Ping Pu
Cheng Hsu Hsiao
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW095103437A priority Critical patent/TWI301657B/zh
Priority to US11/648,048 priority patent/US20070178627A1/en
Publication of TW200729425A publication Critical patent/TW200729425A/zh
Application granted granted Critical
Publication of TWI301657B publication Critical patent/TWI301657B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909Post-treatment of the layer connector or bonding area
    • H01L2224/83951Forming additional members, e.g. for reinforcing, fillet sealant
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

1301657 九、發明說明: • 【發明所屬之技術領域】 本發明係有關於一種覆晶式半導體裝置及其製法,尤 指一種用於防止覆晶式半導體晶片脫層之半導體裝置及其 製法。 【先前技術】 : 覆晶式(FliP_ChiP)半導體封裝件係為一種利用覆晶方 •式進行電性連接的封裝結構,其係藉由多數導電凸塊 Φ (Bumps)而將至少一晶片的作用表面(Acuve surface)電性 連接至基板(Substrate)之表面上,並於該基板另一表面上 植设多數可作為輸入/輸出(1/⑺端之銲球(s〇lder Ball),以 供該半導體晶片電性連接至外部裝置;此設計不但可大幅 縮減封裝件體積,以使半導體晶片與基板之比例更趨接 近,同犄,亦減去習知銲線(Wire)設計,而可降低阻抗提 幵電性,因此已成為下一世代晶片與電子元件的主流封裝 φ技術。 请麥閱第1A及1B圖,係為習知覆晶式半導體封襄件 之平面及剖面示意圖,對於此類封裝件而言,其製程中必 需於覆晶式半導體晶片10與基板u間填充一覆晶底部填 膠材料(UnderfilDU (通常為一熱固性樹脂),以令該覆晶 f部填膠材料12包覆於各導電凸塊13間,而能增強該些 導電凸塊13強度,並定位以避免變形;同時,復可支撐該 覆晶式半導體晶片1〇重量。例如美國專利第號 案與第6,074,895號案等先前技術,均已揭示此一覆晶底 17272 5 1301657 部填膠技術。 然而’因覆晶底部埴膠姑 ㈣科12表面張力作用之關係, 曰^日日底㈣勝材料12填充後,在對應於覆晶式半導體 角端呈現最小量的附著保護,同時,由於該覆晶式 + ¥體甜片10與基板n間之材料熱膨脹係數(cte)差異 ° α此b日片封衣之熱循環過程中產生之熱應力及熱變
=與距離成正比關係,d(變形量η(材料熱膨服係 上)L(與材料變形量為〇之距離)*△((溫度變化幻。亦即 ^覆晶式半導體晶片1G之邊緣角端,由於其與晶片中心處 (受形量為〇處)距離最遠,因此將受到極大熱應力及熱變 形,但此刻卻無法提供足量之覆晶底部填膠材料η保護, =使填充於周緣之覆晶底部填膠材料12出現脫層現象(如 第A圖之s所示)’影響覆晶底部填膠之效果,更嚴重者, 更可能造成脫層之擴散,進而影響導電凸塊的電性。 ;為減少因熱膨脹係數(CTE)不同所產生之熱應力問 題,一般業界之作法係使用低彈性模數(m〇dulus)2覆晶底 4填膠材料來吸收熱應力,但相對地,低彈性模數之覆晶 底部填膠材料並無法提供覆晶式半導體晶狀導電凸塊足 夠支撐強度;相對地,如採用高彈性模數之覆晶底部填膠 材〃斗進行覆晶底部填膠’雖可提供導電凸塊足夠支撐強 度,然卻易導致覆晶式半導體晶片受熱應力作用而發生脫 層問題;是以對應不同晶片大小尺寸’以及不同類型之晶 片與基板接合時,即需花費大量之時間、精力及試驗去尋 找適宜之覆晶底部填膠材料,造成製程時間及費用之增加。
6 17272 1301657 因此,如何開發一種覆晶式半導體裝置及其製法 有效避免晶片角端發生脫層問題,同時提供覆晶式 晶片之導電凸塊有效保護,確已為此相關研發領^ 待解之課題。 、刀 【發明内容】 因此,為解決前述及其他問題,本發明之主要 在提供-種覆晶式半導體裝置及其製法,以防 導體晶片脫層。 1^式+ 本發明之再—目的即在提供—種覆晶式半導體裝置 及其製法’以有效支撐與保護覆晶式半導體晶片 塊。 $电凸 本發明之另一目的即在描极 ^ λ 日7 f隹杈供一種覆晶式半導體裝置 及其製法,俾可提升覆晶式.半導 膠量。 、干冷體曰曰片角端之覆晶底部填 為達前述及其他目的,本發明揭露—種覆 ;置之製法’係包括:在基板之晶片接置區角隅佈設:體 復晶底部填膠材料;將覆晶式半導體晶片透過複數導 塊接置並電性連接於該晶片接置區上,且使該第一覆晶底 部填膠材料夾置於該覆晶式半導體晶片角端與基㈣,·以 及於錢晶式半導體晶片與基板間之間隙填充第二覆晶底 •真膠材料。該第-覆晶底部填膠材料之彈性模數係小於 该第二覆晶底部填膠材料之彈性模數。 本發明亦揭露-種覆晶式半導體裳置,係包括:一基 板’該基板上設有至少一可供容置半導體晶片之晶片接置 7 17272 1301657 區,至少一覆晶式半導體晶片,係透過複數 並電性連接於該晶片接置巴上灵數W凸塊接置 “ 弟一覆晶底部填膠材料, 盘:於該晶片接置區角隅’且夾置於該覆晶式半導體 =板間;以及第二覆晶底部填膠材料,係充佈於該覆曰 ^ , 皁°亥弟一覆晶底部填膠材料 之,柄數係小於該第二覆晶底部填膠材料之彈性模數^ 因此,本發明之覆晶式半導體裝置 係r基板上對應晶片接置區之角隅佈設低二之第 塊材料,再將覆晶式半導體晶片透過導電凸 鬼接置亚%性連接至該基板之晶片接置區 晶底部填膠材料包覆該覆曰 便。亥弟一覆 該覆曰mi +導體晶片之角端,接著於 第一 ::乂晶片與基板間之間隙令填充高彈性模數之 弟::=彻材料,以供保護該導電凸 片,如此即可藉由該低彈性 佈兮於兮变日』 供歎之弟一覆晶底部填膠材料 角:::;“曰式半導體晶片之角端下方,以輸 、由收熱應力而避免造成晶片角端之脫I,同時 料:::數之第二覆晶底部填璆材料佈簡
牛¥體晶片下緣,且奋佑 议日日A 導電凸塊及?截4举、;各蛉電凸塊間,藉以有效保護· A承载该復晶式半導體晶片。 再者由於本發明係對應於覆晶式半導鄉曰 及其餘區域下方分別填充低、高模=端 填膠材料,如此即可對 =拉數之復曰曰底部 免脫層之伴噌 心又日日工冷脰晶片之角端提供避 覆;式半導體晶片下方導電凸塊 、 除白知哥找單一覆晶底部填膠材料時 17272 8 1301657 ^^耗費日^"間及成本問題,以及無法同時提供晶片角 立而及·笔凸塊保護之困境。 【實施方式】 、下係藉由4寸疋之具體實施例配合附圖進一步說明 本發明之特點與功效。 請參閱第2A至2E圖,係為本發明之體 置及其製法。 、千^體衣 ® 2A圖所不’提供_基板2卜該基板上係設有 至>、一可供容置半導體晶片之晶片接置區21〇(如虛線所 :)材St板之晶片接置區21 〇角隅佈設第-覆晶底部填 .材料22 1。該基板2 1之s Η拉r~、 0/1 槪之日日片接置區210内設有複數銲墊 一二供後續接置並電性連接有覆晶式半導體晶片。另該 =一後晶底部填膠材料22!係為低彈性模數(M〇dui叫材 貝’其玻璃轉移溫度(Tg)係例如小於80〇c。 +如弟2BH所不,將覆晶式半導體晶片2㈣過複數導 =凸塊接置並經迴銲㈣GW)以電性連接於該基板Η之晶 之該銲墊24上,並使該第一覆晶底部填膠材 们2!夾置於該覆晶式半導體晶片2〇角端與基板η間。 復請配合㈣2C®,係為第⑼圖中沿麻線2咖 =剖面示意圖,該覆晶式半導體晶片2 〇係藉由複數導電凸 ,2 J而朴覆晶製程,以接置且電性連接至該基板2】之 銲墊24上。另先前塗佈於該晶片接置區加角隅之第 晶底部填膠材料221,係夾置於該覆晶式半導體晶片加角 端與基板21間,以增加該覆晶式半導體晶片2〇角端之覆 17272 9 1301657 晶底部填移量,且該第一覆晶底部填膠材料22i係為低彈 性权數材質’俾可吸收該覆晶式半導體晶片2g之角端輕 =21因熱膨脹係數(CTE)差異所產生之熱應力,從而避免 發生脫層問題。 如第2D圖所示,於該覆晶式半導體晶片2〇與基板21 曰之間㈣填充第二覆晶底部填膠材料奶。該第二覆晶底 ^填膠材料22之彈性模數係大於該第一覆晶底部填膠材 料221之彈性模數。兮楚-舜 、 μ弟一復日日底部填膠材料222係為高 ^ (Modulus)# f , 復請配合參閱:2E圖,係為第扣圖中沿剖面線2e_2e 意圖’該第二覆晶底部填膠材料奶係形成於談 半導晶片20下方,並得充佈於該導電凸塊23間, 二覆晶底部填膠材料222係為高彈性模數(MckMus) t二T保護該導電凸塊23,並得有效支續 丨式+導體晶片20。 2過刚述衣私’本發明亦揭露一種覆晶式半導體裝 一,21 ’該基板21上設有至少-可供 T片2二:片之曰曰片接置區210 ;至少-覆晶式半導體 曰曰=〇,係透過複數導電凸塊23接置並電 片接置區210上;第一覆曰念加成” 晶片接置=填膠材料221,係設於該 與基板M an 覆晶式半導體晶片20 覆晶式半導體晶片2。:;;:=^ 基板21間之間隙。讓第一覆晶底 17272 10 1301657 部填膠材料221《彈性模數係小於該第二覆 料222之彈性模數。 因此,本發明之覆晶式半導體裝置及其製法中,主要 係先於基板上對應晶片接置區之角隅佈設低彈性模數之第 -覆晶底部填膠材料,再將覆晶式半導體晶片透過導電凸 塊接置並電性連接至該基板之晶片接置區,且使該第一 晶底部填膠材料包覆該覆晶式半導體晶片之角端,接著於 覆^半導體晶片與基板間之間隙中填充高彈性模數之 弟了復晶底部填膠材料,以供保護該導電凸塊並承載晶 :,如此即可藉由該低彈性模數之第一覆晶底部填膠材料 2砂該覆晶式半導體晶片之角端下方,以保護該晶片之 二’亚可吸收熱應力而避免造成晶以端之脫層,同時 :=祕模數之第:覆晶底部填膠材料佈設於該覆晶式 導Ϊ =片下緣’且充佈於各導電凸塊間,籍以有效保護 ¥电凸塊及承載該覆晶式半導體晶片。 | 再者,、由於本發明係對應於覆晶式半導體晶片之角端 埴膠2域下方分別填充低、高不同彈性模數之覆晶底部 免脫保t此即可對應覆晶式半導體晶片之角端提供避 脫g之保護,同時對應覆晶式半導體晶片下方導電凸塊 =支承保護’俾免除f知尋找單—覆晶底部填膠材料時 ^f之耗費相及成本問題,以及無法㈣提供晶片角 而及導電凸塊保護之困境 =上所述僅為本發明之較佳實施方式而已,並非用以 ^發明之範圍,亦即,本發明事實上仍可做其他改變, 17272 11 1301657 因此,舉凡熟習該項技術者在未脫離本發明所揭示之精神 人技術心想下所元成之一切等效修飾或改變,仍應由後述 之申請專利範圍所涵蓋。 【圖式簡單說明】 第1A圖係習知覆晶式半導體封裝件之平面示意圖; 第1B圖係習知覆晶式半導體封裝件之剖面示 以及 ^ ,第2A至2E圖係為本發明之半導體裴置及其製法之示 思圖。 10 覆晶式半導體晶片 11 基板 12 復晶底部填膠材料 13 導電凸塊 20 覆晶式半導體晶片 21 基板 210 晶片接置區 221 第一覆晶底部填膠材料 222 弟一覆晶底部填膠材料 23 導電凸塊 24 銲墊 S 脫層現象 【主要元件符號說明】 17272 12

Claims (1)

  1. 第95103437號專利申請案 (97年5月5曰) ? .· -Γ ;嫁,丄匕 1301657 十、申請專利範圍·· 1 --------------、士_. --------# •一種覆晶式半導體裝置之製法,係包括·· 在基板之晶片接置區角隅佈 材料; ,又昂覆晶底部填膠 將覆晶式半導體晶片透過複數邋 性連接於令曰片接署F μ 义數Η凸塊接置並電 料决^ 使該第—覆晶底部填膠材 ;該覆晶式半導體晶片角端與基板間,·以及 於該覆晶式半導體晶片與基板間之間隙殖充第二 覆晶底部填膠材料。 2·如申請專利範圍第1項 貝之復日日式丰導體裝置之製法,其 ,4 -覆晶底部填膠材敎彈性模數係小於該第二 覆晶底部填膠材料之彈性模數。 3.如申::利範圍第!項之覆晶式半導體裝置之製法,其 4丰5導^^之曰曰片接置區内設有複數鲜塾,以供該覆晶 式半導體晶片藉由i_、, 电凸塊接置並經迴鋅而電性連 於該銲墊。 4•如申^專㈣圍第β之覆晶式半導體裝置之製法,其 中亥弟一覆晶底部填膠材料係為低彈性模數(Modulus) 材質。 5.如申^專:範圍第^之覆晶式半導體裝置之製法,其 弟。一覆晶底部填膠材料之玻璃轉移溫度(Μ係小 6·如申;^利範圍第1項之覆晶式半導體裝置之製法,其 中/第设日日底部填膠材料係為高彈性模數(M〇dulus) 19272(修正本) 13 第95103437號專利申請案
    1301657 材質。 7.如申請專利範圍第1項之覆晶式半導體裝置之製法,其 中,該第二覆晶底部填膠材料之玻璃轉移溫度(Tg)係大 於 80〇C。 8.如申請專利範圍第1項之覆晶式半導體裝置之製法,其 , 中,該第二覆晶底部填膠材料係包覆該導電凸塊。 1 9. 一種覆晶式半導體裝置,係包括: 一基板’該基板上設有至少一可供容置半導體晶片 之晶片接置區, 至少一覆晶式半導體晶片,係透過複數導電凸塊接 置並電性連接於該晶片接置區上; 第一覆晶底部填膠材料,係設於該晶片接置區角隅 及該覆晶式半導體晶片之角端下方’且夹置於該覆晶式 半導體晶片與基板間,以及 第二覆晶底部填膠材料,係充佈於該覆晶式半導體 晶片與基板間之間隙及該覆晶式丰導體晶片下緣。 10. 如申請專利範圍第9項之覆晶式半導體裝置,其中,該 第一覆晶底部填膠材料之彈性模數係小於該第二覆晶 底部填膠材料之彈性模數。 11. 如申請專利範圍第9項之覆晶式半導體裝置,其中,該 基板之晶片接置區内設有複數銲墊,以供該覆晶式半導; 體晶片藉由導電凸塊接置並經迴銲而電性連接於該銲 墊。 12.如申請專利範圍第9項之覆晶式半導體裝置,其中,該 14 19272(修正本) §5103437聰專利申:請案 1301657 外广——一…— Ϊ —覆晶底部填膠材料係為低彈性模數(Moduius)材 質。 ^二=T利範圍第9項之覆晶式半導體裝置,其中,該 ' 设日日底σ卩填膠材料之玻璃轉移溫度(Tg)係小於80 C。 1 »申:專利範圍第9項之覆晶式半導體裝置,其中,該 ^後日日底"卩填膠材料係為高彈性模數(Modulus)材 - 質。 鲁冰申明專利耗圍第9項之覆晶式半導體裝置,其中,該 弟-復曰曰底部填膠材料之玻璃轉移溫度㈤係大於 C。 申請專利範圍第9項之覆晶式半導體裝置,其中,該 m底部填膠材料係包覆該導電凸塊。
    19272(修正本) 15
TW095103437A 2006-01-27 2006-01-27 Flip-chip semiconductor device and method for fabricating the same TWI301657B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW095103437A TWI301657B (en) 2006-01-27 2006-01-27 Flip-chip semiconductor device and method for fabricating the same
US11/648,048 US20070178627A1 (en) 2006-01-27 2006-12-28 Flip-chip semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095103437A TWI301657B (en) 2006-01-27 2006-01-27 Flip-chip semiconductor device and method for fabricating the same

Publications (2)

Publication Number Publication Date
TW200729425A TW200729425A (en) 2007-08-01
TWI301657B true TWI301657B (en) 2008-10-01

Family

ID=38322598

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095103437A TWI301657B (en) 2006-01-27 2006-01-27 Flip-chip semiconductor device and method for fabricating the same

Country Status (2)

Country Link
US (1) US20070178627A1 (zh)
TW (1) TWI301657B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426780A (zh) * 2012-05-14 2013-12-04 万国半导体(开曼)股份有限公司 焊球阵列用作高度垫块及焊料固定物

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1914798A3 (en) * 2006-10-18 2009-07-29 Panasonic Corporation Semiconductor Mounting Substrate and Method for Manufacturing the Same
US7745264B2 (en) * 2007-09-04 2010-06-29 Advanced Micro Devices, Inc. Semiconductor chip with stratified underfill
US8222739B2 (en) * 2009-12-19 2012-07-17 International Business Machines Corporation System to improve coreless package connections
US8637992B2 (en) * 2011-11-30 2014-01-28 Invensas Corporation Flip chip package for DRAM with two underfill materials
KR101814022B1 (ko) * 2012-01-27 2018-01-04 삼성전자주식회사 반도체 패키지
US8796133B2 (en) 2012-07-20 2014-08-05 International Business Machines Corporation Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections
US9312193B2 (en) 2012-11-09 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Stress relief structures in package assemblies
JP6182928B2 (ja) * 2013-03-27 2017-08-23 セイコーエプソン株式会社 半導体装置
US9721906B2 (en) * 2015-08-31 2017-08-01 Intel Corporation Electronic package with corner supports
US12087733B2 (en) * 2021-05-13 2024-09-10 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with multiple types of underfill and method forming the same
US11978729B2 (en) * 2021-07-08 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package having warpage control and method of forming the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5056215A (en) * 1990-12-10 1991-10-15 Delco Electronics Corporation Method of providing standoff pillars
US6262513B1 (en) * 1995-06-30 2001-07-17 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
US6074895A (en) * 1997-09-23 2000-06-13 International Business Machines Corporation Method of forming a flip chip assembly
US6225704B1 (en) * 1999-02-12 2001-05-01 Shin-Etsu Chemical Co., Ltd. Flip-chip type semiconductor device
US6461881B1 (en) * 2000-06-08 2002-10-08 Micron Technology, Inc. Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures
US6624216B2 (en) * 2002-01-31 2003-09-23 National Starch And Chemical Investment Holding Corporation No-flow underfill encapsulant
US7224071B2 (en) * 2003-05-22 2007-05-29 Texas Instruments Incorporated System and method to increase die stand-off height
US7148560B2 (en) * 2005-01-25 2006-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. IC chip package structure and underfill process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426780A (zh) * 2012-05-14 2013-12-04 万国半导体(开曼)股份有限公司 焊球阵列用作高度垫块及焊料固定物

Also Published As

Publication number Publication date
TW200729425A (en) 2007-08-01
US20070178627A1 (en) 2007-08-02

Similar Documents

Publication Publication Date Title
TWI301657B (en) Flip-chip semiconductor device and method for fabricating the same
TWI296151B (en) Methods and apparatuses for providing stacked-die devices
CN101226920B (zh) 使用具有降低布线断开的布线结构的布线衬底的半导体器件
US9012269B2 (en) Reducing warpage for fan-out wafer level packaging
TWI574355B (zh) 半導體封裝件及其製法
US9698072B2 (en) Low-stress dual underfill packaging
TWI757587B (zh) 半導體裝置
US20120252169A1 (en) Redistributed chip packaging with thermal contact to device backside
TW201232750A (en) Semiconductor device and method of fabricating the same
US7049695B1 (en) Method and device for heat dissipation in semiconductor modules
US10700030B2 (en) Semiconductor package having varying conductive pad sizes
TWI300614B (en) Flip-chip semiconductor package and chip carrier thereof
TWI228806B (en) Flip chip package
TW200849507A (en) CMOS image sensor chip scale package with die receiving through-hole and method of the same
TW200935574A (en) Inter-connecting structure for semiconductor device package and method of the same
TWI249796B (en) Semiconductor device having flip chip package
TW200824056A (en) Circuit board structure having embedded semiconductor chip and fabrication method thereof
TW200534453A (en) Chip package structure and process for fabricating the same
TW201207962A (en) Chip-sized package and fabrication method thereof
TW200837915A (en) Semiconductor device package
TWI734651B (zh) 電子封裝件及其製法
TW201117687A (en) Electronic component embedded PCB
US20240170435A1 (en) Anisotropic conductive film with carbon-based conductive regions and related semiconductor device assemblies and methods
US20030146520A1 (en) Flip-chip package with a heat spreader
TW200905827A (en) Semiconductor apparatus, and method of manufacturing semiconductor apparatus