TWI300524B - System-on-a-chip and test/debug method thereof - Google Patents

Description

1300524 IX. Description of the Invention: [Technical Field] The present invention is a system single chip and a test and/or debug method applied thereto, especially a system single chip with a built-in test/debug circuit and A system single wafer test method that performs memory direct access testing and/or debugging. [Prior Art] System single-chip (System_on-a_Cliip, referred to as s〇C) or System-Level Integration (SLI) chips have become an important product design trend with current technology. The main design concept of this type of wafer basin is to miniaturize and modularize the circuits in the wafer, by integrating all the methods in the early integrated circuit (1C). The products produced are lighter and more portable, and can meet the individual needs of today's electronic products. However, due to the complexity of the circuit system and the need for a long implementation time, it may affect the further development of its integrated wafer or SiS integrated wafer; for example, 'general design company from product design, verification (ver It takes at least 8 to 12 months for a cati〇n) to produce a photomask plot (such as GDSII) and then to a fab. In other words, a system single-chip or system-integrated wafer may be developed from the initial stage to the possible The profit may be more than 6 1300,524 m ° a year. In the case of F Lun, there are many problems in integrating many different circuits into one-person integrated circuits. For example, ··· Noise interference may occur between the speed digit circuit and the analog circuit. On the other eve, each of the different electric powers of the Insects (Intellectua I 卩 时 ies, referred to as milk) will produce complex power management lines and power waste, etc.?,, and: If you want to go further Considering the integration and verification of embedded memory, it may take about half a year for IC Wei to design, manufacture and complete the product. Therefore, it is necessary to speed up the product (4) trial, debug and verification. The speed of brain products has become one of the improvement goals of various 1C manufacturers. Please refer to the first figure, which is a functional block diagram of a conventional system single chip (SoC). As shown, a central processing unit 1 , an embedded memory 11 and a memory controller 13 are integrated into a system single chip i ' and the central processing unit 10 and the memory controller 13 are The internal memory unit 12 can be connected to the embedded memory n by an internal bus bar 12. Therefore, the central processing unit 1 performs data reading on the embedded memory U through the control of the memory controller 13. Internal transfer of fetch and write. Under the 5 recalculation structure, the immersive memory 11 in the single chip 1 of the system does not have an additional external pin, so that the circuit other than the single chip i of the system can be embedded in the embedded memory. The body U accesses the data, so it is difficult to directly read and write the embedded memory π from the outside, so that the debug program and software for the product design and manufacturing process are performed. Development has a considerable degree of inconvenience. In addition, the general test machine can not provide the current system single chip 1300524

j's fast test signal and a large number of test patterns (Test p敝 (4) storage signal, so the domain to cope with this demand, you need to use high-speed, ^ Li is a high-priced Lai instrument to work, but if you are using When the test instrument of lower price is tested, the result on the At-Speed Test may not be satisfied. In addition, due to the tight structural characteristics of the memory, the system single chip is easily subject to The unfavorable lack of factors affects its performance. Furthermore, the operation mode of the @Memory array is essentially analogous, so its fault tolerance is relatively small. These design features make the array easier. It is influential to the intricate manufacturing defects (4). The tight memory matrix 封J is the state of the adjacent unit, which may cause misoperation in the presence of defects' and some defects may only be specific. Data patterns are exposed. In addition, many of these defect types are time-correlated and therefore only found at normal operating frequencies. The problem of a built-in self-test (built_in_sdf_test, BIST for short) technique is used to thoroughly test embedded memory with a reasonable circuit area. The test involves writing test patterns. In the memory and then read it back to see if the test pattern produced by it is in line with expectations, so we can save a lot of test time, and make the general test instrument can also be used for immediacy test (At -Speed Test) Please refer to the second figure, which is a functional block diagram of another conventional system with self-test function. The design structure shown in this figure is based on a built-in self-test controller! ^〇血〇11 Shen)21, a pattern of production 8 1300524

A Pattern Generator 22 and a Reaction Analyzer (for example, Analyzer) 23 test a circuit to be tested 20, and the built-in self-test controller 21 is input by an external Bist-on signal. After controlling the pattern generator 22 to generate the test pattern and the basic control signal, the BIST mode is entered; a multiplexer 24 is used to select the test pattern generated by the pattern 2, and after a specific time. The turn-out signal is sent to the reaction analyzer 23 for analysis. Finally, the section built-in self-test controller 21 sends a Bist_d〇ne signal to = the test program has been completed. According to the Pass/Fail round-out message, we can judge that the standby circuit 2G is b: normal or cannot be thief. 4€ / However, the above built-in self-test τ) technology still limits the embedded memory in the single chip through the external circuit to achieve the purpose of debugging and verification; in order to solve this problem, take some daily on-chip There are additional pins that are used to operate. Therefore, through these extra two: = yes, the greedy/address pins can be used for the embedded memory. These extra pins are inevitable. The ground will save two's but the volume and production cost, and how to make the external circuit can be the main purpose of the development of the case. [Summary of the Invention] 9 1300524 - external 呷 二 2:: 吉 system single-chip embedded memory can be used without the need to add additional surface 'supplied and debugged by the 提供 ^ 7 provides a system The test and debugging method of the chip can be used to test the lions of the _ _ test and debug, without special design of the implementation of the operation of the pin. Only, spoon ^ ^ 帛 built-in test / Wrong circuit - system single crystal 匕 3 Memory controller--JTAG controller, which is connected to the external device to generate a signal connection for receiving ^=卩衣在在测5式/Debug mode-test/debug two A source should send a control signal to test/debug the signal; and a register device is connected to the embedded clock to store the access contained in the test/debug signal. For the embedded memory, 'Ayne should control the serial number to make the information related to the information transfer between the embedded memory and the external device through the access test. According to the above concept' The scratchpad device includes a memory access data register that can be connected to the memory signal, and a jTAG accessible shift register that can be connected to the η海 JTAG control signal. And the memory access data register and the JTAG accessible shift register are connected to each other. According to the above concept, the system single chip further comprises a built-in self-test circuit for Perform a built-in self-test mode, the built-in self-test circuit The utility model comprises a built-in self-test controller; a first multiplexer 1300524 is connected with the temporary access signal of the memory access data, and is selected according to the control signal of the self-test circuit; The built-in self-test controller sends a memory access data register to output the second power = the output signal or the embedded memory; - the central processing d and the force: _ sent to the And the first multiplexer and the middle=one eve, the JTAG controller sends out the -= postal money, according to the signal output by the output or the central processing two multiplexer is transferred to the embedded In the memory, according to the above-mentioned counties, the towel (5) in addition to the slogan 'includes in the - reading action to be from that age; = the address information and information writing action of the memory In order to write to the embedding according to the above concept, wherein the outer and the accessing phase f are centered, and subsequently read through the temporary storage $: human escaping The ^ - test mode is working normally. The disambiguated memory is analyzed in the mode via #卜5H external device reads the H sub = in the test memory and the access test 埠 from the embedded material, or in one or two to determine whether the data is an error itch to write data to The embedded _3 memory ^ = the access test of the present invention - the second type of "two::: 峨 ^ ^ method includes the following step xian. ^ early ^ (four) method, the shoulder 攸 an external device Through the 11 1300 524 糸 早 早 早 经由 一 一 一 一 一 一 一 一 一 一 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Qualification execution - data writing Γ:: Γ , , , 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 : : : : : : : : : : : : : From the embedded memory;; from the heart / two out to the external device; and using the external device to analyze the data read in the t s & f system: 曰, ν 方法 method includes the following steps: from an external device via the 糸, first 0 days in the film - TAG controller access test 埠, will: out control (four) 'the test signal system contains There is a site address = the address information contained in the _ test signal ± is stored in the temporary crying parameter = according to the address information stored in the register device and corresponding to the 't domain' The embedded memory in the system single chip performs a purchase operation, and outputs the data read from the input memory to the temporary memory device via the access test and the temporary memory device. And using the external device to analyze the data read from the embedded memory. In the step of outputting the data, the embedded memory is stored in the temporary storage of the memory, and then the data is accessed from the memory. Transfer to the TTAG access shift register of the temporary H device, sub] 12 丄 300524 = output the data from the ITAG accessible shift register to the external take: Γ:Γ The system is a system single-chip memory directly stored == method, the method comprises the following steps: from an external device via the number: 1 piece 2: _ controller access test 埠, will - error ^ : In the SiS early chip, 'the debug signal system contains the address ^ and the younger data; the debugger should respond to the signal from the controller ^ ^ times = the address contained on the debug signal Information and the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The second of the second 42L, wherein the first-sub-substance is received from the external device, and the _JTAG accessible shift temporary storage in the temporary register device

Move to the temporary: ==_ The JTAG can access the shift register, and the data is transferred from the memory access data register to the desired J. A multiplexer is used in the system single chip. The time for the embedded line in the user ==:=埠 is debugged and the soft state is reduced to the wafer. :::r 13 1300524 Expressiveness::=== [Embodiment] Referring to the first figure, the invention is developed for improving the conventional technology.

A functional block diagram of a preferred embodiment of 糸, 早早晶(10)GC)3. The single-chip 3-system package-the towel central processing unit 30, the embedded body 3b-built-in self-test circuit 33, the built-in self-test controller 33, a first multiplexer 34 And a coffee _ w & such as n

Gr〇UP 'Joint Test Action Group' controller 35, and integrates these components in a conventional manner, and the towel system of the towel processing unit 3() includes a module for performing the stagnation mode System clock control 3〇1 and a memory access control 302 function. And "JTAG" refers to the organization of JTAG (J〇intTest

Developed by Action Group, the official name is the IEEE 11491 chip design specification, which aims to establish a basic wafer test architecture by developing instruction sets and communication protocols. The JTAG controller 35 mainly includes an Access Test Port (TAP) 350 and a clock controller 351, wherein "TAP" refers to a test interface specified by the JTAG organization, which is tested by data input ( Test Data In (TDI), Data Output Test (TDO), Test Clock (TCK), Test Mode Select (TMS) and Reset Test (TestReset, referred to as Ding 1181〇 and other signals are formed, and for the sake of brevity, in the third figure, only the TDI signal pin mentioned in the 14 1300524 invention and the TD〇 signal are shown. In addition, the deposit The function of the test module 350 is used to interpret its JTAG instruction, and the clock controller 35! is used to provide the clock to other components for the operation. The present invention uses the existing jtag. In addition to the controller's technology and hardware architecture, a memory access data register 36 is added to the system single chip.

Test Action Group, Joint Test Action Group) Accessible Shift Register and a second multiplexer 38 for performing test and debug operations on the embedded memory. In the design of the device, there is no need to add additional pins; in the memory access (4) register, the % ^ contains the necessary control signals, address information and data information of the memory. The access shift register 37 has substantially the same spatial size as the memory access data register 36, and is stored or unloaded in the memory access data register. The method of knowing the test and debugging of the system single chip 3 in the third figure in the third figure is described below according to the present invention. In a test mode, the 'test/debug device 3 ^ In the access test 珲 - Tiger pin to the system single 2 the access test 埠 350 round a test signal, and the test signal is also HI to be written by people (four) and its position (four), and the interview signal is not , to the JTAG accessible shift staging in $37. According to The TAGί poor news and the clock signal generated by the controller 351 that dominates the system clock in the test mode, the JTAG controller 1300524. may further issue (asse_ control signal to write data) To the drums " type note 31; and after the writer test is completed, the data written to the embedded memory 31 is read out and the subsequent analysis is performed. Another test signal containing the address information is input to the line single chip 3 by the access test, and the money signal is then transferred to the JTAG accessible shift register 37. The jtag controls the crying to issue a control signal to the memory access data register 36 in the JTAG accessible shift register π. The address information and the clock signal generated on the clock controller 351 according to the clock of the system (10) in response to the test mode, the like (10). (4) 3\ can further control the money to give the offer The memory of the memory 31 ^ is added to the data, and added to the memory access data temporary storage Then, the data can be further moved from the memory access data buffer 36 to the ITAG-accessible shift register 37, and the IK is from the access test. The last round to the test/debug device % • towel (eg, m(6); off-time-one access action can be loaded into the JTAG accessible shift register 37. In this embodiment Because the current test mode can coexist with the built-in self-test (BIST) mode, the second multiplexer% can be used to build the self-test mode or the memory direct access of the present invention. Test ^^S (direct memory access test mode) for selection. In response to a control signal generated from the / built-in self-test controller 331, the signal output by the built-in self-test circuit 33 or the signal output by the memory access data temporary state 36 is selected. First, after passing through the second multiplexer 16 1300524 38 and transmitted to the first multiplexer 34. Through the first multiplexer 34, a built-in self-test mode/memory direct access test mode, or a positive (five) mode of operation, etc. can be selected according to the control signal sent by the JTAG controller 35. .

In the implementation process described above, the test mode is to check whether the read data is written and written by writing additional test data into the embedded memory and then reading it out. The incoming data is consistent; alternatively, a test mode can be performed during the operation of the central processing unit by reading out the data at the time of operation and checking for errors. Such a memory direct access test mode can be summarized as follows: a signal containing address information from an external device, such as the debug device 39, by means of the TTAG in the system single chip The controller in the controller takes the test and is input to the Wei single chip, and the test signal can be sent to the control signal, and the control signal (4) of the test signal Stored in the scratchpad device / in 'for example: the memory access data register 36 and the magic tag it::: 37 ' and according to the address stored in the register device two === :system? In the chip, the _ human record is executed, and then, the corpse m'a aqing lng 〇perati. Miscellaneous can be added (4) The data read in the memory can be sent to the external loading, and the external and after the test mode, if the material is measured - debug programming Can be added by Kazaki, wrong (four) Kai Ding, for example, the correct capital 17 4 1300524 t: can === in the memory of the lost memory with a and replace the error statement: the first 39 ^ - °卩On the clothing, for example: the test/debug device is turned to the =z and the correct information, and because of the heart: the = & read can be issued - control

The address information and the correct details are stored to Z, such as , the memory access data register 36 and the JTAG can be stored as a register 37, and then, according to the control signal, a data write Into the capital 7 will ^7 : ation) can be executed, according to the address; =: ϊ 梅 置 置 置 置 置 置 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存Overwrite, so

The circuit system 1 used in the memory direct access test described in the upper handle is currently used in the system single chip, and as long as the minimum cost of the special material is used, it can be used in The above-mentioned additional memory debugging operation feature is obtained in the case of the performance of ^. And the ^ " type of personnel in the final program of the chip product design can be a device to the patching state of the chip product (Hiterrogate / m〇dify) of the debug program 'by the design of the invention In addition, it will also be good at the related debugging procedures in its products. That is, the direct access method for embedded recording can effectively reduce the software itself in the process of debugging. ^昉18 13〇〇524 'Re-' for testers responsible for product testing can use the characteristics of this technology to secretize the memory (four) components, in order to improve the production of the product or to help it Analysis at the time of the error. And the present invention is described and illustrated in the manner which is considered to be the most practical and optimal, and the present invention can be implemented not only by the concept disclosed in the embodiments, but also by the present invention. It is _ in a variety of different forms and phases _ design, and in the most extensive (four) (four) ton containing all the two similar &<RTIID=0.0>>> [Simple description of the diagram] ^ By means of the lower touch and the description, the acquisition of the system - the understanding of the system: = diagram, is a system block diagram of the system system. The system has another function of self-employment. The system is not intended to be a single-chip stencil. It is a functional block diagram of the system for developing a single-chip, and the 乂 乂 贝 。 。 。 。 。 。 。 。 。 。 。 。 。 功能 功能 功能 功能 功能 功能 功能 功能 功能The components included are listed as follows: 2: 曰曰 1 1 处理 processing unit 10 甘 记忆 memory 11 (4) bus 12 12 1300524 memory controller 13 built-in self-test controller 21 reaction analyzer 23 system Single Chip 3 System Clock Control 301 Embedded Memory 31 Built-in Self Test Controller 331 JTAG Controller 35 Clock Controller 351 JTAG Accessible Shift Register 37

Test/debug device 39 Circuit to be tested 20 Pattern generator 22 multiplexer 24 Central processing unit 30 Memory access control 302 Built-in self-test circuit 33 First multiplexer 34 Access test 埠 350 Memory access data Register 36 Second multiplexer 38 Signal pins TDI, TDO

20

Claims (1)

L3〇〇524__^ I ^ ;v- 十,:= i.—2 kinds of test/debug circuits—system single-chip, including: an embedded memory; .-out; dynamic group control 11 ' The include-access test is connected to the clothing field to receive the test/debug signal from the external I placed under _ 'test=error=, and should be measured, 曰L#U And send a control signal; and use the six-series and the embedded memory to make money connections, use the 2= war/debug money (4) to access the memory of the person's memory should control the signal The information related to the information is transferred through the mf rehearsal note. The system single chip described in the first paragraph of the patent scope of the second patent includes a === pulse control and the embedded The memory of the memory is controlled by the application of the control unit, wherein the joint control 11 includes a clock control 11 for the test/spear, The clock of the system is controlled. The system single chip described in Item 1 of the Lifan Garden, wherein the temporary access: material t stomach embedded memory type signal The memory is connected to the second; 1:, the sub-' and the controller signal of the joint test action group can be connected to the ancestor-type group to access the shift register, and the memory accesses the shell = The μ and the matching test action group can access the shift register to interconnect with each other. The patent system (4), the system single chip described in item 4, further includes 21 Build self = more than one device, and the memory access data register and the internal system of crying Γ 信号 信号 连接 用 用 用 用 用 用 用 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择The L side is the record (4) access _ temporary storage sub-transfer to the person to find the material. 1. number Writing to the embedded memory, and subsequently reading the test data from the embedded memory via the register device and the access test, to 1300524 6. For example, the fifth item of the patent scope The system single chip further includes: a central processing unit; and a letter multi-worker ^, (four) first-multiplexer and the central processing unit ^, in response to a control issued by the joint test action group controller ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ For example, the system is listed in the first paragraph of the system item 3, which is a computer system that provides one of the test/debug signals. 8. If you apply for the system list described in item 1, the test information contained in the test item is included in the read-in action. The address information related to the data read in the body, and the address information and information in the writing action to write the person to the subtractive note. 9 Zhuang as the system list mentioned in the first paragraph of the patent application scope a wafer, wherein the external device is configured to pass a test data 22 1300 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524 524. The chip described in the item, wherein the external device is configured by the register device and the data read from the memory device to determine the data error material, or In the wrong mode, the device is accessed via the register device to "send the data to the embedded data." Rear- A test method for a system single chip, the method comprising the steps of: batching: an external device via a joint test action group in a system single chip. . The access scale in 曰k, the _th-test signal is input to the system slice, and the mouth should be &quot;Hai first test signal and a first control signal is sent from the joint test action group controller ; A data writing operation is performed according to the first control signal and according to the address message on the first test signal, to write the data into the embedded memory in the single chip of the system; Performing a data action of reading the embedded memory according to the address information and transferring the data extracted from the touched memory to the external device via the access test; and utilizing 4 The external device analyzes the data read from the embedded memory. 12. The method of claim 5, wherein the data reading action is performed by the joint test action group controller in response to the second control signal being issued by the second test signal. 23 1300524. The method of claim </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The address information of the test data read by the data. The method of claim 13 further includes the following steps: storing the test poor material and the address information in the single wafer of the system - the test test group can access the shift In the register, the test information is transferred to the memory access data state of the single chip of the system for performing the data writing operation. Temporary deposit 15. The method described in the application for patent (4), 14 includes: (4) Jing Cun to the joint action group can be shifted &amp; cry:: the address information is transferred to the memory The access data ': is used to perform the data reading operation.曰 口 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Transfer to the second out of the poor for output. 17: The method described in claim 16 is as follows: by selecting the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Round; road round out test: the pull output is transmitted to the embedded memory, as it is my test mode and - external measurement type - built-in 丨 18 · as described in claim 17 The method further comprises the following step 24 1300524, wherein the rounding of the test mode and the signal of the round-up of the central processing unit in the single chip of the system are transmitted to the embedded memory, thereby "Switch between the machine mode and the factory normal mode. The memory direct access test method of the human system system single chip, the method package 3 the following steps: #制2 + external device via the system single chip in a joint test action The access test in the group, a test signal is input to the single crystal (four) port of the system, and the test signal is sent from the joint test action group controller - (four) signal, the _ signal contains - address information ; the test signal is contained The address information is stored in a temporary storage device, and the address information stored in the temporary storage device is processed and the data is read by the H-type memory in the system. , 丨咅Μ = access 'Xiao 5 series and the temporary storage (4) the data read from the embedded L body is rotated out to the external device; and the material into the Si external I set to the slave The memory direct access test described in item 19 of the human memory reads the data and shoots the money, and the self-winding memory is used in the memory, and then the device is loaded. A memory access data in f is temporarily stored in the register device r η, the memory access data register is transferred to ^, the joint test action group can access the shift register, 25 1300524 The battle-riding can access the shift register register wheel I1 next single-body money face elimination method, the method package control signal; (4) the action group controller issues a 1-to-temporary address information and the first The data is stored in the system, and the system is overwritten to the second data stored in 22. The patent application body. The first data in the memory device directly accessed from the memory device is stored in the temporary register, and the first data is taken from the associated register: Then, =tT ===:=. The read access data is temporarily stored and transferred to the embedded memory.