TWI299845B - Drive circuit achieving fast processing and low power consumption, image display device with the same and portable device with the same - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a driving circuit, particularly to a driving circuit capable of driving an image display portion for displaying images, including the same, and a portable device including the same. This is achieved by driving a plurality of pixels arranged in an array. [Prior Art] In the past two years, the communication equipment, audio-visual equipment, etc. outside the information machine have gradually changed from analog signal processing to digital ==?, these machines have a thinner and lower power consumption. In the portable device represented by a mobile phone, a liquid crystal display device is used as a display device with low power consumption. The liquid crystal display device generally includes an image display unit, and a supply layer 舆f 彳 源 源 源 在 应 应 应 应 库 库 库 库 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应After that, the horizontal scanning circuit is not pressed and the circuit is made. The vertical scanning power activated by the hard line between the hard lines in the π direction: after the 'gate scanning circuit is sequentially activated by the vertical scanning circuit', the display voltage is supplied through the selected line, and the corresponding display is displayed on the pixel connected to the two t lines. According to the data, the elements contained in each element display the desired image early in the liquid phase corresponding to the voltage. In the whole image display unit, the resolution of the display device has increased in recent years, and the amount of material has skyrocketed, so there is a demand for high-speed data processing. :里=

According to 2075-7047-PF J299845, it is also necessary to use low power consumption to low consumption. Specifically, in order to be able to meet the processing and drive the lightning drive voltage, but the high-speed capital "1 scoop voltage is reduced to mutual relationship. 1 This point, generally used. Construction road operation time and resources ^ ^疋 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由In order to ensure the operation time of the internal circuit, the man sees the speed of the return and reduces the power consumption. Fighting open 2 0 〇〇 — 3 5 6 9 7 5 public interest _ _ _ 么 么 report does not have a structure, its Set the first and Le-latch state, and further reduce the floating capacitance generated by the fil 1 ^Bei 1, the line and the intersection area between the data line and the tiger line. The number of points in the intersection area between the signal lines is 1 line = the load is different, so there will be problems, such as the data supplier's degree will be wrong and the image data will not be transmitted normally. Moreover, in the case of heavy load 6^ Brother, there will be electricity to drive the data supply line _ _ 砀, bad According to the configuration disclosed in the above publication, high-speed processing can be performed and power consumption can be further reduced. 疋 In the above-mentioned A report, it is described that the control signal line for supplying the image supply line and for driving the control signal can be reduced. The suspension generated by the father and the area is electrically connected to the configuration of the power supply. However, not only the control capacitor I line 'the supply line between the supply lines but also the floating capacitance is generated. In addition, as described above, with the analysis of the display device The degree of transmission increased, and the transmission frequency of v "T* 士/, 线线 (hereinafter also referred to as data bus) also increased due to the high-speed transmission of the bulging amount of tribute.

2075-7047-PF 6 Viewing 45 Suspension Capacitance: The intersection between the busbars and the busbars is generated in the area of the valley. Furthermore, as described above, it is possible to cause the power consumption to be normal to transmit image data. "There is no error in the transmission speed." The present invention is directed to a drive circuit for consuming power, including a high-speed processing and low-intensity image display device including the circuit, and The portable circuit of the circuit is reduced, and the busbar capacitance is reduced. The monthly driving circuit is the star right part, and the image display unit of the 4 成 成 将 ^ ^ ^ ^ 禝 禝 禝 禝 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ , , /, 70 pieces of squash into a plurality of blocks of the known t-display, which is characterized by, respectively, / set μ / S μ +, · a plurality of image data supply lines, /, the knife corresponds to the upper and lower multiple areas Block π 粗 Λ 而 而 而 而 而 而 而 而 而 D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D Set and respond to the first indication signal separately to ask the image data of the image transmission line in the lock transmission; the second question lock circuit part, ... ¥ Γ _ ' lock circuit part is set and the echoes are not heard separately! 1 ί corresponds to the first _ circuit part of the _ shadow winter: material 'and brother one And the second indication signal line 'transmits the above-mentioned -##7F' respectively, wherein the plurality of image data supply lines are arranged in such a manner that they do not cross each other. The image display device preferably includes an image display portion and the above drive circuit. In particular, the portable device preferably includes the above image display device. The driving circuit, the image display device and the portable device of the present invention are configured such that the 2075-7047-PF 7 1299845 plural in, % like the feeding supply lines are arranged without interdigitating, so that the supply of image data can be reduced. The floating capacitance generated by the intersection between the lines enables high-speed processing and low power consumption. The above and other objects, features, aspects and advantages of the present invention will become apparent from DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the same or corresponding components will be described in detail with reference to the drawings, and the same reference numerals will be given to the same or corresponding components, and the description will not be repeated. First Embodiment The image display device 1 of the first embodiment of the present invention includes a liquid crystal display unit 5 (video display unit) for displaying materials, a vertical scanning circuit 2, and a horizontal scanning circuit 3. Further, the image display device 1 receives an input of a plurality of bits from the frame memory for constituting the digital signal of the image data m. The liquid crystal display portion 5 includes a plurality of liquid crystal cells % arranged in an array. On each liquid crystal cell, a color filter of any one of R (red), G (green) (blue) and three primary colors is provided, and the liquid crystal cell (R) liquid SB unit (G) and the liquid crystal cell adjacent to each other in the alignment direction (B) A display unit is formed, that is, a plurality of gate lines are arranged corresponding to the rows of the liquid crystal cells, and a plurality of source lines are arranged corresponding to the columns of the liquid crystal cells. The vertical scanning circuit 2 receives the start signal GST and the time base signal GCLK, and activates a plurality of inter-pole lines in the row direction according to the time points of the gt. 5, and the vertical scanning circuit 2 has a start signal. Activation of GST,

2075-7047-PF 8 1299845 Synchronize with the % base signal GCLK to sequentially activate the multiple inter-pole lines. The horizontal scanning circuit 3 includes a demultiplexing circuit group 4, an analog amplifying circuit group 6, a D/A conversion circuit group 8, a 帛: a LOCK circuit group 1GU lock circuit group 1, a shift register 14 and a plurality of data Bus bar]) B. The image data input by the framed memory 2 is transmitted through the data stream: rounded to the first latch circuit group 12. The first latch circuit group 1 2 responds to the instruction from the shift register 14 to flash the data, and the second challenge circuit group 10 responds to the indication of the shift register 14 to further ask for the lock data and output it to the D/A conversion circuit group. The shift register 14 is synchronized with the time base signal SCLK due to the activation of the start signal SST, and the data transmitted from the data bus (10) is fixed to the first latch circuit group 12 and the second latch circuit group 1 The control signal of the latch is output at the time. The D/A conversion circuit group 8 converts the data that is latched in the second latch circuit group, that is, the digital signal into an analog signal. Then, the analog amplifier circuit group 6 is amplified, and output to the multiplexed circuit group 4. The circuit group 4 receives the amplified analog signal, that is, the display voltage corresponding to the displayed data, corresponding to each display of the selected gate line. The unit outputs the time at which the received display voltage is divided by the respective source lines of the display voltages corresponding to the liquid crystal cell (R), the liquid crystal cell (G), and the liquid crystal cell (B). Further, the configuration of the liquid crystal display unit 5 shown in Fig. 2 will now be described using Fig. 2 . Further, in Fig. 2, only a part of the liquid crystal display unit 5 is displayed due to the relationship shown in the figure. * 2075-7047-PF 9 1299845 ί , , , 弟 2 曰 显示 s display portion 5 includes a plurality of liquid crystal cells ρ χ, a plurality of gate lines GL, a plurality of source lines SI ^ a plurality of liquid crystal cells Each consists of an N-channel thin film transistor 1〇2, a capacitor 1〇4, and a liquid crystal display element ι〇6. In addition, the thin film transistor is also referred to as "TFT" (ThinFiim).

Transistor)". A plurality of liquid crystal cells ρ are arranged in an array, a plurality of gate lines GL are arranged along the row direction, and a plurality of source lines 配置 are arranged along the column direction. Then, each of the plurality of liquid crystal cells PX is connected to the corresponding source line SL and the gate, and each of the plurality of other liquid crystal cells PX of the friend GL receives the phase-to-phase voltage VC0M. An example of this is that the N-channel TFT 102 in the liquid crystal cell ρ χ (丄, . j) (j, j; an integer of 2 or more) in the i-th row and the j-th column is connected to the source line, SL (j ) and the node. Between 8 and 8, a gate is connected to the gate line GL of the vertical scanning circuit. The liquid crystal display element 1〇6 has a liquid crystal single-electrode connected to the node 108, and a counter electrode voltage vc〇M is applied. The opposite electrode is connected to the node 1〇8 and the other side is fixed to the opposite electrode voltage VC0M. In the liquid crystal cell ρχ( i,j ), the liquid crystal display changes according to the potential difference between the liquid crystal cell electrode and the opposite electrode. The arrangement directivity of the liquid crystal in the element 1〇6 changes the brightness of the liquid crystal display element 1〇6. Thereby, the transmission source line SL (and the n-channel TFT can be displayed on the liquid crystal display element 1〇6). The brightness (reflectance) corresponding to the display voltage applied by 1〇2. Then, the gate line GL(i) is activated by the vertical scanning circuit 2 and the liquid crystal display element 1〇6 is applied from the source line SL(j). After the voltage is displayed, the gate line (〇2075~7047~pp 10 1299845 is inactivated, N channel Although the TFT 102 is turned off, the capacitor 104 can also store the potential of the liquid crystal cell electrode during the off period of the N channel TFτ ι 2, so that the liquid crystal display element 106 can maintain the brightness (reflectance) corresponding to the applied display voltage. The other liquid crystal cells have the same structure, and therefore, the detailed description thereof will not be repeated. Now, the horizontal scanning circuit 3 of the third embodiment of the present invention will be described using FIG. 3, referring to FIG. 3, the third aspect of the present invention. The horizontal scanning circuit 3 of the embodiment includes a demultiplexing circuit group 4 composed of a plurality of 1:8 demultiplexing circuits 、, an analog amplifying circuit group 6 composed of a plurality of analog amplifying circuits AM, and a plurality of d/a conversions. A D/A conversion circuit group 8 composed of a circuit DAC, a first flash lock circuit group 12 composed of a plurality of first latch circuits, a second latch circuit group 10 composed of a plurality of second latch circuits, and a data sink Rows DB1 to DB22 and data terminals DQ1 to DQ22. Further, signal lines for transmitting control signals LATA1 to LATA18 are provided, and the control signals are used to control the first latch output from the shift register 丨4 (not shown). Electricity And a signal line for transmitting the control signal UTB, the control signal is used to control the second latch circuit. In the present configuration, the liquid crystal display portion 5 in which the pixel number is set to 176 pixels in the horizontal direction will be described. This is a structure in which 17βχ 3 = 528 liquid crystal cells are arranged in the horizontal direction. Further, the liquid crystal display unit 5 is divided into a plurality of blocks in the horizontal direction. Specifically, in this example, the corresponding column direction is set to S001 to S528. The 528 source lines are divided into blocks having each of the 24 source lines. Then, corresponding to each of the plurality of blocks, 2075-7047-PF 11 1299845 is set to store a plurality of data bus rows DB. Corresponding to the block having the source lines s 〇〇丨 s s 〇 24, the lean bus bar DB1 is set. Further, the data bus DB2 is set corresponding to the block having the source lines s〇25 to s〇48. Similarly, the data bus DB 22 is set corresponding to the block having S5〇5 to S528. Each data bus]] B receives an input of image data from the data terminal DQ. That is, in the present configuration, each of the blocks is a structure for receiving the supply of the image data from one of the data bus bars DB, and the data bus bars DB are arranged so as not to intersect each other. Further, the control signals laTA:1 to LATA 18 and LATB outputted from the shift register 14 are also arranged so as not to intersect each other. A part of the first flash lock circuit group 12 and the second latch circuit group 1 of the first embodiment of the present invention will now be described in detail using the drawings. In this example, the first and second latch circuits corresponding to the data bus bars DBk and DBk+Ι are displayed. Referring to Fig. 4, the 18 first latch circuits LA respectively respond to the input of the control signals LATA1 to LATA18, latching the image data transmitted from the data bus. Then, the 'second latch circuit LB respectively responds to the input signal of the control signal to latch the image data latched by the 18 latch circuits LA. The data bus DBkH is also of the same configuration, so it is not repeated. DETAILED DESCRIPTION Referring to Fig. 5, the latch circuit LA of the first embodiment of the present invention includes transmission gates 201, 204 and inverters 202, 203, 205, 206. The input data DTA is transmitted to the node NO through the transmission gate 201. The data DTA transmitted to the node N0 is inverted by the inverter 20 5 and transmitted to the output node N1. The signal transmitted to the output node N1 is transmitted to the node pin through the inverter 205 and the transmission gate 2075-7047-PF 12 1299845 2 04. The latch is formed by the inverters 2〇5 and 2〇6. The transmission interpole 201 receives the input of the inversion signal of the control signal LATA through the inverter 2〇2 and receives the control through the inverters 2〇2 and 203. The input of the signal LATA transmits the input data DTA to the node no. Specifically, the transmission gate 2〇1 responds to the input of the control signal LATA ("η" level), and transmits the input data DTA to the node N0. The control signal LATA is off at the "L" level 4'. The transmission gate 2 0 4 receives the input of the inversion signal of the control signal LATA through the inverter 2 0 2 and receives the wheel of the control vanadium LATA through the inverters 2〇2 and 2〇3, and transmits the signal to the node n 1 Transfer to node N0 ° Specifically, the transfer gate 2〇4 responds to the input of the control signal LATA ("[" level), and transmits the signal transmitted to the node N1 to the node N〇. When the control signal LATA is at the "H" level, it is off. The latched package 1^ of the structure of the present invention responds to the logic level of the control signal LATA and its reverse signal, and forms the transmission gates 201, 2〇4 and the inverter 2〇5, 2〇6 of the flash lock portion. Enter the material DTA. In addition, in this configuration, the input control signal is single, and the internal inverter 202, 2〇3 is used to generate its reverse control signal. Therefore, the number of signal lines to which the control signal is transmitted can be reduced. Further, in the configuration of the latch circuit LB, the input control signal UTB is different, and the other portions are constructed in the same manner as the above-described latch circuit u. 6 is a diagram showing the input form of the input data DTA1 to DTA22 input to the data bus of the embodiment of the present invention. As shown in FIG. 6, in the first scan, each data terminal is sequentially called the input image data DTA1~ DTA22. In this configuration, the image is circulated to each data terminal Dq in a serial manner. Specifically, the data terminals 2075-7047-PF 13 1299845 DQ1 to DQ22 are respectively given data DTA1 to DTA22, one of which is When focusing on the material terminal DQ 1, at the first time 11, the image data of sooi(i) corresponding to the source line S1 is input. Then, at this time t1, the control signal LATA1 (Η" level is input, the image The bit data S〇〇1 ( 1 ) is latched at the first latch circuit LA. Then, in sequence ΐ2, ΐ3··, input the image bit data of 6 bits such as S001 (2), S001 (3), ... S001 (6) in sequence, and input control signals LATA2 to LATA6 ("Η "Level", sequentially latched in the first latch circuit LA. Here, the symbol () 〇 represents bit data for specifying the wheel-out voltage corresponding to the source line > sooi. Specifically, (1) represents the first station and (6) represents the sixth unit. The image data of the pixel unit is formed by the image bit data of the 6 bits. Similarly, after inputting the image data of 6 bits of the source line S00 9 and the image data of 6 bits of S01 7 , the input of the control signals LATA7 to LATA18 is responded to and latched. After the input period of the 18-bit image data, the control signal LΑΤβ ("Η" level) is input, and the image bit data latched on the 18 latch circuits 1a is latched in the second latch circuit. lock. This series of processing is equivalent to the first scan. The image bit data latched in the second latch circuit is targeted by the D/A conversion circuit DAC and the analog amplifying circuit! ··8 Solve the multiplexed circuit's source line to drive a given voltage. Specifically, for the source lines s〇〇1, s〇〇g, S017, a predetermined voltage corresponding to the image bit data of 6 bits is driven. In the above-mentioned period, the second scan is started while driving the D/A conversion circuit DAC and the analog amplifying circuit am and 1:8 to solve the source line of the multiplex circuit. Specifically, the image bits corresponding to the source lines such as the source lines S002, S010, and S018 are input in a serial manner. After that, repeat the same process. For each of the 2075-7047-ΡΡ 14 1299845 material terminals DQ2 to DQ22, the same processing is performed in parallel with the Ί^ equation. Further, there are eight types of 1:8 demultiplexing circuits, and the right horse image data is displayed on the liquid crystal display unit 5 by the processing of the above. All the shirts in this structure, as shown in Figure 3, the flat women's factory 丄nR,, R each block set data bus DB, sub-, and the poor material bus bar DB between your B 匕 do not cross each other To configure. Yu Yu can reduce the floating private valley between the data bus and the domain, and then process it at high speed and reduce power consumption. #再者, regarding the control input to the first question lock circuit and the second flash lock circuit _ "ATA bat LATA1 8 and LATB, also configured in the way of data bus _ mutual intersection. By this, the data bus DB The floating capacitance generated by the signal line for transmitting the control signals LATA and LATB can also be reduced, thereby performing high-speed processing and reducing power consumption. Further, in the present configuration, as an example, the liquid crystal display unit is driven to be used as an example. The configuration of the driving circuit, wherein the liquid crystal display portion has 176 pixels, that is, 528 source lines S001 to S528. However, the configuration of the driving circuit is not limited to the above, and the configuration may be such that the number of data terminals DQ The number is set to 22, the number of the first and second latch circuits corresponding to each terminal DQ is set to 24, the number of multiplexed circuits is set to 6 'or, and the number of data terminals DQ is set to 33. The number of the first and second interrogation circuits is set to 丨2, and the number of multiplexed circuits is set to 8. The second embodiment now uses the seventh embodiment to explain the first embodiment of the second embodiment in detail. Part of the second latch circuit group. Here, First and second latch circuits corresponding to data terminals DQk and DQk+1. 2075-7047-PF 15 1299845 In this example, the difference is that the _ 装 罘 latch circuit group 12 is replaced by a brother A latch circuit group 12#. The difference between the question lock circuit group 12# is that the corresponding data sinks the set potential converter LSF. Generally speaking, the tft^ value of the operating voltage constituting the pixel is high. Therefore, it is necessary to supply an electric grinder of 5 V (volts or more). First, 'present the state of the amplitude conversion potential of the tributary signal as the driving voltage level of the data bus," ie, the driving voltage of (10) or more is given to the image bit. Metadata. ^ In this configuration, before the data is input from the data bus bar DB to the first latch circuit LA, the potential converter lsf is set. In this configuration, the data signal of the data bus can be transmitted. For example, the drive voltage of 3V is driven by the potential converter lsf to increase the amplitude level of 5V, thereby reducing the amplitude level of the data signal of the data bus (10), thus further suppressing the consumption in the data bus. Power consumption For a modification of the second embodiment, a part of the first and second latch circuit groups according to a modification of the second embodiment of the present invention will be described in detail with reference to Fig. 8. Second, the second embodiment of the present invention The configuration of the modified example is different in that the first latch circuit group 12 is replaced with the first latch circuit group 1 2#. The other aspects are the same, and thus the detailed description thereof will not be repeated. In the first latch circuit group 12#a' of the modification of the embodiment, the difference is that the latch circuit LA is replaced with the latch circuit LA#. 4 a FIG. 9 'the second invention of the present invention Latch circuit LA# of a modification of the embodiment

2075-7047-PF 16 1299845 The converter 21 is compared to the moon lock circuit u illustrated in FIG. The dimming potential potential is converted to 21 0, including the buffer 207 with the buffer ^ 2 〇 8 and the potential conversion crying, and the transmitted 207; the structure is transmitted from the data lion rushing The amplitude of the number can be 0~3 volts, the first lock circuit LA# is rotated into the data signal of 0~3V. That is, the charging and discharging of the data bus DB is caused by the charging and discharging] The cross-capacitance is opposite to the opposite electrode = power consumption. The data busbar wiring surrounds the panel terminal: = the part of the device, so there are several tens of centimeters long, and the parasitic power between the opposing electrodes is also equivalent. Big value. Therefore, under ... and ==, the power consumed by the first power lock_input can be effectively reduced. Ί In the first-lock lock circuit LA#, the question lock portion of the data is driven with the same voltage of 3 volts as the input == amplitude, and the _changer 210 is set again after the lock is applied. ~5V signal conversion potential. In addition, the spur potential conversion caused by the potential (four) 21 〇 can be performed in the second flash lock circuit, but the output of the first flash lock circuit and the control signal LATA are opposite to the capacitance and the opposite electrode capacitance. The load is increased, and there is a 3V drive. Therefore, in order to ensure sufficient drive capability, it is necessary to convert the buffer capacity of H2l〇 to (4), that is, the inverter is set to be very large, but the efficiency in design area is therefore In addition, the power consumption of this buffer portion is increased. Therefore, in the configuration of the lock circuit of the modification of the second embodiment, the 2075-7047-PF 17 1299845 is converted to drive the flash lock circuit LA# with 5V, and the electric buffer is shortened shortly after the lock is applied. Design area. In addition, 'hunting by the first latch circuit NING IE 43⁄4 ^ ^ Φ Λ i mouth and then to 3V drive, resulting in a 1, the body to increase the amount of rain, at this time mixed & mountain" below The way to suppress. With

Body and L, will constitute the frequency converter 205 of the wheel b „ 7 rebel into the electric pole of the body's pole width / gate length and (/ 丄) ΰ and pay ratio constitute the first question lock mountain + θ door lock circuit to The output gate of the inverter 205 has a smaller gate width/gate length (W/L). By turning on the potential converter 21, it is possible to suppress the latching required in the first latch circuit. In LA#, the W/L ratio of the input transistor is set to increase in a relatively small time. The meal brother 1 0 A picture 'in the installation of the shadow silly strong and strong to the forklift another ~ 1 boundary is not described in the mobile phone 丨3 〇〇, a plurality of operation buttons 1 302 and a liquid crystal display unit 1 〇〇 5 are displayed. Photograph 10B of the photo shows a display information output source 1 inside the mobile phone 13 〇〇〇, display information processing circuit丨002, power circuit 1〇〇4, image display device 1 006 time base generator 200. The display information output source 1 000 includes the frame memory, etc., R〇M (Read 〇nly, RAM (Random Access Memory) ), such as memory, various disk storage units, coherent circuits that output video signals, etc., perform response operations输入3〇2 input operation and outputting interface information such as display information for the predetermined input processing, etc. Further, 'the image processing circuit 1 〇〇2 is supplied with the image of the predetermined format according to various time base signals generated by the time base generator 200. The information processing circuit 1 002 includes a variety of known circuits such as a rotating circuit and a 7-correcting circuit, and processes the input display information, and the image data DTA together with various time base signals such as the above GCLK, SSLK and Start 2075-7047-PF 18 1299845 Signals GST, SST and other control signals are supplied to the camera from the $Su. 琶1 0 0 6. jk External 'Power Circuit 1 004 supplies the structural elements with the power of the other brothers. , electrical, is not limited to the line

Le phone, you can also use A day TV, video recorder, vehicle guidance device - a ^ device. The present invention has been described in detail in the various displays of the information, and is merely a 搓# 垣 死 死 死 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Gangyue arsenic and its scope are only limited by the attached patent of the company. [Simplified illustration] Figure 1 is a schematic block diagram showing the image of the invention. Fig. 2 is a circuit diagram showing the structure of the liquid crystal display unit shown in the drawing. The electric drawing is a schematic block diagram showing the structure of the horizontal sweeping body 4 of the first embodiment of the present invention. A part of the first lock circuit group and the second flash lock circuit group according to the first embodiment of the present invention will be described in detail. "By the circuit structure of the latch circuit of the present invention." The timing chart illustrates the input form of the wheeled data of the input bus of the first embodiment of the present invention. / FIG. 7 is a conceptual diagram for explaining in detail the first part of the second embodiment of the present invention and a part of the latch circuit group. Figure 8 is a structural diagram illustrating the present invention in detail 2 is a part of the first embodiment and a part of the latch circuit group. Fig. 9 is a diagram showing the structure of the circuit of the town of the second embodiment of the second embodiment of the present invention, 2〇75-7〇47-ρρ 19 1299845. 1 OB diagram is a diagram illustrating an appliance in which an image display device is mounted. [Main component symbol description] 1 image display device 2 vertical scanning circuit 3 horizontal scanning circuit DM demultiplexing circuit > DAC D/A conversion circuit 4 is multiplexed Circuit group 5 liquid crystal display part 6 analogy circuit group 8 D/A conversion circuit group 1 0 second latch circuit group 12, 12# first latch circuit group 14 shift register 1 DB, DB1~DB22 data Bus DQ, DQ1~DQ22 Data Terminal DAT, DAn~DAT22 Data LATA, LATA Bu LATA18, LATB Control Signal PX Liquid Crystal Cell GL Gate Line SL, S001~S528 Source Line VC0M Electrode Dust

2075-7047-PF 20 1299845 LA, LA# first latch circuit LSF potential converter 2 0 frame memory 102 Ν channel thin film transistor (Ν channel TFT) 104 capacitor 1 0 6 liquid crystal display element 108, NO, N1 node 200 time base generator > 201, 204 transmission gate 202, 203, 205, 206, 207, 208 frequency converter 209 potential converter unit 210 potential converter 1 000 display information output source 1 002 display information processing circuit 1 004 power circuit 1006 image display device 1300 mobile phone

2075-7047-PF 21

Claims (1)

Revision date: 96.11· 5 The image display unit arrays are arranged in an array. The number of applications for which the number of the TL pieces is divided into a plurality of blocks is revised. The scope of the patent application: 1 · The drive circuit, gg JU, 4 pieces 'Drives the plurality of above-mentioned image display units, characterized by comprising: / a plurality of image data supply lines respectively corresponding to the plurality of blocks, and the mouth is set again and the knife receives a supply of a plurality of bit data, The bit data is used to form image data displayed on the image display unit; and the first-flash lock circuit unit is respectively disposed corresponding to the plurality of image data supply lines and respectively responds to the first indication signal to send the lock to Corresponding image data supply line image data; • 13 number f two-flash lock circuit portion 'which respectively corresponds to the plurality of first flash lock circuit portions and respectively respond to the second indication 1 - is asked in the flash lock circuit portion The image data of the lock; and the first and second indication signal lines of the brothers, which respectively transmit the first and second indication signals; wherein the plurality of image data are provided for Lines do not intersect each other are each configured. 2. The driving circuit of claim 1, wherein the driving circuit further comprises a plurality of digital amplification conversion portions respectively corresponding to the plurality of second flash lock circuit portions for respectively corresponding second error lock circuit portions The output of the number is converted from the digital signal into an analog signal and is extracted to the plurality of shadows, wherein the first one is as follows: the driving circuit of the first item of claim 1 2075-7047-PF2 22 1299845 Πη and the second Instruct the signal line to not match the ιΓ你·欠... The above shirts are arranged like the * supply line. 4. The driving circuit of claim 3, wherein one of the first and second flash lock circuit units is connected to the single first signal line and the second indicator signal line. And at least one of the first and second flash lock circuit sections includes an inversion circuit that receives an indication signal of the at least one of the indication signal lines and reverses the logic level. Outputting, each of the first flash lock circuit portions includes a first flash lock portion that responds to the logic level of the first indication signal and reverses the logic level of the first indication signal by a signal H. The second flash lock circuit portion includes a second question lock portion that responds to the logic level of the second instruction signal and reverses the logic level of the second indication signal. The first flash lock is the latched bit data in the road section. The driving circuit of claim 3, wherein each of the image-poor supply lines transmits a plurality of bit data constituting the image data input in a serial manner. 6. The driving circuit of claim 1, wherein the potential converter circuit is disposed between each of the image data supply lines and the corresponding first-flash lock circuit portion, and has a small amplitude of the bit data. The digital signal is converted into a large amplitude digital signal. 7. The driving circuit of claim 1, wherein the potential converter circuit is further configured to convert the small amplitude digital signal of the bit data on the first flash lock circuit portion into a large amplitude digital position. Signal, lose 2〇75-7 04 7-PF'2 23 1 1 1299845 goes out to the second latch circuit section. 8. The driving circuit of claim 7, wherein the first latch circuit 邛 has an output transistor for rotating the latched signal, and the packet is converted into a circuit having a buffer circuit. An input transistor is provided to receive the signal input of the output transistor lock output, and the input transistor of the buffer circuit is designed to be below the size of the output transistor. 9. The driving circuit of claim 8 wherein the channel width (W) / channel length (L) of the above-described wheel-in transistor is designed to be the channel width (w) / channel length of the above-mentioned wheel transistor (L) )the following. ~ 10· An image display device, including the scope of the patent application. The dynamic circuit further includes an image display unit. Drive 11 · A portable machine, including an image display device with a patent range of q π 1 mussels. ~ 2075—7047—PF2 24