1298526 五、發明說明（ I ) 1 .本技藝所屬技術領域 .务技藝適用於記憶體I c之「容量可以分割」之設計，特別 適用於彈性減半記憶體I C容量之設計。 2 .先前技術 習知技藝如圖1所示，以2MB記憶體I C 1 0，作為範例說明， 習知的記憶體為製作成為單一容量記憶體I C之產品，僅需 一半容量之記憶體時，須以控制電路設定捨棄一半容量不 |，實體上無法切割成為一半容量之記憶體，形成一半晶 面積之浪費；若想節省成本，提高兩倍利潤空間，須要 減半容量之記憶體I C時，將被視為是另外一個新的產品， 須要另外為此減半容量之記憶體產品特別設計一套光罩， 才可以生產此一減半容量之記憶體產品。當客戶需求更多 不同容量記憶體I C時，就須要針對每一個不同記憶體容量 的產品，分別設計一套之光罩，也就是一套光罩只能生產 一個記憶體容量之產品，本技藝便是可以以一套光罩可以 同時生產全量記憶體、減半容量之記憶體產品、或是再減 半容量之記憶體產品。 懦·本技藝之内容 本技藝乃是為了配合客戶對於記憶體容量之彈性需求，降 低生產成本以及時間之設計。在高密度的產品中，晶片切 割以後，鄰近的金屬線可能會因為切割刀的拉動造成短路 問題，本技藝在被切割的金屬線兩邊分別安置有通過電晶1298526 V. INSTRUCTIONS (I) 1. The technical field of the art belongs to the design of the "capacity can be divided" of the memory I c, and is particularly suitable for the design of the elastic halving memory I C capacity. 2. Prior art techniques are shown in FIG. 1, with 2MB memory IC 10 as an example, a conventional memory is a product that is a single-capacity memory IC, and requires only half of the memory. If the control circuit is set to discard half of the capacity, it cannot be cut into half the capacity of the memory, which is a waste of half the crystal area. If you want to save costs and increase the profit margin by half, you need to reduce the memory IC by half the capacity. It will be considered as another new product, and it is necessary to specially design a mask for this half-capacity memory product to produce this half-capacity memory product. When customers need more different capacity memory ICs, they need to design a set of reticle for each product with different memory capacity, that is, a set of reticle can only produce one memory capacity product. It is possible to produce a full-size memory, a half-capacity memory product, or a half-capacity memory product with a single mask.懦· The content of this technology This technology is designed to meet the customer's flexible demand for memory capacity, reducing production costs and time. In high-density products, after the wafer is cut, the adjacent metal wires may be short-circuited due to the pulling of the cutting blade. The art is placed on both sides of the cut metal wire through the electro-crystal
1298526 五、發明說明（2) 體（p a s s t r a n s i s t 〇 r )，以便在生產減半容量之記憶體I C 時，可以將電晶體關閉，如此可以避免切割造成金屬接線 .2 3之間或與晶圓基底的短路，致使最終產品在運作時功能 失常。 本技藝包含有控制電路（圖中未表示），用以控制整個產品 之記憶體之使用，當生產全容量之記憶體時，控制電路將 通過電晶體的開關打開（ο η )，同時，控制兩塊記憶體區塊 «使用。當生產半量之記憶體產品時，控制電路將通過電 體的開關關閉（ofO，避免切割線因為短路對產品運作 時所產生的雜訊。 4.實施方式 圖2本技藝之實施例一 顯示本技藝之製作方式，以相對於圖1所示之2MB記憶體 I C 1 0，作為範例對照說明。本技藝將2 Μ B記憶體I C 2 0，以 兩個1 Μ Β之記憶體區塊2 1、2 2相連接構成。具有相同容量 «第一區塊記憶體2 1、以及第二區塊記憶體2 2，每個記憶 區塊都會於側邊安置一「通過電晶體」，第一組通過 電晶體2 1 R，安置於1 MB記憶體2 1的右邊；第二組通過電晶 體2 2 L，安置於1 Μ B記憶體2 2的左邊。多條金屬接線2 3，安 置於前述之兩組電晶體2 1 R、 2 2 L中間，金屬接線2 3用以電 性耦合兩區塊記憶體2 1、2 2使成為一整體，以便結合兩區1298526 V. Inventive Note (2) Body (passtransist 〇r ), in order to produce a half-capacity memory IC, the transistor can be turned off, so as to avoid cutting metal wiring. 2 3 or with the wafer substrate The short circuit causes the final product to malfunction during operation. The art includes a control circuit (not shown) for controlling the use of the memory of the entire product. When a full-capacity memory is produced, the control circuit is opened (ο η ) through the transistor switch, and at the same time, controlled. Two memory blocks «used. When a half of the memory product is produced, the control circuit will be turned off by the switch of the electric body (ofO, avoiding the noise generated by the cutting line due to the short circuit to the product operation. 4. Embodiment FIG. 2 shows the first embodiment of the present technology The method of making the technique is described with reference to the 2MB memory IC 1 0 shown in Fig. 1. The art will be 2 Μ B memory IC 2 0, with two 1 Β memory blocks 2 1 2 2 phase connection structure. With the same capacity «first block memory 2 1 and second block memory 2 2, each memory block will be placed on the side of a "passing transistor", the first group Placed on the right side of the 1 MB memory 2 1 through the transistor 2 1 R; the second group is placed on the left side of the 1 Μ B memory 2 2 through the transistor 2 2 L. A plurality of metal wires 2 3 are disposed in the foregoing In the middle of the two sets of transistors 2 1 R and 2 2 L, the metal wires 23 are electrically coupled to the two block memories 2 1 and 2 2 to form a whole body, so as to combine the two regions.
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1298526 五、發明說明（3) 塊記憶體2 1、2 2提供2 Μ B全量記憶體（f u 1 1 c a p a c i t y )產品 '之使用。 ΐΐ 3 .本技藝實施例二 當客戶需要的產品為2MB全量記憶體產品時，依據圖2的設 計，在晶圓階段（w a f e r s t a g e )依據水平切割線Η 1、垂直 切割線V 1加以切割，便可以產出2ΜΒ之全量記憶體產品。 g客戶需要1 Μ B記憶體I C時，恰好為前述2 Μ B記憶體I C之半 ，便可以將圖2的產品沿著中央切割線切割而獲的兩個 1 Μ Β之記憶體I C。如圖3所示，將2 Μ Β之記憶體I C，沿著水 平切割線丨I 2、垂直切割線V 2加以切割，便可以產出半容量 記憶體I C 2 1、2 2。 圖4 .本技藝實施例三 顯示本技藝在每個半量記憶體區塊的兩邊，各安置一排通 過電晶體。圖中顯示第一組通過電晶體21 L安置於記憶體 2 1的左邊，第二組通過電晶體2 1 R安置於記憶體2 1的右 «。第三組電晶體2 2 L安置於記憶體2 2的左邊，第四組電 體2 2R，安置於記憶體22的右邊，如此，可以向記憶體 2 1的左邊擴充擴增與鄰近該邊之第三區塊記體相聯接，也 可以向記憶體2 2的右邊擴增與鄰近該邊之第四區塊記體相 聯接，而擴充更大的記憶體容量，生產更為彈性之記憶體 1 C，提供更多不同容量之記憶體I C，然而只使用了 一套光1298526 V. INSTRUCTIONS (3) Block memory 2 1 and 2 2 provides the use of 2 Μ B full memory (f u 1 1 c a p a c i t y ) product '. Ϊ́ΐ 3. In the second embodiment of the present technology, when the product required by the customer is a 2MB full-size memory product, according to the design of FIG. 2, the wafer stage is cut according to the horizontal cutting line Η 1 and the vertical cutting line V 1 . It can produce 2% of the full amount of memory products. When the customer needs 1 Μ B memory I C, which is exactly half of the above 2 Μ B memory I C , the memory of the product of Fig. 2 can be cut along the central cutting line to obtain the memory 1 C of the two 1 Μ 。. As shown in Fig. 3, by cutting the memory I C of 2 Β 沿着 along the horizontal cutting line 丨 I 2 and the vertical cutting line V 2 , the half-capacity memory I C 2 1 , 2 2 can be produced. Figure 4. Embodiment 3 of the present technology shows the art by placing a row of transistors through each of the two sides of each half-size memory block. The figure shows that the first group is placed on the left side of the memory 2 1 through the transistor 21 L and the second group is placed on the right side of the memory 2 1 through the transistor 2 1 R. The third group of transistors 2 2 L is disposed on the left side of the memory 2 2 , and the fourth group of electrodes 2 2R is disposed on the right side of the memory 22, so that the amplification and the adjacent side can be expanded to the left side of the memory 2 1 The third block is connected to the body, and can also be expanded to the right side of the memory 2 2 and connected to the fourth block of the adjacent side to expand the larger memory capacity to produce a more flexible memory. Body 1 C, providing more memory ICs of different capacities, but using only one set of light
1298526 五、發明說明（4) 罩 ° .圖5 .本技藝實施例四 k示本技藝的部分電路示意圖，本技藝之兩區塊記憶體I C 3 0 1， 3 0 2，每一個記憶體區塊都分別具有多個銲墊3 1 4， 箭頭3 1 0表示打線，以將銲墊耦合至外部。金屬線3 3將記 憶體3 0 1 , 3 0 2兩區塊對應之銲墊--並聯。每一條金屬線 3 3兩側皆安置有通過電晶體3 2 2，第一組通過電晶體3 2 2在 i 一記憶體區塊的一邊，第二組通過電晶體3 2 2在第二記 體區塊的一邊，兩組通過電晶體32 2係安置在兩區塊記 憶體的相鄰邊附近。所有通過電晶體3 2 2的閘極，皆電性 耦合至G銲墊3 1 2。當兩區塊記憶體3 01，3 0 2整合為一體使 用時，通過電晶體3 2 2被設定為打開；當兩區塊記憶體 3 0 1，3 0 2被切割為兩個單體分別使用時，通過電晶體3 2 2被 設定為關閉。 當兩區塊記憶體3 0 1， 3 0 2被整合使用時，因為兩區塊記憶 體3 0 1， 3 0 2的所有對應銲墊皆是一對一相耦合，因此，當 «墊打線耦合至外部電路時，只要選擇一邊記憶體區塊的 墊對外打線耦合即可，另外一邊記憶體區塊的銲墊保持 空接不必打線。 以NMOS作為通過電晶體為例，當兩區塊記憶體30 1，3 0 2被 切割為兩個單體分別使用時，圖中顯示G銲墊3 1 2耦合電晶1298526 V. Description of the invention (4) hood ° Figure 5. The embodiment of the present invention shows a partial circuit diagram of the art, two blocks of memory IC 3 0 1, 3 0 2 of the art, each memory area The blocks each have a plurality of pads 3 1 4, and an arrow 3 1 0 indicates wire bonding to couple the pads to the outside. The metal wire 3 3 connects the pads corresponding to the two blocks of the memory body 3 0 1 , 3 0 2 in parallel. Each of the metal wires 3 3 is disposed on both sides thereof through a transistor 3 2 2 , the first group passes through the transistor 3 2 2 on one side of the i memory block, and the second group passes through the transistor 3 2 2 in the second row One side of the body block, two sets are placed near the adjacent sides of the two block memories by a transistor 32 2 system. All of the gates through the transistor 3 2 2 are electrically coupled to the G pad 3 1 2 . When the two block memory 3 01, 3 0 2 is integrated into one, the transistor 3 2 2 is set to be turned on; when the two block memory 3 0 1, 3 0 2 is cut into two cells respectively In use, the transistor 3 2 2 is set to off. When the two block memories 3 0 1, 3 0 2 are used in combination, since all the corresponding pads of the two block memories 3 0 1, 3 0 2 are one-to-one coupled, therefore, when the padding line When coupling to an external circuit, it is only necessary to select the pad of the memory block to be externally coupled, and the pad of the memory block remains empty without wiring. Taking NMOS as the pass transistor as an example, when the two-block memory 30 1,3 0 2 is cut into two monomers, respectively, the figure shows the G pad 3 1 2 coupled electron crystal.
1298526 五、發明說明（5) 體32 4洩極接地（低電位），原因是電晶體32 4因閘極接Vdd 、導通電晶體3 2 4使得源極和洩極電位皆為低電位，用以預 .設通過電晶體3 2 2為關。當兩區塊記憶體3 0 1，3 0 2整合使用 時，G銲墊3 1 2打線至高電位（Vdd )，因此，將NMOS通過電 晶體3 2 2打開，便可以使用兩區塊之記憶體。 選擇器銲墊3 1 6， 係用以控制兩區塊記憶體之資訊存取， 例如：當選擇器銲墊3 1 6接收到訊號Ob夺，内部的解碼器 中未表示）將指示系統使用左邊的記憶體區塊之貪訊存 當選擇器銲墊3 1 6接收到訊號1時，内部的解碼器（圖 中未表示）將指示系統使用右邊的記憶體區塊之資訊存 取。 前述描述揭示了本技藝之較佳實施例以及設計圖式，惟， 較佳實施例以及設計圖式僅是舉例說明，並非用於限制本 技藝之權利範圍於此，凡是以均等之技藝手段實施本技藝 者、或是以下述之「申請專利範圍」所涵蓋之權利範圍而 實施者，均不脫離本技藝之精神而為申請人之權利範圍。1298526 V. INSTRUCTIONS (5) Body 32 4 venting ground (low potential), because the transistor 32 4 is connected to Vdd by the gate, and the conduction current crystal 3 4 4 makes the source and the bleed potential all low. It is set to pass through the transistor 3 2 2 in advance. When the two-tile memory 3 0 1,300 is integrated, the G pad 3 1 2 is wired to a high potential (Vdd). Therefore, by opening the NMOS through the transistor 3 2 2, the memory of the two blocks can be used. body. The selector pad 3 1 6 is used to control the information access of the two-tile memory. For example, when the selector pad 3 16 receives the signal Ob, the internal decoder does not indicate that the system will be used. Corruption of the memory block on the left When the selector pad 3 16 receives the signal 1, the internal decoder (not shown) will instruct the system to access the information using the memory block on the right. The above description of the preferred embodiments and the drawings are intended to be illustrative of the preferred embodiments of the invention, and are not intended to limit the scope of the invention. The present invention is intended to be within the scope of the applicant's scope of the invention.
第10頁 1298526 圖式簡單說明 5 .圖式的簡單說明 '圖1 .習知技藝 .圖2 .本技藝實施例一 圖3.本技藝實施例二 圖4.本技藝實施例三 圖5.本技藝實施例四 6 .元件編號表 «憶體 I C 1 0， 2 1， 2 2， 3 0 1，3 0 2 過電晶體 21L， 21R， 22L， 22R， 金屬接線 23， 33 322Page 10 1298526 Brief Description of the Drawings 5. Brief Description of the Drawings Fig. 1. Conventional Skills. Fig. 2. Embodiment 1 of the present technology Fig. 3. Embodiment 2 of the present technology Fig. 4. Embodiment 3 of the present technology Fig. 5. Embodiment 4 of the present technology 6. Component number table «Remembrance IC 1 0, 2 1, 2 2, 3 0 1, 3 0 2 Transistor 21L, 21R, 22L, 22R, metal wiring 23, 33 322