TWI298351B - Bonded structure for a thin-film circuit - Google Patents

Bonded structure for a thin-film circuit Download PDF

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Publication number
TWI298351B
TWI298351B TW094108743A TW94108743A TWI298351B TW I298351 B TWI298351 B TW I298351B TW 094108743 A TW094108743 A TW 094108743A TW 94108743 A TW94108743 A TW 94108743A TW I298351 B TWI298351 B TW I298351B
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Taiwan
Prior art keywords
electrode layer
thin film
alloy electrode
film circuit
aluminum alloy
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TW094108743A
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Chinese (zh)
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TW200536944A (en
Inventor
Takashi Kubota
Yoshinori Matsuura
Makoto Ikeda
Kazuteru Kato
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Mitsui Mining & Smelting Co
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13458Terminal pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Description

1298351 九、發明說明: 【發明所屬之技術領域】 本發明係關於構成顯示裝置的薄膜電路,特別是關於 具有液晶顯示器中之透明電極與紹合金電極的薄膜電路之 接合構造。 【先前技術】 對資訊機器、AV機器、家電製品等的顯示裝置而言, 目前正廣泛地使用採用諸如薄膜電晶體(Thin Film Transistor,以下簡稱TFT)的顯示器。對於此種顯示器來 說,有使用以薄膜電晶體為代表的主動式矩陣方式的液晶 顯示器(LCD)、自行發光型的有機發光二極體(〇ELD)或 使用被動式矩陣方式的有機發光二極體等種種元件結構被 提出,此種元件係以由薄膜所形成之薄膜電路所構成,以 進行前述元件顯示的控制。 在上述各種顯示裝置的元件構造中,大多是具有以銦 錫氧化物電極為代表的透明電極以及接線用的導電性電 極。此種薄膜電路的構造係為直接影響顯示裝置的品質、 電力消耗、產品成本的重要因素,此種構造改善在現今的 狀態下被日益要求著。 對於此薄膜電路的構造而言,以液晶顯示器(LCD)為 例,以下具體說明所期望要改善的事項。 具有佔據顯示裝置中心傾向的液晶顯示器(LCD),由 於喚醒高精細化、低成本化’因此廣泛採用薄膜電晶體的 兀件構造料此薄膜電路。而且,使用銘合金作為此薄膜 2169-6972-PF 5 1298351 電路的接線材料。對此薄膜電晶體等的薄膜電路而言,在 形成用以構成接線或電極的電極層之際,大多也使用鋁合 金薄膜,此係因習知所使用之鈕、鉻、鈦及其合金等高熔 點材料的比阻抗較高等理由,故以比阻抗低、接線加工容 易的銘作為替代材料,係為顯著的結果。 然而,在由此鋁合金薄膜形成電極層(鋁合金電極層) 之情形下,液晶顯示器中關於銦錫氧化物電極層等的透明 電極的接觸部分而言,已知會發生下列現象。此係鋁合金 電極層與銦錫氧化物電極層直接接合時,由於此兩層之電 化學特性的差異,因此會於此兩層之接合介面上產生電化 學反應,進而產生接合介面的破壞或阻抗值的增加。為此, 於液晶顯示元件上使用鋁合金電極層之際,需形成由鉬或 鉻等形成之所謂的蓋層(或接觸阻擋層。以下使用『蓋層』 一詞時,係有包括接觸阻擋層的含意)。(例如是參照非 專利文獻1 ) [非專利文獻1]内田龍男編著,『次世代液晶顯示 器技術』,初版,工業調查會股份有限公司,1 994年11月i 曰,第36頁至第38頁 其中具有鋁合金電極層的薄膜電晶體必須設置有以 鉬、鉻等為主要材料的蓋層。於薄膜電晶體構成材料中使 用鋁合金薄膜之情形下,由於不可避免地需要形成蓋層, 因而此層積構造複雜,而導致生產成本的增加。而且,最 近在構成此蓋層的材料中,有排除鉻的使用之市場動向, 而致對形成盍層之技術開始產生大的限制。 2169-6972-PF 6 1298351 • 可是’在最近的薄膜電晶體製造技術中,也有提倡省 略上述蓋層的製造技術。例如在專利文獻1中,揭露可與銦 錫氧化物電極層直接接合的假定鋁接線膜以及關於此的濺 鍍標靶。此專利文獻1中,鋁接線膜係在鋁中含有既定量之 用以形成鋁與金屬間化合物的元素或標準電極電位高於鋁 的元素、碳、氧、氮、氫等,即可達到蓋層省略的結果。 [專利文獻1] 國際公開第W097/1 3885號 再者’專利文獻2中,揭露一種使用鋁合金膜的顯示裝 置及其製造技術,此技術可以將鋁合金膜與透明電極膜直 接接觸,且可以省略阻擋金屬。此專利文獻2係將構成鋁合 金膜之合金成分中的一部份或全部,以析出物或濃縮層的 方式存在於鋁合金膜與晝素電極直接接觸的介面上,以省 • 略阻擋金屬(蓋層)。 [專利文獻2] 特開20 04-214606 此種先前技術,基本上大多數例示的鋁合金,係著重 在銘合金中之合金元素或析出物(例如是金屬間化合物), •以传到直接接合的可能性。 【發明内容】 [發明所欲解決的課題] 然而’關於鋁合金的各種組成或鋁合金中的析出物(金 屬間化合物)存在’無論是由習知所知的、上述專利文獻1 • 或上述專利文獻2,均難以確認關於各種合金元素或金屬間 化合物的存在有助於直接接合的推測。亦即在此種先前技 術中,鋁合金中之合金元素或析出物等,究竟是依據何種 2169-6972-PF 7 1298351 要因而抑制直接接合之際的界面反應,並未特別明示此現 象的說明。 ’ 為此’關於可能省略蓋層之液晶顯示元件的開發而 °由於並未具體指出如何抑制直接接合之界面反應,因 此現在的狀況是必須檢驗證明各種組成的鋁合金。再者, 用以抑制界面反應的銘合金組成也需滿&液晶顯*元件的 全部特性,亦即所謂的對應歐姆接合的電流-電壓特性、接 合阻抗性、接線阻抗性、耐熱性等,以得到實用的液晶顯 •示元件的構造,然實情仍是困難的。 還有,在此液晶顯示元件中,可直接接合的接合構造, 在其他有機發光二極體(0ELD)或利用被動式矩陣方式的 有機發光二極體等薄膜電路中,實情是也同樣被要求著。 - 本發明係在以上述事情為背景的情形下,提供一種薄 膜電路之接合構造,於具有透明電極層與銘合金電極層的 薄膜電路中,不僅可以省略蓋層,也不會產生界面反應, 也可以歐姆接合,也具有較佳之接合特性。還有,提供— 種實用的、極適用的薄膜電路之接合構造,以在液晶顯示 兀件採用此薄膜電路之際,可以與以銦錫氧化物為代表透 明電極層直接接合,也可確實達到界面反應的抑制,並滿 足歐姆接合特性、低接合阻抗、接線膜阻抗、耐熱性等全 部液晶顯示元件特性。 [用以解決課題的手段]BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film circuit constituting a display device, and more particularly to a bonded structure of a thin film circuit having a transparent electrode and a sintered alloy electrode in a liquid crystal display. [Prior Art] For display devices of information equipment, AV equipment, home electric appliances, and the like, a display such as a Thin Film Transistor (TFT) is currently widely used. For such a display, there is an active matrix liquid crystal display (LCD) represented by a thin film transistor, a self-luminous organic light emitting diode (〇ELD), or an organic light emitting diode using a passive matrix method. Various element structures such as a body are proposed, which are constructed by a thin film circuit formed of a film to perform control of display of the aforementioned elements. In the element structure of each of the above various display devices, a transparent electrode typified by an indium tin oxide electrode and a conductive electrode for wiring are often used. The construction of such a thin film circuit is an important factor that directly affects the quality of the display device, power consumption, and product cost, and such structural improvement is increasingly required in the present state. For the construction of this thin film circuit, a liquid crystal display (LCD) is taken as an example, and the matters desired to be improved will be specifically described below. A liquid crystal display (LCD) having a tendency to occupy the center of the display device has a high-definition and low-cost waking-up. Therefore, a thin film circuit of a thin film transistor is widely used. Moreover, Ming alloy was used as the wiring material for this film 2169-6972-PF 5 1298351 circuit. In the thin film circuit such as a thin film transistor, when an electrode layer for forming a wiring or an electrode is formed, an aluminum alloy film is often used. This is because the button, chromium, titanium, and alloy thereof are conventionally used. Since the specific resistance of the melting point material is high, etc., it is a substitute for a material having a lower specific resistance and easier wiring processing, which is a remarkable result. However, in the case where the electrode layer (aluminum alloy electrode layer) is formed of the aluminum alloy film, the following phenomenon is known to occur in the contact portion of the transparent electrode of the indium tin oxide electrode layer or the like in the liquid crystal display. When the aluminum alloy electrode layer is directly bonded to the indium tin oxide electrode layer, due to the difference in electrochemical characteristics of the two layers, an electrochemical reaction occurs on the bonding interface of the two layers, thereby causing damage of the bonding interface or The increase in impedance value. For this reason, when an aluminum alloy electrode layer is used for a liquid crystal display element, it is necessary to form a so-called cap layer (or a contact barrier layer) formed of molybdenum or chromium, etc. When the term "cover layer" is used below, the contact block is included. The meaning of the layer). (For example, refer to Non-Patent Document 1) [Non-Patent Document 1] edited by Uchida Natsuo, "Next Generation Liquid Crystal Display Technology", First Edition, Industrial Investigation Association Co., Ltd., November 1994 i 曰, page 36 to 38 A thin film transistor having an aluminum alloy electrode layer therein must be provided with a cap layer mainly composed of molybdenum, chromium or the like. In the case where an aluminum alloy film is used in the thin film transistor constituent material, since the cap layer is inevitably required to be formed, the laminated structure is complicated, resulting in an increase in production cost. Moreover, recently, among the materials constituting the cap layer, there has been a market trend to exclude the use of chromium, and the technique for forming a ruthenium layer has begun to impose a large limitation. 2169-6972-PF 6 1298351 • However, in the recent thin film transistor manufacturing technology, there is also a manufacturing technique that advocates the elimination of the above cap layer. For example, in Patent Document 1, a hypothetical aluminum wiring film which can be directly bonded to an indium tin oxide electrode layer and a sputtering target relating thereto are disclosed. In Patent Document 1, an aluminum wiring film contains a predetermined amount of an element for forming an aluminum and an intermetallic compound or an element having a standard electrode potential higher than aluminum, carbon, oxygen, nitrogen, hydrogen, etc. in aluminum. The result of the layer omission. [Patent Document 1] International Publication No. WO97/1 3885 No. 'Patent Document 2 discloses a display device using an aluminum alloy film and a manufacturing technique thereof, which can directly contact an aluminum alloy film with a transparent electrode film, and The barrier metal can be omitted. This Patent Document 2 is a part or all of the alloy components constituting the aluminum alloy film, and is present as a precipitate or a concentrated layer on the interface where the aluminum alloy film is in direct contact with the halogen electrode, thereby saving/slightly blocking the metal. (cover layer). [Patent Document 2] Japanese Patent Laid-Open No. 20 04-214606. This prior art, substantially the majority of the exemplified aluminum alloys, focuses on alloying elements or precipitates (for example, intermetallic compounds) in the alloy, and The possibility of joining. [Problems to be Solved by the Invention] However, 'there are various kinds of compositions of aluminum alloys or precipitates (intermetallic compounds) in aluminum alloys', which are known from the above-mentioned patent document 1 or above In Patent Document 2, it is difficult to confirm the estimation that the presence of various alloying elements or intermetallic compounds contributes to direct bonding. That is, in such prior art, the alloying elements or precipitates in the aluminum alloy are based on what kind of 2169-6972-PF 7 1298351 to thereby suppress the interfacial reaction at the time of direct bonding, and this phenomenon is not particularly shown. Description. For this purpose, the development of a liquid crystal display element which may omit the cap layer is not specifically indicated as to how to suppress the interface reaction of the direct bonding. Therefore, it is now necessary to inspect an aluminum alloy which proves various compositions. Furthermore, the composition of the alloy for suppressing the interfacial reaction also needs to be full of all the characteristics of the liquid crystal display device, that is, the so-called ohmic junction current-voltage characteristics, joint resistance, wiring resistance, heat resistance, and the like. In order to obtain a practical structure of a liquid crystal display element, the reality is still difficult. Further, in the liquid crystal display device, the bonding structure which can be directly bonded is also required in the thin film circuits such as other organic light emitting diodes (0ELD) or passive matrix type organic light emitting diodes. . - The present invention provides a bonding structure of a thin film circuit in the case of the above-mentioned matter. In a thin film circuit having a transparent electrode layer and an alloy electrode layer, not only the cap layer but also an interface reaction can be omitted. It is also possible to bond ohmically and also has better bonding characteristics. Further, a practical and highly suitable bonding structure of a thin film circuit is provided, and when the thin film circuit is used for a liquid crystal display element, it can be directly bonded to a transparent electrode layer represented by indium tin oxide, or can be surely achieved. The interface reaction is suppressed, and all liquid crystal display element characteristics such as ohmic junction characteristics, low bonding resistance, wiring film resistance, and heat resistance are satisfied. [Means to solve the problem]

為了解決上述問題,本發明者對透明電極直接接合於 種種' 口金上時之界面反應現象進行深入研究的結果發 2169-6972-PF 8 1298351 =,在直接接合的接合界面上,存在有具既定的 電位之析出物時’發現可抑制直接接合的界面反應且也: 以有歐姆接合的現象,進而想到本發明。 μ 可 本發明之薄膜電路之接合構造,具有透 與前述透明電極層直接接合的 = 夕垃入祕I从 电位續,此薄膜電路 -&特徵係為於鋁合金電極層中分散有具—"伏 至-0. 6伏特範圍内之氧化還原電位的析出物。 、 由本發明者的研究發現,於銘合金電極層中,存在且 二近Π透明?極㈣化還原電位值的電位,亦即所謂 曰程度的乳化還原電位的析出物,藉此析出物可以抑 |、月電極層與銘合金電極層之間的電化學反應,也不會 起接合界面上的破壞現象及阻抗增加等情形, ς =:Γ。還有,此「氧化還原電位」可謂在反應物 、原反應中,其氧化速度與還原速度相等平衡之際 的電位,亦即所謂之平衡電位。 不 人析出物的氧化還原電位為低於一 12伏特的電位值時, f口界面上會有產生破壞現象的傾向’而氧化還原電位為 门於〇· 6伏特的電位值時,則會有提高鋁合金電極層本身 阻抗值的傾向。具有—1· 2伏特至-0.6伏特之範圍内的氧化 還原電位的析出物,可以確實地抑制界面反應,代表的實 U為3有銘的金屬間化合物。含有銘的金屬間化合物例如 是鎳(Ni)、鈷(Co)、鐵(Fe)、鈥(M)、紀(γ)、鈀(pd)等元 素與鋁的金屬間化合物,具體而言,較佳是鎳化鋁 (Al3Nl)、姑化銘(Al9C〇2)、鐵化紹(AhFe)、鈥鎳化鋁In order to solve the above problems, the inventors of the present invention conducted intensive studies on the phenomenon of interface reaction when a transparent electrode is directly bonded to various kinds of gold. 2169-6972-PF 8 1298351 =, at the joint interface of direct bonding, there is a predetermined In the case of the precipitate of the potential, it was found that the interface reaction of the direct bonding can be suppressed and also the phenomenon of ohmic bonding is considered. μ The bonding structure of the thin film circuit of the present invention has a transparent connection with the transparent electrode layer, and the thin film circuit is characterized by being dispersed in the aluminum alloy electrode layer. "Precipitate of the redox potential in the range of -0.6 volts. According to the research of the present inventors, in the electrode layer of Yuming alloy, there is two transparent layers. The potential of the polar (four) reduction potential value, that is, the precipitate of the emulsified reduction potential of the so-called enthalpy, whereby the precipitate can suppress the electrochemical reaction between the moon electrode layer and the electrode layer of the alloy, and does not cause bonding. The damage phenomenon on the interface and the increase in impedance, etc., ς =:Γ. Further, the "oxidation-reduction potential" is a potential at which the oxidation rate and the reduction rate are equal in equilibrium in the reactants and the original reaction, that is, the so-called equilibrium potential. When the oxidation-reduction potential of a non-human precipitate is less than a potential value of 12 volts, there is a tendency for destruction at the interface of the f-portion, and when the oxidation-reduction potential is a potential value of 〇·6 volts, there is The tendency to increase the resistance value of the aluminum alloy electrode layer itself. The precipitate having an oxidation-reduction potential in the range of -1. 2 volts to -0.6 volts can surely suppress the interfacial reaction, and the representative U is an intermetallic compound of the same name. The intermetallic compound containing the mark is, for example, an intermetallic compound of an element such as nickel (Ni), cobalt (Co), iron (Fe), yttrium (M), gamma (p), palladium (pd) and aluminum, specifically, Preferred are nickel aluminum (Al3Nl), Gu Huaming (Al9C〇2), iron oxide (AhFe), niobium aluminum nitride

2169-6972-PF 9 1298351 絶化銘(ALPd)、紀化 (Al7NdNi2)、始錄化銘(Al4C〇iNii) 鋁(Α13γ!) 〇 J!,本發明的薄膜電路之接合構造較佳是紹合金電 二、’昆合電位為十4伏特至_〇. 6伏特。此混合電位 鋁合金電極層全體的電位,也 ’…、 ^ 也T M疋合有析出物狀態的鋁 ;電極層的電位’其中上述的氧化還原電位與測量法均 此混合電位為低於-U伏特的電位值時,在用以形 膜電路亦即所謂的圖案形成製財,進行顯影處理之 際,使用驗性顯影液等,會產生因發生電化學反應而致透 明電極層的變色等不適合的情形。還有,此混合電位為高 伏特的電位值時,則會增加銘合金電極層中的析出 量、鋁合金電極層中產生高電位部分與低電位部分,在所 謂之圖案形成製程中’進行㈣處理之際也有溶解銘本 身,而難以形成電路的傾向。 —在本發明之薄膜電路之接合構造中,透明電極層係由 3銦系氧化物的膜所構成,較佳是前述透明電極與鋁合金 電極層的接合阻抗值係為1歐姆/□ 10微米至200歐姆/匚]10 U米在接合阻抗值超過2 0 0歐姆/□ 1 〇微米時,會導致液 晶顯示元件的實用性消失。含有此銦系氧化物的膜係為所 谓的氧化鋼系透明電極(銦錫氧化物膜(Indium Tin 〇Xlde))、鋼辞氧化物膜(Indium Zinc Oxide))。還有,此 接合阻抗值係量測構成所謂的開爾文(ke丨v i n)元件的接合 阻抗值’在本發明中所規定的接合阻抗值係為量測丨〇微米 角之接觸面的值。 2169-6972-PF 10 1298351 另外,本發明之薄膜電路之接合構造中,鋁合金電極 層在攝氏300度、1小時熱處理後的比阻抗值較佳為3. 5微歐 姆公分至35微歐姆公分。還有,鋁合金電極層在攝氏3〇〇 度、1小時熱處理後的铭合金電極層表面上,形成有漣漪的 發生率較佳為百分之3. 〇以下。設比阻抗值超過35微歐姆公 分時,無法形成實用的薄膜電路。比阻抗值較佳為丨〇微歐 姆a为以下’更佳為5. 0微歐姆公分以下。還有,漣漪係指 形成於熱處理後之紹合金電極層表面的窪狀缺陷,此係與 小丘之突起相反,因體積收縮而產生。而且,漣漪的發生 率係藉由以掃瞄式電子顯微鏡(SEM : 1萬倍)觀察熱處理 後之鋁合金電極層表面,測量此表面上所觀察到的窪狀部 位的面積,並計算出窪狀部位之面積佔此觀察之全體視野 面積的比例而得。設此漣漪的發生率超過百分之3· 〇時,會 _ 有無法實現與透明電極層直接接合之際之良好接合狀態^ 傾向。 上述本發明之液晶顯示元件的接合構造中,鋁合金電 極層較佳疋含有0.5 at%至25 at%的鎳’也可以含有〇. i 至7.0 at%的鈷及/或鐵《而且,前述鋁合金電極層也可以 進一步包含0.1 at%至3.0 at%的钕。此種元素可藉由存在 於銘合金電極層中具有上述含銘之金屬間化合物B的析出 物,以抑制界面反應,而確實實現紹合 極層與透明電 極層間的直接接合。 含有錄的銘合金電極層中,錐合旦 』▼ 里不足0.5 at%之際, 析出物量會減少’無法完全達到界面 夂應的抑制。而鎳含2169-6972-PF 9 1298351 Extinct Ming (ALPd), Kehua (Al7NdNi2), Shilu Huaming (Al4C〇iNii) Aluminum (Α13γ!) 〇J!, the bonding structure of the thin film circuit of the present invention is preferably Alloy electric 2, 'Kunhe potential is 10 4 volts to _ 〇 6 volts. The potential of the entire mixed potential aluminum alloy electrode layer is also '..., ^ is also TM combined with the aluminum in the precipitate state; the potential of the electrode layer 'where the above-mentioned redox potential and the measurement method are both lower than -U When the potential value of the volt is used, when the development process is performed by using a so-called pattern forming method for forming a film circuit, an in-progress developing solution or the like is used, and discoloration of the transparent electrode layer due to an electrochemical reaction occurs, which is unsuitable. The situation. Further, when the mixed potential is a potential value of high volts, the amount of precipitation in the electrode layer of the alloy is increased, and a high potential portion and a low potential portion are generated in the aluminum alloy electrode layer, and the process is performed in a so-called pattern forming process (4). At the time of processing, there is also a tendency to dissolve the name itself, and it is difficult to form a circuit. In the bonded structure of the thin film circuit of the present invention, the transparent electrode layer is composed of a film of 3 indium oxide, and preferably the bonding resistance value of the transparent electrode and the aluminum alloy electrode layer is 1 ohm/□ 10 μm. When the bonding resistance value exceeds 200 ohms/□ 1 〇 micron to 200 ohms/匚] 10 U meters, the practicality of the liquid crystal display element disappears. The film containing the indium-based oxide is a so-called oxidized steel-based transparent electrode (Indium Tin Oxide film) or an indium Zinc Oxide film. Further, the joint impedance value is measured to constitute a joint impedance value of a so-called Kelvin element. The joint impedance value defined in the present invention is a value of the contact surface of the 丨〇 micron angle. 2微米之间的范围内的范围内的范围内的范围内的范围内的范围内的范围内的范围内的范围内的范围内的范围内的范围内。 The thickness of the aluminum alloy electrode layer is preferably 3. 5 micro ohm centimeters to 35 micro ohms centimeters after heat treatment at 300 degrees Celsius, 1 hour heat treatment. . Further, the aluminum alloy electrode layer has a cerium formation rate of preferably 3.3% or less on the surface of the alloy electrode layer after heat treatment at 3 ° C for 1 hour. When the specific impedance value exceeds 35 micro ohms, a practical thin film circuit cannot be formed. The specific resistance value is preferably 丨〇 micro ohm a is below ‘more preferably 5. 0 micro ohm centimeter or less. Further, lanthanum refers to a ruthenium-like defect formed on the surface of the electrode layer of the alloy after heat treatment, which is caused by volume shrinkage as opposed to the protrusion of the hillock. Further, the incidence of ruthenium was observed by scanning a scanning electron microscope (SEM: 10,000 times) to observe the surface of the aluminum alloy electrode layer after heat treatment, and the area of the ruthenium-like portion observed on the surface was measured, and 洼 was calculated. The area of the shaped portion is obtained as a ratio of the total field of view of the observation. If the incidence of ruthenium is more than 3 % ,, there is a tendency that a good bonding state can be achieved when the transparent electrode layer is not directly bonded. In the above-described bonding structure of the liquid crystal display device of the present invention, the aluminum alloy electrode layer preferably contains 0.5 at% to 25 at% of nickel', and may also contain 〇.i to 7.0 at% of cobalt and/or iron. The aluminum alloy electrode layer may further contain 0.1 at% to 3.0 at% of ruthenium. Such an element can suppress the interfacial reaction by the presence of the above-mentioned precipitate containing the intermetallic compound B contained in the electrode layer of the alloy, and can realize the direct bonding between the electrode layer and the transparent electrode layer. In the case of the recorded alloy electrode layer, when the cone is less than 0.5 at%, the amount of precipitates is reduced, and the inhibition of the interface is not fully achieved. Nickel

2169-6972-PF 1298351 2超過25 at%時,接線阻抗值會過大,無法得到實用的接 $構造。還有’祕或鐵而言,與鎳相同,在姑或鐵的含 里不足1 at%時,析出物量會減少,無法完全達到界面反應 的抑制’而姑或鐵的含量超過7.Gat%時,接線阻抗值會過 大二t法成為實用的構造。還有’在更包含有鈥的情形下, 鉞3里不足G. i㈣時,會有發生漣騎的傾向,而敍含量超 過=Oat%時,則會在鋁合金電極層與透明電極層直接接合 之際,有降低兩者間之接合耐久性的傾向。 還有,本發明之液晶顯示元件的接合構造中,鋁合金 電極層也可以含有°,1 at%至3.〇 at%的碳。此碳元素具有 防止小丘或漣漪的發生以及提高耐熱特性的作用。再者, =發明者的研究中,含有碳元㈣,推定具有可以發揮 提尚紹合金電極中析出物的界面反應抑制效果的作用。此 碳含量不at%時’會有使漣漪的發生變容易的傾向, 而碳含量超過3.0 at%時,則會有增純合金電極層之 抗值的傾向。 一在本發明的薄媒電路之接合構造中,薄膜電路為液晶 ’、》員示元件透明電極層為銦錫氧化物電極層時,析出物 較佳是氧化還原電位為透明電極層之氧化還原電位值+ 〇_.2伏特範圍内的銘系金屬間化合物。如此所構成之液晶顯 丁几件不僅可以省略習知液晶顯示元件中所採用的蓋 層,也可以不產生界面反應及實現歐姆接合。 還有,液晶顯示元件採用本發明之際,作為析出 銘系金屬間化合物較佳是録化紹(AhNi)。接著,此紹系金 2169-6972-PF 12 1298351 還有,形成各電極層時的薄膜形成,係於輸入電力為 3·0瓦/平方公*(Watt/cm2)、氬氣流量為1〇〇立方公分/分 鐘(ccm)、氬氣壓力為〇· 5帕(pa)等條件下,利用磁電管· 濺鍍裝置進行。 首先,先以本發明用作液晶顯示元件之接合構造為例 、/亍說月第1圖至第3圖,係關於钢錫氧化物電極層與實 施例1之鋁合金電極層的接合構造,並用以說明此接合部的 觀察結果。第1圖所示係為利用穿透式電子顯微鏡觀察實施 例1之鋁合金電極層與矽層間接合部剖面的照片。第2圖及 第3圖係為利用穿透式電子顯微鏡觀察實施例之鋁合金電 極層與銦錫氧化物電極層間接合部剖面的照片。 請參照第1圖,在η型矽基板(照片中,下半部分之黑 色部分)表面上層積ρ型非晶矽層(照片中,在中央部分中 約80奈米厚的白色部分),再於此0型非晶矽層表面上形成 實施例1的鋁合金電極層(照片中,上半部分約2〇〇奈米厚 的部分)以得到試樣,之後進行溫度為攝氏25〇度、'丨小時 的熱處理,並以聚焦離子束(FIB)對欲觀察的試樣剖面進行 加工,再以穿透式電子顯微鏡(倍率為1〇萬倍)進行觀察而 得第1圖所示之照片。還有,藉由對剖面之多個電子束回折 影像,以對特定部分之組織確認結晶構造。藉由第丨圖的剖 面觀察,可以明確判斷出進行將實施例丨之鋁合金電極層接 合於石夕層上之熱處理後,於鋁合金電極層和矽層間的^面 上,會析出鎳化鋁(照片中標號4的部分)金屬間化合物。 請參照第2圖,在銦錫氧化物(氧化錮(In2〇d —1〇重量 2169-6972-PF 14 1298351 百分比(wt%)的氧化錫(SnO2))電極層(照片中,中央下側 約150奈米厚之略黑色部分)表面上形成實施例丨之鋁合金 電極層(照片中,中央上側約2〇〇奈米厚的略白色部分)以 得到試樣,之後進行溫度為攝氏3〇〇度、丨小時的熱處理, 並以聚焦離子束對欲觀察的試樣剖面進行加工,再以穿透 式電子顯微鏡(倍率為10萬倍)進行觀察而得第2圖所示之 照片。第3圖係為放大(倍率為1 〇 〇萬倍)第2圖之接合部界面 的…、片由弟3圖之放大照片可知,銦錫氧化物電極層側(照 片中,下側黑色部分)與鋁合金電極層側(照片中,下側 白色邛刀)之間癌認有結塊狀析出物。此析出物可明確判 斷出是第1圖所確認之鎳化鋁金屬間化合物。 由第1圖至第3圖的觀察結果可明確判斷出本實施例1 之銘合金電極層直接接合於銦錫氧化物電極層上,且經之 後的熱處理而於界面析出約1 〇奈米至1 5 〇奈米粒徑的鎳化 銘金屬間化合物(第1圖中標號4 )。還有,由第3圖的放大 觀察可知,在本實施例1之鋁合金電極層與銦錫氧化物電極 層間的接合界面析出鎳化鋁金屬間化合物的附近,呈擴散 接合狀怨的部分為約3奈米至2 0奈米厚的層狀擴散部分。 接著,關於本實施例1與比較例1的鋁合金電極層而 έ ’對調查兩者與銦錫氧化物電極層接合時的電流—電壓特 性結果進行說明。此接合耐久測試係作成第4圖所示之测試 試樣而進行的。測試試樣係為被稱為所謂之開爾文元件結 構,第4圖係在銦錫氧化物(氧化銦—丨〇重量百分比的氧化 錫)電極層(〇· 2微米厚)上,形成垂直相交的鋁合金電極 2169-6972-PF 15 1298351 層(0.2微米厚),再從箭頭部分的端子部(1〇、4〇)通電 而得。此電流-電壓特性係在施加電壓於端子間之際,測量 流經端子間的電流而得。而且,接合部的面積係為1〇〇平方 微米(10微米X 10微米)。 第5圖及第6圖係表示在實施例丨及比較例丨之鋁合金電 極層與銦錫氧化物電極層上測量電流-電壓特性的結果。第 5圖係為實施例1的測量結果,第6圖係為比較例丨的測量結 果。還有,在各測量結果圖巾,實㈣為未熱處理(濺鑛 後)的情形,虛線是指施加攝氏25〇度、i小時熱處理的情 形。 由第5圖可知,在實施例丨的鋁合金電極層之情形下, 確認無論有無熱處理,電流一電壓特性均有線形關係。由此 可知,本實施例1之鋁合金電極層與銦錫氧化物電極層可以 實現歐姆接合。另一方面,由第6圖可知,比較例】的鋁合 金電極層在熱處理之際會產生非線性形狀的電流_電壓關 係。此係比較例1之鋁合金電極層與銦錫氧化物間的接合是 具有整流作用的構造,與預想之所謂的池•弗蘭克爾(ρ〇〇ι • Frankel)機構所說明之金屬-絕緣體_金屬結構(Μ"結 構:相同。亦即’在比較例i之鋁合金電極層的情形下,推 測藉由熱處理,會於比較例k鋁合金電極層與銦錫氧化物 間的接合界面上,形成氧化鋁的氧化皮膜。還有,在此所 示之電流-電壓特性,由於是在第4圖所示之二端子間(第4 圖中標號10、4G) 4測電流及電壓,因而所得為形成垂直 相交之接合部份以外的接線部分(銘合金電極層與銦錫氧 2169-6972-PF 16 1298351 化物)上’含有接線阻抗狀態時的結果。2169-6972-PF 1298351 2 When the temperature exceeds 25 at%, the wiring resistance value will be too large to obtain a practical connection structure. In addition, as for the secret or iron, when it is less than 1 at% in the content of uranium or iron, the amount of precipitates will decrease, and the inhibition of the interfacial reaction will not be fully achieved, and the content of uranium or iron exceeds 7. Gat%. When the wiring impedance value is too large, the two-t method becomes a practical structure. Also, in the case where there is more 鈥, when 钺3 is less than G. i (four), there will be a tendency to ride, and when the content exceeds =Oat%, it will be directly in the aluminum alloy electrode layer and the transparent electrode layer. At the time of joining, there is a tendency to lower the joint durability between the two. Further, in the joint structure of the liquid crystal display element of the present invention, the aluminum alloy electrode layer may contain carbon in an amount of from 1 at% to 3. at%. This carbon element has the effect of preventing the occurrence of hillocks or ridges and improving heat resistance. Further, in the study by the inventors, the carbon element (4) was contained, and it was presumed that it had an effect of suppressing the interfacial reaction of the precipitate in the electrode of the Tishansau alloy. When the carbon content is not at%, the occurrence of ruthenium tends to be easy, and when the carbon content exceeds 3.0 at%, the resistance of the alloy electrode layer tends to be increased. In the bonding structure of the thin dielectric circuit of the present invention, when the thin film circuit is a liquid crystal, and the transparent electrode layer of the device is an indium tin oxide electrode layer, the precipitate is preferably a redox potential of the transparent electrode layer. Inductive intermetallic compounds in the range of potential values + 〇_.2 volts. The liquid crystal display thus constituted can not only omit the cap layer used in the conventional liquid crystal display element, but also can generate an ohmic junction without causing an interface reaction. Further, in the case where the liquid crystal display element is used in the present invention, it is preferable to use AhH as a precipitation-based intermetallic compound. Next, this is a gold 2169-6972-PF 12 1298351. The film formation is performed when each electrode layer is formed, and the input electric power is 3·0 watt/square ** (Watt/cm 2 ), and the argon flow rate is 1 〇. In the case of 〇 cubic centimeters per minute (ccm) and argon pressure of 〇·5 Pa (pa), it is carried out using a magnetron/sputtering device. First, the joint structure of the liquid crystal display element of the present invention is taken as an example, and the first to third figures of the present invention relate to the joint structure of the steel tin oxide electrode layer and the aluminum alloy electrode layer of the first embodiment. And used to explain the observation results of this joint. Fig. 1 is a photograph showing a cross section of the joint between the aluminum alloy electrode layer and the tantalum layer of Example 1 by a transmission electron microscope. Fig. 2 and Fig. 3 are photographs showing a cross section of the joint between the aluminum alloy electrode layer and the indium tin oxide electrode layer of the example by a transmission electron microscope. Referring to Fig. 1, a p-type amorphous germanium layer is laminated on the surface of the n-type germanium substrate (the black portion of the lower half of the photograph) (in the photograph, a white portion of about 80 nm thick in the central portion), and then On the surface of the 0-type amorphous germanium layer, the aluminum alloy electrode layer of Example 1 (in the photograph, the upper half is about 2 nm thick) is obtained to obtain a sample, and then the temperature is 25 degrees Celsius. 'Hour-hour heat treatment, and the sample to be observed is processed with a focused ion beam (FIB), and then observed by a transmission electron microscope (magnification: 1 million times) to obtain a photograph shown in Fig. 1. . Further, by reversing the image of a plurality of electron beams of the cross section, the crystal structure is confirmed for the structure of the specific portion. By the cross-sectional observation of the second drawing, it can be clearly determined that after the heat treatment of bonding the aluminum alloy electrode layer of the embodiment 于 to the shihua layer, nickel plating is precipitated on the surface between the aluminum alloy electrode layer and the ruthenium layer. Aluminum (part of the number 4 in the photograph) intermetallic compound. Please refer to Figure 2, in the indium tin oxide (In2〇d - 1 〇 weight 2169-6972-PF 14 1298351% (wt%) tin oxide (SnO2)) electrode layer (photograph, the lower side of the center Approximately 150 nm thick black portion) The aluminum alloy electrode layer of Example ( was formed on the surface (in the photograph, the upper side of the center was about 2 〇〇 nanometer thick and slightly white portion) to obtain a sample, and then the temperature was 3 ° C. The heat treatment of the twist and the hour was performed, and the cross section of the sample to be observed was processed by a focused ion beam, and then observed by a transmission electron microscope (magnification: 100,000 times) to obtain a photograph shown in Fig. 2 . Fig. 3 is an enlargement (magnification of 1 million times) of the interface of the joint portion of Fig. 2, and the sheet is shown by the enlarged photograph of the figure of the brother 3, the side of the indium tin oxide electrode layer (in the photo, the black portion on the lower side) In the case of the aluminum alloy electrode layer side (in the photograph, the lower side white trowel), agglomerated precipitates are observed in the cancer. The precipitate can be clearly identified as the nickel-aluminum intermetallic compound confirmed in Fig. 1. The observation results of FIGS. 1 to 3 can clearly determine the present embodiment. 1 The alloy electrode layer is directly bonded to the indium tin oxide electrode layer, and after the subsequent heat treatment, a nickel-plated intermetallic compound having a particle size of about 1 〇 nanometer to 15 〇 nanometer is deposited at the interface (Fig. 1 Further, as shown in the enlarged view of Fig. 3, it is understood that the vicinity of the nickel-aluminum intermetallic compound is deposited at the joint interface between the aluminum alloy electrode layer and the indium tin oxide electrode layer of the first embodiment, and diffusion bonding is performed. The portion of the complaint is a layered diffusion portion of about 3 nm to 20 nm thick. Next, regarding the aluminum alloy electrode layers of the first embodiment and the comparative example 1, the pair of indium tin oxide electrodes were investigated. The result of the current-voltage characteristic at the time of layer bonding is described. This bonding endurance test is performed by preparing the test sample shown in Fig. 4. The test sample is called a so-called Kelvin element structure, and the fourth figure is On the indium tin oxide (indium oxide-niobium weight percent tin oxide) electrode layer (〇·2 μm thick), a vertically intersecting aluminum alloy electrode 2169-6972-PF 15 1298351 layer (0.2 μm thick) is formed, and then Terminal part from the arrow part (1 (4 〇) is obtained by energization. This current-voltage characteristic is obtained by measuring the current flowing between the terminals when a voltage is applied between the terminals. Moreover, the area of the joint portion is 1 〇〇 square micrometer (10 μm X). 10 μm) Fig. 5 and Fig. 6 show the results of measuring current-voltage characteristics on the aluminum alloy electrode layer and the indium tin oxide electrode layer of the examples and comparative examples. Fig. 5 is a first embodiment. The measurement results, Fig. 6 is the measurement result of the comparative example. Also, in the case of the measurement results, the actual (4) is the case of no heat treatment (after splashing), and the dotted line means 25 degrees Celsius, i hour. In the case of heat treatment, it can be seen from Fig. 5 that in the case of the aluminum alloy electrode layer of Example ,, it was confirmed that the current-voltage characteristics have a linear relationship regardless of the presence or absence of heat treatment. From this, it is understood that the aluminum alloy electrode layer of the first embodiment and the indium tin oxide electrode layer can be ohmically bonded. On the other hand, as can be seen from Fig. 6, the aluminum alloy electrode layer of the comparative example produced a current-voltage relationship of a nonlinear shape during heat treatment. The joint between the aluminum alloy electrode layer of Comparative Example 1 and indium tin oxide is a rectifying structure, and the metal-insulator described by the so-called pool•Frankel (Frankel) mechanism. The metal structure (Μ "structure: the same. That is, in the case of the aluminum alloy electrode layer of Comparative Example i, it is presumed that by heat treatment, it will be at the joint interface between the aluminum alloy electrode layer of the comparative example k and the indium tin oxide. An oxide film of aluminum oxide is formed. Further, the current-voltage characteristic shown here is obtained by measuring current and voltage between the two terminals shown in Fig. 4 (reference numerals 10 and 4G in Fig. 4). The result of the wire-impedance state on the wiring portion (the alloy electrode layer and the indium tin oxide 2169-6972-PF 16 1298351 compound) other than the joint portion where the perpendicular intersection is formed.

、接著,對進行與銦錫氧化物電極的接合耐久測試的結 ”進行次明。此接合耐久測試係以作成上述所說明之第4 圖斤不的測试試樣進行測試。測試試樣與上述相同,係在 7錫^化物(氧化錮-10重量百分比的氧化錫)電極層(〇 2 ⑼米厚)上,形成垂直相交的鋁合金電極層(〇· 2微米厚), =則頭邛分的端子部通電而進行。通電耐久特性係測量 /子間阻抗,並測篁此端子間阻抗變化終了的通電時間 =電極層係以實施例!、比較例!以及習知實例等3種類 進仃,其中習知實例是在純鋁電極層與透明電極之間,形 成f層構成材料之-的鉻膜(〇· 〇5微米厚)而得的結構。 / —方法疋在測里裱境為大氣氣氛氣中進行,電流值為1 0 微女培=3¾安培等2種,接合部阻抗值為初始值倍的時 為可?而且,在通電時溫度為攝氏85度、攝氏1〇0 度、攝氏150度、攝氏2〇〇度及攝氏250度下進行。Then, the junction for performing the bonding endurance test with the indium tin oxide electrode is performed. This bonding endurance test is carried out by testing the test specimen prepared as the fourth figure described above. The same applies to the formation of a vertically intersecting aluminum alloy electrode layer (〇·2 μm thick) on a 7-tin (yttria-10 wt% tin oxide) electrode layer (〇 2 (9) m thick), = then The terminal portion of the split is energized. The energization endurance characteristic is the measurement/inter-substrate impedance, and the energization time at which the impedance change between the terminals is completed = the electrode layer is in the embodiment!, the comparative example, and the conventional example. The conventional example is a structure obtained by forming a chromium film (〇·〇 5 μm thick) between the pure aluminum electrode layer and the transparent electrode, and forming a material of the f layer. The atmosphere is carried out in an atmospheric atmosphere, and the current value is 1 micro micro-peech = 33⁄4 ampere. The junction resistance value is equal to the initial value. Moreover, the temperature is 85 degrees Celsius and 1 Celsius at the time of energization. 0 degrees, 150 degrees Celsius, 2 degrees Celsius and photo Carried out at 250 degrees.

、弟7圖所不為,置測各溫度下產生接合部阻抗上昇(成 為初始值之1〇〇倍的時間點)的時間,並將通電時保持溫度 的倒數對其壽命時間而得之亞罕尼斯圖形。於第7圖中,縱 軸為哥命時間,橫軸為1〇〇〇/絕對溫度。從自此亞罕尼斯圖 料插而得之-次直線的傾斜度,計算出開始使接合部之 阻抗上昇的活化能,由此可明確判斷出實施例i之活化能為 5電,伏特、比較例!之活化能為〇· 電子伏特。由此結 可U知例1之銘合金電極層所具有之活化能約為比 乂例1的3· 3倍。還有,在實施例1之情形下,推測在攝氏85 2169-6972-PF 17 1298351 度:,可以具有約7萬小時的耐久性,此結果近似於習知實 例在電極層間有鉻膜的情形。 接著,對調查實施们紹合金電極層之小丘特性而得之 結果進行說明。藉由濺鍍 戮乃八進仃於晶圓基板上形成鋁合 金膜的接線加工後’在藉由化學氣相沈積法形成絕緣膜之 IV、在已接線加工的銘合金膜上加熱攝氏_度至攝氏糊 度’而在銘合金膜表面所產生的結塊狀突起即為小丘。自In the picture of the brother 7th, the time at which the impedance of the joint is increased at each temperature (the time point which is 1〇〇 times the initial value) is measured, and the reciprocal of the temperature at the time of energization is obtained. Hannis graphics. In Fig. 7, the vertical axis is the life time and the horizontal axis is 1 〇〇〇/absolute temperature. From the inclination of the secondary line inserted from the Yahannis material, the activation energy at which the impedance of the joint portion is increased is calculated, and it can be clearly determined that the activation energy of the embodiment i is 5 volts, volt, Comparative example! The activation energy is 〇·electron volts. Thus, the activation energy of the alloy electrode layer of Example 1 is about 3.3 times that of Example 1. Further, in the case of the first embodiment, it is presumed that the temperature is 85 169-6972-PF 17 1298351 degrees: and may have a durability of about 70,000 hours, which is similar to the case where the conventional example has a chromium film between the electrode layers. . Next, the results obtained by investigating the hillock characteristics of the alloy electrode layer will be described. After the wiring of the aluminum alloy film is formed on the wafer substrate by sputtering, the IV of the insulating film is formed by chemical vapor deposition, and the Celsius film is heated on the gated alloy film. The agglomeration of the surface of the alloy film is the hillock. from

此,小丘可能是因熱處理而在銘合金膜上增加應力而發 生。為此,將純铭電極層與實施例k銘合金電極層分別形 成於矽晶圓基板上,於加熱之際,調查電極層上所產生之 應力所發生的變化。具體而言,在半徑100毫米的矽晶圓基 板上,藉由濺鍍方式層積〇· 2微米厚的電極層以作成試樣。Therefore, the hillock may be caused by an increase in stress on the alloy film due to heat treatment. To this end, the pure electrode layer and the electrode layer of the example k-shaped alloy were formed on the germanium wafer substrate, and the change in the stress generated on the electrode layer was investigated while heating. Specifically, on a tantalum wafer substrate having a radius of 100 mm, an electrode layer of 2 μm thick was laminated by sputtering to prepare a sample.

而且,利用雷射式應力量測裝置FLX —2320 (科磊(KLA TENCOR)公司製:氮氣氣流為(5升/分鐘(1/min))、固體 雷射為670奈米),以雷射測量電極層所產生之應力。此測 里結果如第8圖所示。 第8圖是從室溫昇溫至攝氏5〇〇度,接著從攝氏5〇〇度降 λ至攝氏1 〇 〇度之際的各溫度下所測得之電極層應力狀態 的結果(昇溫速度、降溫速度為攝氏5度/分鐘)。負的應 力值係表示施加壓縮應力的狀態,正的應力值係表示施加 拉伸應力的狀態。粗線係表示實施例1,細線係表示純鋁。 由純鋁的應力狀態可明顯得知,從昇溫時的攝氏1 8 〇度開始 至攝氏40 0度左右為止,連續為-100百萬帕的應力值,此係 表示純鋁電極層被施加壓縮應力時,會發生產生小丘以緩 18Moreover, a laser-type stress measuring device FLX-2320 (manufactured by KLA TENCOR Co., Ltd.: nitrogen gas flow rate (5 liter / minute (1/min)), solid laser light of 670 nm), with a laser The stress generated by the electrode layer is measured. The results of this test are shown in Figure 8. Figure 8 is the result of measuring the stress state of the electrode layer at various temperatures from room temperature to 5 degrees Celsius, and then from λ to 5 degrees Celsius to 1 degree Celsius (temperature rise rate, The cooling rate is 5 degrees Celsius / minute). The negative stress value indicates a state in which a compressive stress is applied, and the positive stress value indicates a state in which a tensile stress is applied. The thick line indicates Example 1, and the thin line indicates pure aluminum. From the stress state of pure aluminum, it is apparent that the stress value of -100 MPa continuously from the temperature of 18 ° C to the temperature of 40 ° C, which means that the pure aluminum electrode layer is compressed. When stress occurs, it will happen to produce hillocks to slow down 18

2169-6972-PF 1298351 和此壓縮應力的現象。另一方面,在實施例鴻情形下,於 昇溫時的攝氏2。。度附近發現較大的負應力被緩和的狀 態’此係實施例1之紹合金電極層中析出鍊化紹金屬間化合 物之故。亦即,在實施例的情形下,相可以藉由析出: 化銘金屬間化合物,而在不發生小丘之情形下緩和施加於 銘合金電極層上的麗縮應力。 另外,對測量實施例卜比較例卜作為蓋層之構成材 料的鉻、翻、銦錫氧化物膜、鎳化鋁等的氧化還原電位而 得之結果進行說明。此氧化還原電位之測量係以濺鑛裝置 在玻璃基板上形成依據各組成而得之既定厚度為(〇/2微 米)的薄膜,再切割此玻璃基板而作為電位量‘ 且,遮蔽電位測量試樣表面,露出相當於心::二 積,而形成測量用電極。氧化還原電位係使用百分之3 5 的氯化鈉水溶液(液體溫度為攝氏27度),且參考7電極為 銀/氯化銀的情形下進行測量。冑有,銦錫氧化膜係使用氧 化銦-10重量百分比的氧化錫所組成之膜。其結果如表㈣ 示02169-6972-PF 1298351 and the phenomenon of this compressive stress. On the other hand, in the case of the embodiment, Celsius 2 at the time of temperature rise. . A large negative stress was found to be moderated in the vicinity of the degree. This is the reason why the intermetallic compound was precipitated in the electrode layer of the alloy of Example 1. That is, in the case of the embodiment, the phase can be relaxed by the precipitation: the intermetallic compound, and the stress applied to the electrode layer of the alloy is relaxed without occurrence of hillocks. Further, the results of measuring the oxidation-reduction potential of chromium, tumbling, indium tin oxide film, nickel aluminide or the like which are constituent materials of the cap layer in the comparative example of the measurement examples will be described. The oxidation-reduction potential is measured by forming a film having a predetermined thickness (〇/2 μm) according to each composition on a glass substrate by a sputtering apparatus, and then cutting the glass substrate as a potential amount 'and a masking potential measurement test. The surface of the sample is exposed to the equivalent of the heart: two, and the electrode for measurement is formed. The redox potential was measured using a 35% aqueous solution of sodium chloride (liquid temperature was 27 degrees Celsius), and the reference 7 electrode was silver/silver chloride. Further, the indium tin oxide film is a film composed of indium oxide - 10% by weight of tin oxide. The results are shown in Table (4).

0. 73 0. 78 鎳化銘(AhNi) i(Cr) m (M〇) 銦錫氧化物膜(ιτο膜) -〇· 51 一〇· 82 2169-6972-PF1-20051028 19 1298351 在表2中,實施例1之氧化還原電位 ^ ^ ^ W疋非常靠近銦 錫虱化物膜。還有金屬間化合物鎳化鋁 〜半L化還原電位 值’也明確散具有與鉻相同之非常#近_氧化物膜之 氧化還原電位值。 接著,對與錮錫氧化物電極層的接合阻抗評估進行說 明。第9圖係為所測得之各電極層分別與鋼_氧化物電極層 接合阻抗值的結果,與所求得之各電極層氧化還原電位: :銦錫氧化物氧化還原電位值的差值,所繪得的圖形。測 量方法係作成如第7圖所示之測試試樣,再測量無熱處理 (濺鍍後)、有熱處理(於攝氏2〇〇度、攝氏25〇度、攝氏3〇〇 度的各溫度下、1小時的退火後)的試樣之阻抗值。 接合阻抗值之測量係利用如第4圖所示之測試試樣所 進行,在銦錫氧化物(氧化銦,重量百分比的氧化錫)電 極層4〇 (〇· 2微米厚)上,形成交錯的電極層10 (0.2微米 厚),再從箭頭部分的端子部通電而測量阻抗,以算出膜重 璺部分(10微米X 1〇微米)的接合阻抗。電極層係以表^斤 示之實施例1及比較例丨以及純鋁膜與鉻膜層積而得之構造 等3種電極層進行測試。此層積構造的電極層係在〇· 〇3微米 鉻膜上形成〇· 2微米的純鋁膜。還有利用表2所示之氧化還 原電位值,算出銦錫氧化物與各電極層的電位差,此電位 差為橫軸,與所測得之各接合阻抗值一同繪圖(第9圖)。 由第9圖可知,在電極與銦錫氧化物之間有具與銦錫氧 化物之氧化還原電位幾乎同一標準之電位的鉻膜的電極 時’確遇接合阻抗非常低。在實施例1與比較例1之鋁合金 2169-6972-PF 20 1298351 電極層的情形下,與銦錫氧化物電位差差異不大的實施例1 接合阻抗較低’且確認比較例1之銘合金電極層在進行熱處 理後,此接合阻抗顯著變大。還有,上述接合阻抗之量測 雖以在銦錫氧化物電極層上形成鋁合金電極層之情形為 例’然也確認在鋁合金電極層上形成銦錫氧化物電極層的 顛倒構造可以得到相同接合阻抗特性。0. 73 0. 78 Nickel inscription (AhNi) i(Cr) m (M〇) Indium tin oxide film (ιτο膜) -〇· 51 一〇· 82 2169-6972-PF1-20051028 19 1298351 In Table 2 The oxidation-reduction potential of Example 1 ^ ^ ^ W疋 is very close to the indium tin halide film. Further, the intermetallic compound nickel aluminide 〜half-L reduction potential value ′ also clearly has the same oxidation-reduction potential value as the chromium film. Next, the evaluation of the bonding resistance with the antimony tin oxide electrode layer will be described. Figure 9 is a graph showing the difference between the measured impedance values of the respective electrode layers and the steel-oxide electrode layer, and the difference between the measured oxidation-reduction potential of each electrode layer: the indium tin oxide oxidation-reduction potential value. , the painted figure. The measurement method is to prepare a test sample as shown in Fig. 7, and then to measure without heat treatment (after sputtering) and heat treatment (at various temperatures of 2 degrees Celsius, 25 degrees Celsius, 3 degrees Celsius, The impedance value of the sample after 1 hour of annealing. The measurement of the bonding resistance value was carried out by using the test sample as shown in Fig. 4, and the interplating was formed on the electrode layer 4 〇 (〇 2 μm thick) of indium tin oxide (indium oxide, weight percent tin oxide). The electrode layer 10 (0.2 μm thick) was further energized from the terminal portion of the arrow portion to measure the impedance to calculate the junction resistance of the film overlap portion (10 μm X 1 μm). The electrode layer was tested in three types of electrode layers, such as Example 1 and Comparative Example, and a structure in which a pure aluminum film and a chromium film were laminated. The electrode layer of this laminated structure was formed on a 〇·〇3 μm chromium film to form a 2 μm pure aluminum film. Further, using the oxidation reduction potential value shown in Table 2, the potential difference between the indium tin oxide and each electrode layer was calculated, and this potential difference was plotted on the horizontal axis, together with the measured joint resistance values (Fig. 9). As is apparent from Fig. 9, when an electrode having a chromium film having a potential equal to the same standard as the oxidation-reduction potential of indium tin oxide is present between the electrode and the indium tin oxide, the bonding resistance is extremely low. In the case of the electrode layers of the aluminum alloy 2169-6972-PF 20 1298351 of Example 1 and Comparative Example 1, the bonding resistance of Example 1 which is not significantly different from the potential difference of indium tin oxide was lower, and the alloy of Comparative Example 1 was confirmed. After the electrode layer is subjected to heat treatment, the joint resistance is remarkably large. Further, although the measurement of the bonding resistance is performed by taking an aluminum alloy electrode layer on the indium tin oxide electrode layer as an example, it has been confirmed that the inverted structure in which the indium tin oxide electrode layer is formed on the aluminum alloy electrode layer can be obtained. Same joint impedance characteristics.

由以上結果可知,實施例1之鋁合金電極層,不僅本 身的氧化還原電位具有近似於銦錫氧化物之氧化還原電位 的值,而且與銦錫氧化物電極層直接接合之際的接合阻抗 也低,另外,藉由進行熱處理,於兩者接合界面上析出鎳 化鋁金屬間化合物,也可以實現較佳之接合特性。此理由 推測是由於鎳化鋁的氧化還原電位極為接近銦錫氧化物的 氧化還原電位,因此不會引起與銦錫氧化物的電化學反 應’進而不會引起接合部的破壞等。From the above results, it is understood that the aluminum alloy electrode layer of the first embodiment has not only the oxidation-reduction potential of itself but also the value of the oxidation-reduction potential of indium tin oxide, and the bonding resistance when directly bonded to the indium tin oxide electrode layer. It is also low, and by performing heat treatment, a nickel-aluminum intermetallic compound is deposited on the joint interface of the two, and preferable joining characteristics can be achieved. This reason is presumed to be because the oxidation-reduction potential of the aluminum aluminide is extremely close to the redox potential of the indium tin oxide, so that the electrochemical reaction with the indium tin oxide does not occur, and the joint portion is not broken.

自此,以與銦錫氧化物膜之透明電極直接接合的方式 形成鋁合金電極層之際,藉由可在銦錫氧化物電極層與鋁 合金電極層間的界面析出具與銦錫氧化物電極之氧化還原 電位值± 200毫伏特左右的氧化還原電位的銘系金屬間化 T物(鎳化鋁)的接合構造,可以實現較佳之接合特性。 逛有此銘系金屬間化合物(錄化幻平均粒徑為Μ奈米至 150奈米時,由界面所析出之鋁系金屬間化合物形成的接人 擴散層,推測厚度為3奈米至2〇奈米。 D 使用鎳、鈷、鐵、錢、 並對調查液晶顯示元 第二實施例:此第二實施例係以 碳,形成各種組成的鋁合金電極層, 2169-6972-PF 21 1298351 件特性之結果進行說明。表3中,係探討此第二實施例之鋁 •合金電極層組成。此表3所示之各合金膜係以與第一實施例 _ 所示之成膜條件相同的條件所形成。 表3 組成 析出物 析出物電位 混合電位 at% V V 實施例2 Al~0.3C-3.0Ni AlsNi - 0·73 -1. 02 實施例3 Al-0.5C-3.0Ni AMi -0· 73 -1.05 實施例4 Al-0.3C-5.0Ni AhNi -0.73 -1.01 實施例5 Al-l.0Nd-2.0Ni AhNdNiz - 0.92 -1· 05 實施例6 A 卜 0.2C-2.0Ni - 3.0C〇 AhCoiNii -0· 70 -0.93 實施例7 Al-3.0Ni AMi -0.73 -1.04 實施例8 Al-10Ni AMi -0.73 -0.86 實施例9 Al-25Ni AMi -0.73 -0.73 實施例10 Al-2.OFe AlsFe -1.08 -1.37 實施例11 A1-2.0C〇 AI9C02 -1.09 -1· 25 實施例12 A1 - Pd AhPd -0.94 -1· 10 實施例13 A1-4Y AhYi -0.70 -0· 86 比較例2 A1-2.0M AlnNda -1.53 -1.58 比較例3 純A1 一 — -1.68 比較例4 純Cr — 一 -0.78 表3中係顯示實施例2至實施例1 3、比較例2至實施例3 各組成之合金膜、此合金膜中的析出物、此析出物之氧化 還原電位以及此合金膜之混合電位等量測結果。電位測量Since the aluminum alloy electrode layer is formed by directly bonding to the transparent electrode of the indium tin oxide film, the interface between the indium tin oxide electrode layer and the aluminum alloy electrode layer can be deposited with the indium tin oxide electrode. The bonding structure of the metal-oxide T material (nickel-aluminum) having an oxidation-reduction potential value of about ±200 mV is excellent in bonding characteristics. Visiting the intermetallic compound (the interfacial diffusion layer formed by the aluminum-based intermetallic compound precipitated at the interface when the average particle size is from nanometer to 150 nm, the thickness is estimated to be 3 nm to 2 〇N. D uses nickel, cobalt, iron, money, and investigates liquid crystal display elements. Second embodiment: This second embodiment uses carbon to form aluminum alloy electrode layers of various compositions, 2169-6972-PF 21 1298351 The results of the characteristics of the members are explained. In Table 3, the composition of the aluminum alloy electrode layer of the second embodiment is discussed. The alloy films shown in Table 3 are the same as those of the first embodiment. Table 3 Composition Precipitate Precipitate Potential Mixing Potential at% VV Example 2 Al~0.3C-3.0Ni AlsNi - 0·73 -1. 02 Example 3 Al-0.5C-3.0Ni AMi -0 · 73 -1.05 Example 4 Al-0.3C-5.0Ni AhNi -0.73 -1.01 Example 5 Al-l.0Nd-2.0Ni AhNdNiz - 0.92 -1· 05 Example 6 A Bu 0.2C-2.0Ni - 3.0C 〇AhCoiNii -0·70 -0.93 Example 7 Al-3.0Ni AMi -0.73 -1.04 Example 8 Al-10Ni AMi -0.73 -0.86 Example 9 Al-25Ni AMi -0.73 -0.73 Example 10 Al-2.OFe AlsFe -1.08 -1.37 Example 11 A1-2.0C〇AI9C02 -1.09 -1· 25 Example 12 A1 - Pd AhPd -0.94 -1· 10 Example 13 A1-4Y AhYi -0.70 -0· 86 Comparative Example 2 A1-2.0M AlnNda -1.53 -1.58 Comparative Example 3 Pure A1 - - 1.68 Comparative Example 4 Pure Cr - One - 0.78 Table 3 shows Example 2 to Example 1 3. Comparative Example 2 to 3 The measurement results of the alloy film of each composition, the precipitate in the alloy film, the oxidation-reduction potential of the precipitate, and the mixed potential of the alloy film.

方法係相同於表2所說明的方法。 接著,對表3中之實施例2至實施例9、比較例2至實施 例3各組成之合金膜調查其比阻抗、耐熱性、漣漪特性的結 果如表4所示。 , 表4 2169-6972-PF1-20051028 22 1298351 比阻抗值 # Ω · cm 小丘耐熱性 °C 漣漪發生率 % 實施例2 3. 76 400 0 實施例3 4. 12 400 0 ~~ 實施例4 4. 02 400 0 實施例5 3. 43 400 0 實施例6 5. 46 530 0 實施例7 3. 74 400 0.8 0 實施例8 實施例9 10. 0 500 1.14 " 31. 6 500 2. 40 比較例2 4. 13 400 0 比較例3 3. 00 200 小丘發生 比較例4 13· 2 — 0 比阻抗值係為在玻璃基板上形成各合金膜的單膜(厚 度約〇· 3微米),於攝氏300度、時的熱處理後,以4端: 阻抗測量裝置測量熱處理後膜的結果。還有,々、丘耐熱性 係為在玻璃基板上形成各合金膜的單膜(厚度約〇 3微 米),分別於攝氏100度、攝氏2〇〇度、攝氏3〇〇度、攝氏 度的各溫度下進行1小時的熱處理後,再以㈣式電子顯微 鏡(SEM)觀察膜表面,確認有次微# (sub__以上之 突起物存在時的溫度’其結果如表4所示。還有,漣濟的發 生率係利用與比阻抗測量相同的試樣,於攝氏300度、!小 夺的,,,、々里後以掃猫式電子顯微鏡(〗萬倍)觀察膜表面, 特定表面上被觀察到窪狀部A (内徑為。· 3微米至。.5微 未)’並測量存在於觀察視野中之窪狀部分總面積,再計算 窪狀部分總面積佔令_,# 積王體視野面積的比例而得。而且,於表4 中,係顯示從各膜表面乂 s 相…的5處部位所算出之試樣發生率 2169-6972-PF1-20051028 23 ' 1298351 的平均值。 由表4可知,實施例2至實施例6的合金薄膜在不足攝氏 400度下沒有小丘的發生,也不會發生漣漪。但是,實施例 7至實施例9則確認有發生漣漪的傾向。此係因為實施例2 至實施例4、實施例6的組成中含有碳,實施例6之組成中更 含有鈥,因此可明確判斷出藉由碳、鈦可以防止小丘或漣 漪的發生。 - 更甚之,對表3中之實施例2至實施例9、比較例2至比 φ 較例3各組成的合金膜而言,調查各膜與銦錫氧化物電極層 直接接合時之電壓-電流特性、接合特性(接觸阻抗、接合 耐久性),結果如表5所示。還有,此第二實施例中調查接 合特性之試樣,為了有良好的接合狀態,因此在透明電極 - 層與各合金膜層直接接合後,會進行既定的熱處理(在惰 性氣體(氮氣、氬氣)氣氛氣中,攝氏300度,60分鐘)。The method is the same as that described in Table 2. Next, the results of investigating the specific resistance, heat resistance and enthalpy characteristics of the alloy films of the compositions of Examples 2 to 9 and Comparative Examples 2 to 3 in Table 3 are shown in Table 4. Table 4 2169-6972-PF1-20051028 22 1298351 Specific Impedance Value # Ω · cm Hillock Heat Resistance °C 涟漪 Incidence Rate % Example 2 3. 76 400 0 Example 3 4. 12 400 0 ~~ Example 4 4. 02 400 0 Example 5 3. 43 400 0 Example 6 5. 46 530 0 Example 7 3. 74 400 0.8 0 Example 8 Example 9 10. 0 500 1.14 " 31. 6 500 2. 40 Comparative Example 2 4. 13 400 0 Comparative Example 3 3. 00 200 Hillock occurrence Comparative Example 4 13· 2 - 0 The specific impedance value is a single film (thickness about 〇·3 μm) in which each alloy film is formed on a glass substrate. After heat treatment at 300 °C, the results of the film after heat treatment were measured by a 4-terminal: impedance measuring device. Further, the heat resistance of the dome and the hill is a single film (thickness of about 3 μm) in which each alloy film is formed on a glass substrate, and each of 100 degrees Celsius, 2 degrees Celsius, 3 degrees Celsius, and Celsius. After heat treatment at a temperature for 1 hour, the surface of the film was observed by a (IV) electron microscope (SEM), and it was confirmed that there was a sub-micro (the temperature at which the protrusions of sub__ or more were present). The results are shown in Table 4. The incidence of relief is based on the same sample as the specific impedance measurement, and the surface of the membrane is observed on a specific surface by a cat-type electron microscope (〖10,000 times) at 300 degrees Celsius, 小, 、, 々, 々 Obtained the beak A (inner diameter is ···3 micrometer to .5 micro-not)' and measure the total area of the braided part existing in the observation field, and then calculate the total area of the braided part to occupy _,# product The ratio of the field of view of the king's body is obtained. Moreover, in Table 4, the average value of the sample calculated from the five parts of the 乂s phase of each film is 2169-6972-PF1-20051028 23 ' 1298351 As can be seen from Table 4, the alloy films of Examples 2 to 6 are in less than Celsius. There was no occurrence of hillocks at 400 degrees, and no flaws occurred. However, Examples 7 to 9 confirmed the tendency to cause enthalpy. This is because the compositions of Examples 2 to 4 and Example 6 contained Carbon, the composition of Example 6 further contains ruthenium, so it can be clearly determined that the occurrence of hillocks or mites can be prevented by carbon or titanium. - Furthermore, comparison is made to Example 2 to Example 9 in Table 3 Example 2 to φ Compared with the alloy film of each of the compositions of Example 3, the voltage-current characteristics and the bonding characteristics (contact resistance and bonding durability) when the respective films were directly bonded to the indium tin oxide electrode layer were examined. The results are shown in Table 5. Further, in the second embodiment, in the sample in which the bonding characteristics were investigated, in order to have a good bonding state, after the transparent electrode layer was directly bonded to each alloy film layer, a predetermined heat treatment (in an inert gas) was performed. (Nitrogen, argon) atmosphere gas, 300 degrees Celsius, 60 minutes).

表5 接合特性1 接合ί 降性2 電流-電壓 特性 接合阻抗值 接合耐久性 接合阻抗值 接合耐久性 Ω(Π10/ζπι) Hour Ω(Π10//πι) Hour 實施例2 歐姆 50〜150 >250 50〜150 70000 實施例3 歐姆 50〜150 >250 50〜150 >250 實施例4 歐姆 50〜100 >250 50〜150 >250 實施例5 歐姆 50〜150 >250 50〜150 200 實施例6 歐姆 50〜150 >250 50〜150 >250 實施例7 歐姆 50〜150 >250 50〜150 >250 實施例8 歐姆 50〜150 >250 50〜150 >250 實施例9 歐姆 30 〜50 >250 30 〜50 >250 比較例2 二枝體 50〜150 2卜30 (21200) 1.5 比較例3 二極體 100〜200 10 (7020) 0.3 比較例4 歐姆 5〜10 >250 5〜10 >70000 2169-6972-PF1-20051028 24 1298351 表5所示之電流-電壓特性,係以相同於第一實施例之 ' 第5圖及第6圖所說明之方法進行測量,而作成各電流-電壓 ^ 特性圖,由此圖顯示是否會產生整流作用的判斷結果。 還有,接合特性之調查係以形成各合金膜,於此膜上 形成錮錫氧化物膜的情形為接合特性丨,而在銦錫氧化物電 極層上形成各合金膜之情形為接合特性2。而且,接合特性 之接合阻抗值係為形成與第一實施例之電流—電壓特性測 量相同的開爾文元件,於攝氏250度、i小時熱處理後,流 籲過3mA的電流,電壓發生激烈變化時點的接合阻抗值。還 有,用以進行接合特性1之測量的開爾文元件的製作,係先 藉由濺鍍方式於基板上形成合金膜,再蝕刻此合金膜以形 成直線線路。然後,在前述合金膜表面上形成非晶銦錫氧 化物膜,使用不會溶解底面合金膜直線電路的弱酸的草酸 -系姓刻液,以僅餘刻銦錫氧化物膜的方式,形成與底面合 金膜直線電路垂直相交的銦錫氧化物膜直線電路,而製作 得到試樣。 _ 接合耐久性係分別製作如第一實施例第γ圖所示之亞 罕尼斯圖形,在許可電流為3毫安培、1〇微安培下,從亞罕 尼斯圖之傾斜度,估計其活化能,而顯示攝氏85度的接合 耐久時間的結果(此接合耐久性測量係參考JIS_C—5〇〇3電 子元件故障率測試法、JIS-C-0021加熱測試法而進行)。 由表5之結果可知,實施例2之情形,實施例2之接合阻 抗值與鉻膜相較之下略高一些,然卻具有與用作蓋層之鉻 相同程度的接合特性。還有,實施例3、實施例4、實施例6 2169-6972-PF 25 ;1298351 至實施例9的情形,對於接合阻抗值及接合耐久值兩者而 '言,均具有可滿^實用上的特性。實施例5之情形,接合特 :14 接σ耐久a有良好的結果’判斷應是受形成此直接 接合構造的過程相異所影響。 第二Λ細例.此第三實施例係對調查實施例4 (鋁-0· 3 at%碳-5. 0 at%錄)的銘合金電極層接合阻抗特性與熱處理 間關係的結果進行說明。 . 接合阻抗的測量係以與上述第二實施例表5所說明之 馨接合特性1 (於銦錫氧化物膜上接合銘合金電極層)相同的 方式進打。但’第三實施例之用以測量接合阻抗值的測試 試樣,係在透明電極層(銦錫氧化物膜)與紹合金電極層 直接接合後,於惰性氣體(氮氣)氣氛氣中,於攝氏250 *度、攝氏3〇0度、攝氏350度等3個溫度下進行熱處理(60Table 5 Bonding characteristics 1 Bonding 脱 Degradation 2 Current-voltage characteristic Bonding resistance value Bonding durability Bonding resistance value Bonding durability Ω(Π10/ζπι) Hour Ω(Π10//πι) Hour Example 2 Ohm 50~150 > 250 50 to 150 70000 Example 3 Ohm 50 to 150 > 250 50 to 150 > 250 Example 4 Ohm 50 to 100 > 250 50 to 150 > 250 Example 5 Ohm 50 to 150 > 250 50 to 150 200 Example 6 Ohm 50 to 150 > 250 50 to 150 > 250 Example 7 Ohm 50 to 150 > 250 50 to 150 > 250 Example 8 Ohm 50 to 150 > 250 50 to 150 > 250 Implementation Example 9 Ohm 30 to 50 > 250 30 to 50 > 250 Comparative Example 2 Two-piece 50 to 150 2 Bu 30 (21200) 1.5 Comparative Example 3 Dipole 100 to 200 10 (7020) 0.3 Comparative Example 4 Ohm 5 〜10 >250 5~10 >70000 2169-6972-PF1-20051028 24 1298351 The current-voltage characteristics shown in Table 5 are the same as those described in the fifth and sixth figures of the first embodiment. The method performs measurement, and each current-voltage characteristic map is created, and the graph shows whether or not the result of the rectification effect is generated. Further, in the investigation of the bonding characteristics, in the case of forming each alloy film, the case where the antimony-tin oxide film is formed on the film is the bonding property 丨, and the case where the alloy film is formed on the indium-tin oxide electrode layer is the bonding property 2 . Further, the bonding resistance value of the bonding characteristics is such that the Kelvin element having the same current-voltage characteristic measurement as that of the first embodiment is formed, and after a heat treatment of 250 degrees Celsius and i hour, a current of 3 mA is flown, and the voltage is drastically changed. Bonding impedance value. Further, the Kelvin element for measuring the bonding property 1 is formed by first forming an alloy film on a substrate by sputtering, and etching the alloy film to form a straight line. Then, an amorphous indium tin oxide film is formed on the surface of the alloy film, and an oxalic acid-based solution of a weak acid which does not dissolve the linear circuit of the underlying alloy film is used, and the indium tin oxide film is formed only in the form of a residual indium tin oxide film. The in-line alloy film linear circuit vertically intersects the indium tin oxide film linear circuit to produce a sample. _ Bonding durability is to produce the Alhansne pattern as shown in the γth diagram of the first embodiment, and the activation energy is estimated from the slope of the Yahannis diagram at a permissible current of 3 mA and 1 〇 microamperes. The result of the bonding endurance time of 85 degrees Celsius is displayed (this joint durability measurement is performed by referring to JIS_C-5〇〇3 electronic component failure rate test method and JIS-C-0021 heating test method). As is apparent from the results of Table 5, in the case of Example 2, the joint resistance value of Example 2 was slightly higher than that of the chromium film, but had the same degree of bonding characteristics as the chromium used as the cap layer. Further, in the case of Embodiment 3, Embodiment 4, and Embodiment 6 2169-6972-PF 25; 12938351 to Embodiment 9, it is sufficient for both the joint resistance value and the joint endurance value. Characteristics. In the case of Example 5, the joint: 14 σ is durable and has good results. The judgment should be influenced by the process of forming the direct joint structure. Second Example. This third embodiment illustrates the results of the relationship between the bonding resistance characteristics of the alloy electrode layer and the heat treatment of Investigation Example 4 (aluminum-0·3 at% carbon-5. 0 at%). . The measurement of the bonding resistance was carried out in the same manner as the bonding property 1 described in Table 5 of the second embodiment described above (bonding the alloy electrode layer on the indium tin oxide film). However, the test sample for measuring the joint resistance value of the third embodiment is directly bonded to the electrode layer of the sinter alloy after the transparent electrode layer (indium tin oxide film) is placed in an inert gas (nitrogen) atmosphere. Heat treatment at 3 temperatures of 250 ° C, 3 〇 0 ° C, and 350 ° C (60

分鐘)。結果如表6所示D 表6 熱處理溫度 接合阻抗值Ω 250t: 220 300°C 「 ιϊ5 ~ 350〇C 100 還有,在玻璃基板上濺鍍(輪入電力為3.0瓦特/平方 公分、氬氣流量為100立方公分/分鐘、氬氣壓力為〇 5帕) 形成〇· 2微米厚的鋁合金電極層,以製作得到測試試樣,再 將此測試試樣於氮氣氣氛氣中熱處理(攝氏2〇〇度至攝氏 400度)1小時,再以掃瞄式電子顯微鏡(sem : ι〇〇〇〇倍) Μ察熱處理後的測試試樣表面,結果如第1 〇圖所示。 2169-6972-PF1-20051028 26 1298351 由表6可知,接合後熱處理溫度變高時,確認接合阻抗 值會變小。還有,如第1〇圖所示,在攝氏度至攝氏_ 度(D、E、F)的熱處理中,嫁認有形成於銘合金電極層中 的铭金屬間化合物(_化幻析出物(在各觀察照片中白 色班點部分)存在,且也確認高溫度狀態下,才斤出物會變 大。還有,第10圖之B (攝氏2〇〇度)、c (攝氏25〇度)析出 物未明確顯現,經參考第一實施例所示之第旧的結果,應 是鋁合金電極層中開始析出金屬間化合物(鎳化鋁)所致。 由表6及第10圖可知,為了實現接合阻抗值為2〇〇歐姆/ □ ίο微米以下的接合狀態,較有佳係進行攝氏28〇度以上的 熱處理。此係藉由進行某一程度的熱處理,以使適當的鋁 金屬間化合物分散存在於鋁合金電極層中,如此所析出之 鋁金屬間化合物可以某種程度地凝集成適當的粒徑,而實 現良好的接合狀態。還有,此熱處理的上限溫度,在考虞 鋁合金電極層的耐熱性及各種元件的製造條件後,較實用 的上限溫度係為攝氏400度至攝氏500度。 第四實施例··最後,此第四實施例係對調查上述實施 例2、實施例4、實施例5、比較例2等組成的鋁合金電極層 與作為透明電極的銦錫氧化物電極層相接合之情形的接人 特性的結果進行說明。 此第四實施例係對上述第二實施例之接合特性丨進行 調查。亦即,形成各合金膜後,利用銦鋅氧化物(I ZO )才,、 乾(氧化姻(In2〇3)-10.7重篁百分比的氧化鋅(zn〇))於各 合金膜上形成銦鋅氧化物膜。此時測試試樣的製造條件、minute). The results are shown in Table 6. Table D Heat Treatment Temperature Bonding Impedance Value Ω 250t: 220 300°C " ϊ 5 ~ 350 〇 C 100 Also, sputtered on a glass substrate (round-in power is 3.0 watts / cm ^ 2, argon The flow rate is 100 cubic centimeters per minute, and the argon pressure is 〇5 Pa.) A 2 μm thick aluminum alloy electrode layer is formed to prepare a test sample, and the test sample is heat treated in a nitrogen atmosphere (Celsius 2). The temperature was measured to 400 ° C for 1 hour, and the surface of the test specimen after heat treatment was observed with a scanning electron microscope (sem : ι〇〇〇〇). The results are shown in Fig. 1 2169-6972 -PF1-20051028 26 1298351 It can be seen from Table 6 that when the heat treatment temperature after joining becomes high, it is confirmed that the joint resistance value becomes small. Also, as shown in Fig. 1, in degrees Celsius to Celsius (D, E, F) In the heat treatment, the intermetallic compound formed in the electrode layer of the alloy is affixed (the illusion of the illusion (in the white part of each observation photograph) exists, and it is confirmed that the temperature is high. Things will get bigger. Also, Figure 10 B (Celsius 2〇〇) ), c (25 degrees Celsius) precipitates are not clearly manifested, and the old results shown in the first embodiment should be caused by the initiation of precipitation of intermetallic compounds (nickel aluminum) in the aluminum alloy electrode layer. It can be seen from Tables 6 and 10 that in order to achieve a bonding state in which the bonding resistance value is 2 〇〇 ohm / □ ί 微米 or less, it is preferable to perform heat treatment at 28 degrees Celsius or higher. This is performed by a certain degree of heat treatment. In order to disperse an appropriate aluminum intermetallic compound in the aluminum alloy electrode layer, the aluminum intermetallic compound thus precipitated can be a certain degree of aggregation into a suitable particle size to achieve a good bonding state. The upper limit temperature is a practical upper limit temperature of 400 degrees Celsius to 500 degrees Celsius after the heat resistance of the aluminum alloy electrode layer and the manufacturing conditions of various components. Fourth Embodiment Finally, this fourth embodiment The investigation of the case where the aluminum alloy electrode layer composed of the above-described Example 2, Example 4, Example 5, and Comparative Example 2 is bonded to the indium tin oxide electrode layer as a transparent electrode is used. The fourth embodiment investigates the bonding characteristics of the second embodiment described above, that is, after forming each alloy film, using indium zinc oxide (I ZO ), dry (oxidized marriage ( In2〇3)-10.7% by weight of zinc oxide (zn〇)) forms an indium zinc oxide film on each alloy film. At this time, the test sample is manufactured,

2169-6972-PF 27 1298351 接合特性1的測量方法皆與上述第二實施例相同。但是,用 來調查此第四實施例之接合特性丨的測試試樣,係於構成開 爾文元件之際的接合面積為2500平方微米(5〇微米χ5〇微 米)的情形下進行測試。接合阻抗值的測量結果如表7所 示,壽命耐久測試結果係如第11圖所示。表7及第u圖所示 之接合阻抗值’係於測喊试樣製作後,在惰性氣體(氮氣、 氣氛氣中,進行攝氏250度熱處理(60分鐘)後,所測量的 結果。2169-6972-PF 27 1298351 The measurement method of the bonding characteristic 1 is the same as that of the second embodiment described above. However, the test specimen for investigating the joint characteristics of the fourth embodiment was tested in the case where the joint area at the time of forming the Kelvin element was 2,500 square micrometers (5 Å to 5 μm). The measurement results of the joint resistance values are shown in Table 7, and the endurance test results are shown in Fig. 11. The joint resistance value shown in Table 7 and Fig. u is the result of measurement after heat treatment (60 minutes) in an inert gas (nitrogen gas or atmosphere) after the preparation of the test sample.

表7 電流-電壓 測定 接合特性1 接合阻抗值 Ω (Π50/Ζ m) 實施例2 歐姆 34. 0 實施例4 歐姆 30. 2 實施例5 歐姆 30. 6 比較例2 歐姆 32. 8Table 7 Current-voltage measurement Bonding characteristics 1 Bonding resistance value Ω (Π50/Ζ m) Example 2 Ohm 34. 0 Example 4 Ohm 30. 2 Example 5 Ohm 30. 6 Comparative Example 2 Ohm 32. 8

由表7所示之結果可知,實施例2、實施例4、實施例5 及比較例2全部在與銦辞氧化物電極層相接合時,皆可得到 良好的接合阻抗值。然而,由第丨丨圖之壽命耐久測試結果 可知’實施例2、實施例4、實施例5在超過耐久時間2〇〇小 時後,接合阻抗值仍未見到大的變化。另一方面,比較例2 在經過約20小時後,即見到激烈的接合阻抗值的增大,確 認是產生接合部份的破壞。 [產業上可利性]Γ 由上述可知’本發明之具有透明電極層與鋁合金電極 2169-6972-PF1-20051028 28 1298351 層的薄膜電路中,係構成不僅可以省略蓋層、也不會產生 "心也可以歐姆接合且具有優異的接合阻抗性的薄 膜電路冑有,液晶顯示元件採用此薄膜電路之際,不僅 可 '、以銦錫氧化物電極層為代表的透明電極層直接接 合’也可Μ確實抑制界面反應,也可以滿足歐姆接合特性、 低接合阻抗、接線膜阻抗、耐熱性等全部液晶顯示元件特 性,而為實用上極適合的薄膜電路。 【圖式簡單說明】 > 帛1圖係為利用穿透式電子顯微鏡觀察實施例之銘合 金電極層與矽層間接合部剖面的照片。 第2圖係為利用穿透式電子顯微鏡觀察實施例之鋁合 金電極層與銦錫氧化物電極層間接合部剖面的照I 第3圖係為第2圖之接合部剖面的放大照片。 第4圖係為將銦錫氧化物電極層與鋁合金電極層交叉 層積的測試試樣概略立體圖。 第5圖係為測量實施例之電流-電壓特性的圖形。 ’第6圖係為測量比較例之電流—電壓特性的圖形。 第7圖係為測量接合耐久特性的亞罕尼斯圖形。 第8圖係為施加於電極層之應力與熱處理溫度間的關 係圖。 第9圖係為接合阻抗與銦錫氧化物電位差的關係圖。 第圖係為熱處理後之鋁合金電極層表面的掃瞄式電 子顯微鏡觀察照>;。 第11圖係為銦鋅氧化物電極層之壽命耐久測試結果的As is apparent from the results shown in Table 7, all of Example 2, Example 4, Example 5, and Comparative Example 2 were excellent in joint resistance values when they were joined to the indium oxide electrode layer. However, it can be seen from the results of the life endurance test of the second diagram that "Example 2, Example 4, and Example 5 have not seen a large change in the joint resistance value after the endurance time exceeds 2 hrs. On the other hand, in Comparative Example 2, after about 20 hours passed, an increase in the intense joint resistance value was observed, and it was confirmed that the joint portion was broken. [Industrial Applicability] Γ From the above, it is known that the thin film circuit having the transparent electrode layer and the aluminum alloy electrode 2169-6972-PF1-20051028 28 1298351 layer of the present invention can not only omit the cap layer but also does not generate "Thin film which can also be ohmically bonded and has excellent joint resistance. When the liquid crystal display element uses this thin film circuit, not only the transparent electrode layer typified by the indium tin oxide electrode layer can be directly bonded' It is also possible to suppress the interface reaction, and it is also possible to satisfy the characteristics of all liquid crystal display elements such as ohmic junction characteristics, low junction resistance, wiring film resistance, and heat resistance, and is a practically suitable thin film circuit. BRIEF DESCRIPTION OF THE DRAWINGS > The Fig. 1 is a photograph of a cross section of the joint between the electrode electrode layer and the tantalum layer of the embodiment by a transmission electron microscope. Fig. 2 is a magnified photograph of a cross section of the joint portion of Fig. 2, which is a cross section of the joint portion between the aluminum alloy electrode layer and the indium tin oxide electrode layer of the embodiment, observed by a transmission electron microscope. Fig. 4 is a schematic perspective view showing a test sample in which an indium tin oxide electrode layer and an aluminum alloy electrode layer are laminated. Figure 5 is a graph showing the current-voltage characteristics of the measurement examples. Fig. 6 is a graph for measuring the current-voltage characteristics of the comparative example. Figure 7 is an Al Hanisian figure for measuring the durability characteristics of the joint. Figure 8 is a graph showing the relationship between the stress applied to the electrode layer and the heat treatment temperature. Figure 9 is a graph showing the relationship between the bonding resistance and the potential difference of indium tin oxide. The figure is a scanning electron microscope observation of the surface of the aluminum alloy electrode layer after heat treatment>; Figure 11 is the endurance test result of the indium zinc oxide electrode layer.

2169-6972-PF 29 1298351 接合阻抗值圖形。 【主要元件符號說明】 1 〇〜端子部 40〜端子部2169-6972-PF 29 1298351 Bonding resistance value graph. [Description of main component symbols] 1 〇~terminal section 40~terminal section

2169-6972-PF 302169-6972-PF 30

Claims (1)

1298351 十、申請專利範園·· h 一種薄膜電路之接合構造,包括. 透明電極層;以及 ::金電極層’與前述透明電極層直接接合. 其特徵在於: 设授口, 於叙合金電極層中分 内之氧化還原電位的析出物,、'2伏特至—°.1 2 3伏特範圍 :::=:1項所述㈣膜電路之接合構 啊出物係為含鋁之金屬間化合物。 冰,3. ^申請專利範圍第1項所述的薄膜電路之接合構 造’其中前述紹合金電極層之混合電位係為] -0· 6伏特。 # & 4.如申請專利範圍第2項所述的薄膜電路之接合構 造,其中前述鋁合金電極層之混合電位係為-1. 4伏特至 -0. 6伏特。 2169-6972-PF 31 1 ·如申請專利範圍第1項所述的薄膜電路之接合構 造’其中前述透明電極層係由含銦系氧化物的膜所構成, 刖述透明電極與前述鋁合金電極層的接合阻抗值係為1歐 姆/口10微米至200歐姆/口1〇微米。 2 ·如申請專利範圍第2項所述的薄膜電路之接合構 造’其中前述透明電極層係由含銦系氧化物的膜所構成, 前述透明電極與前述鋁合金電極層的接合阻抗值係為1歐 姆/口10微米至2〇〇歐姆/〇1〇微米。 3 ·如申請專利範圍第3項所述的溥膜電路之接合構 1298351 造,其中前述透明電極層係由含銦系氧化物的膜所構成, 則述透明電極與前述鋁合金電極層的接合阻抗值係為ι歐 姆/口10微米至2〇〇歐姆/口1〇微米。 8·如申請專利範圍第4項所述的薄膜電路之接合構 造’其中前述透明電極層係由含銦系氧化物的膜所構成, 則述透明電極與前述鋁合金電極層的接合阻抗值係為^歐 姆/口10微米至2〇〇歐姆/□〗〇微米。 9 ·如申凊專利範圍第1項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏3〇〇度、j小時熱處理後 的比阻抗值係為3· 5微歐姆公分至35微歐姆公分。 10·如申請專利範圍第2項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏3〇〇度、丨小時熱處理後 的比阻抗值係為3· 5微歐姆公分至35微歐姆公分。 11 ·如申請專利範圍第3項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏3〇〇度、丨小時熱處理後 的比阻抗值係為3· 5微歐姆公分至35微歐姆公分。 12·如申請專利範圍第4項所述的薄膜電路之接合構 造’其中前述銘合金電極層在攝氏3〇〇度、1小時熱處理後 的比阻抗值係為3· 5微歐姆公分至35微歐姆公分。 13·如申請專利範圍第5項所述的薄膜電路之接合構 造’其中前述銘合金電極層在攝氏3〇〇度、1小時熱處理後 的比阻抗值係為3 · 5微歐姆公分至3 5微歐姆公分。 14·如申請專利範圍第6項所述的薄膜電路之接合構 造’其中前述銘合金電極層在攝氏3〇〇度、1小時熱處理後 2169-6972-PF 32 1298351 的比阻抗值係為3· 5微歐姆公分至35微歐姆公分。 15·如申請專利範圍第7項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏3〇〇度、i小時熱處理後 的比阻抗值係為3· 5微歐姆公分至35微歐姆公分。 1 6 ·如申凊專利範圍第8項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏3〇〇度、丨小時熱處理後 的比阻抗值係為3· 5微歐姆公分至35微歐姆公分。 1 7·如申請專利範圍第1項所述的薄膜電路之接合構 造’其中前述鋁合金電極層在攝氏3〇〇度、1小時熱處理後 的鋁合金電極層表面上,形成有漣漪的發生率係為百分之 3 · 〇以下。 18·如申請專利範圍第2項所述的薄膜電路之接合構 造’其中前述鋁合金電極層在攝氏3〇〇度、1小時熱處理後 的銘合金電極層表面上,形成有漣漪的發生率係為百分之 3. 〇以下。 1 9·如申請專利範圍第3項所述的薄膜電路之接合構 造’其中前述鋁合金電極層在攝氏3〇〇度、1小時熱處理後 的銘合金電極層表面上,形成有漣漪的發生率係為百分之 3. 〇以下。 20如申請專利範圍第4項所述的薄膜電路之接合構 造’其中前述鋁合金電極層在攝氏300度、1小時熱處理後 的銘合金電極層表面上,形成有漣漪的發生率係為百分之 3. 〇以下。 21 ·如申請專利範圍第5項所述的薄膜電路之接合構 2169-6972-PF 33 12983^1 造,其中前述鋁合金電極層在攝氏300度、i小時熱處理後 的銘合金電極層表面上,形成有漣漪的發生率係為百分之 〇以下 2 2 ·如申凊專利範圍第6項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏300度、1小時熱處理後 的鋁口金電極層表面上,形成有漣漪的發生率係為百分之 q 〇以下。1298351 X. Patent application Fan Park·· h A bonding structure of a thin film circuit, comprising: a transparent electrode layer; and: a gold electrode layer 'directly bonded to the transparent electrode layer. The feature is: providing an orifice, the alloy electrode The precipitate of the redox potential in the layer, '2 volts to -1. 1 2 3 volt range:::=: 1 item (4) The junction structure of the membrane circuit is the aluminum-containing metal Compound. Ice, 3. The joint structure of the thin film circuit described in claim 1 wherein the mixed potential of the electrode layer is -0·6 volt. The volts of the mixture of the aluminum alloy electrode layer is -1. 4 volts to -0.6 volts. 2169-6972-PF 31 1 The bonding structure of the thin film circuit according to the first aspect of the invention, wherein the transparent electrode layer is composed of a film containing an indium-based oxide, and the transparent electrode and the aluminum alloy electrode are described. The bonding resistance value of the layer is 1 ohm/port 10 micron to 200 ohm/port 1 〇 micron. 2. The bonding structure of the thin film circuit according to the second aspect of the invention, wherein the transparent electrode layer is composed of a film containing an indium-based oxide, and a bonding resistance value between the transparent electrode and the aluminum alloy electrode layer is 1 ohm / port 10 microns to 2 ohms / 〇 1 〇 micron. 3. The bonding structure of the ruthenium film circuit according to the third aspect of the invention, wherein the transparent electrode layer is composed of a film containing an indium-based oxide, and the bonding between the transparent electrode and the aluminum alloy electrode layer is described. The impedance value is ι ohm / port 10 micron to 2 ohm ohm / port 1 〇 micron. 8. The bonding structure of the thin film circuit according to the fourth aspect of the invention, wherein the transparent electrode layer is composed of a film containing an indium oxide, and the bonding resistance value between the transparent electrode and the aluminum alloy electrode layer is For ^ ohm / port 10 microns to 2 ohms / □ 〇 〇 micron. The bonded structure of the thin film circuit according to the first aspect of the invention, wherein the specific resistance value of the aluminum alloy electrode layer after heat treatment at 3 degrees Celsius and j hours is 3.5 micro ohm centimeters to 35 Micro ohm centimeters. The bonding structure of the thin film circuit according to the second aspect of the invention, wherein the specific resistance value of the aluminum alloy electrode layer after heat treatment at 3 degrees Celsius and 丨 hour is 3·5 micro ohm centimeters to 35 micrometers. Ohm centimeters. The bonding structure of the thin film circuit according to the third aspect of the invention, wherein the specific resistance value of the aluminum alloy electrode layer after heat treatment at 3 degrees Celsius and 丨 hour is 3·5 micro ohm centimeters to 35 micrometers. Ohm centimeters. 12. The joint structure of the thin film circuit as described in claim 4, wherein the specific impedance of the electrode layer of the alloy electrode at 3 degrees Celsius and 1 hour heat treatment is 3.5 micro ohm centimeters to 35 micrometers. Ohm centimeters. 13. The bonding structure of the thin film circuit according to claim 5, wherein the specific impedance value of the electrode layer of the alloy electrode after 3 hours of heating at 1 degree Celsius and 1 hour heat treatment is 3 · 5 micro ohm centimeters to 3 5 Micro ohm centimeters. 14. The joint structure of the thin film circuit as described in claim 6 wherein the specific impedance of the electrode layer of the first alloy is 3 degrees Celsius, and after 1 hour heat treatment, the specific impedance value of 2169-6972-PF 32 1298351 is 3· 5 micro ohm centimeters to 35 micro ohm centimeters. The bonding structure of the thin film circuit according to claim 7, wherein the specific resistance value of the aluminum alloy electrode layer after heat treatment at 3 degrees Celsius and i hour is 3-5 micro ohm centimeters to 35 micrometers. Ohm centimeters. The bonding structure of the thin film circuit according to the eighth aspect of the invention, wherein the specific resistance value of the aluminum alloy electrode layer after heat treatment at 3 degrees Celsius and 丨 hours is 3.6 micro ohm centimeters to 35 micro ohm centimeters. The joint structure of the thin film circuit according to the first aspect of the invention, wherein the aluminum alloy electrode layer is formed on the surface of the aluminum alloy electrode layer after heat treatment at 3 degrees Celsius and 1 hour, and the incidence of bismuth is formed. It is 3 % 〇 or less. 18. The joint structure of a thin film circuit according to claim 2, wherein the aluminum alloy electrode layer is formed on the surface of the alloy electrode layer after heat treatment at 3 degrees Celsius and 1 hour heat treatment. For the percentage of 3. 〇 below. The bonding structure of the thin film circuit as described in claim 3, wherein the aluminum alloy electrode layer is formed on the surface of the alloy electrode layer after heat treatment at 3 degrees Celsius and 1 hour heat treatment. The system is 3.3% below. (20) The bonding structure of the thin film circuit according to the fourth aspect of the invention, wherein the aluminum alloy electrode layer is formed on the surface of the alloy electrode layer after heat treatment at 300 ° C for 1 hour, and the incidence of bismuth is percentage 3. The following. [21] The bonding structure of the thin film circuit of claim 5, wherein the aluminum alloy electrode layer is on the surface of the alloy electrode layer after heat treatment at 300 ° C for 1 hour. The incidence of the formation of bismuth is less than or equal to 2%. The bonding structure of the thin film circuit as described in claim 6, wherein the aluminum alloy electrode layer is heat treated at 300 degrees Celsius for 1 hour. On the surface of the aluminum-plated gold electrode layer, the incidence of bismuth formation is less than q 〇. 23·如申請專利範圍第7項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏300度、1小時熱處理後 的鋁合金電極層表面上,形成有漣漪的發生率係為百分之 3. 0以下。 24·如申請專利範圍第8項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏3〇〇度、i小時熱處理後 的鋁合金電極層表面上,形成有漣漪的發生率係為百分之 3. 〇以下。 25·如申請專利範圍第9項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏3〇〇度、i小時熱處理後 的鋁合金電極層表面上,形成有漣漪的發生率係為百分之 3. 〇以下。 2 6 ·如申凊專利範圍第1 〇項所述的薄膜電路之接合構 造,其中前述鋁合金電極層在攝氏3〇〇度、i小時熱處理後 的鋁合金電極層表面上,形成有漣漪的發生率係為百分之 3. 〇以下。 27·如申請專利範圍第n項所述的薄膜電路之接合構 2169-6972-PF 1298351 造,其中前述鋁合金電極層在攝氏300度、1小時熱處理後 的銘合金電極層表面上,形成有漣漪的發生率係為百分之 3. 0以下。 28·如申請專利範圍第12項所述的薄膜電路之接合構 造’其中前述鋁合金電極層在攝氏300度、i小時熱處理後 的铭合金電極層表面上,形成有漣漪的發生率係為百分之 3 · 0以下。 29·如申請專利範圍第13項所述的薄膜電路之接合構 造’其中前述鋁合金電極層在攝氏3〇〇度、1小時熱處理後 的銘合金電極層表面上,形成有漣漪的發生率係為百分之 3. 0以下。 3 〇 ·如申請專利範圍第丨4項所述的薄膜電路之接合構 造’其中前述鋁合金電極層在攝氏3〇〇度、1小時熱處理後 的銘合金電極層表面上,形成有漣漪的發生率係為百分之 3. 0以下。 31 ·如申請專利範圍第丨5項所述的薄膜電路之接合構 造’其中前述銘合金電極層在攝氏3〇〇度、1小時熱處理後 的銘合金電極層表面上,形成有漣漪的發生率係為百分之 3. 0以下。 32·如申請專利範圍第16項所述的薄膜電路之接合構 造’其中前述紹合金電極層在攝氏300度、1小時熱處理後 的铭合金電極層表面上,形成有漣漪的發生率係為百分之 3 · 0以下。 33.如申請專利範圍第1項所述的薄膜電路之接合構 2169-6972-PF 35 1298351 造,其中前述鋁合金電極層含有〇· 5 at%至25 at%的鎳。 34.如申請專利範圍第2項所述的薄膜電路之接合構 -造’其中前述鋁合金電極層含有〇· 5 at%至25 at%的鎳。 35·如申請專利範圍第3項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有0.5 at%至25 at%的鎳。 36·如申請專利範圍第4項所述的薄膜電路之接合構 造,其中前述鋁合金電極層含有〇· 5 at%至25 at%的鎳。 37·如申請專利範圍第5項所述的薄膜電路之接合構 春造’其中前述鋁合金電極層含有〇· 5 at%至25 at%的鎳。 38·如申請專利範圍第6項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有〇. 5 at%至25 at%的鎳。 39·如申請專利範圍第7項所述的薄膜電路之接合構 - 造’其中前述鋁合金電極層含有0.5 at%至25 at%的鎳。 - 40·如申請專利範圍第8項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有〇. 5 at%至25 at%的鎳。 41.如申請專利範圍第9項所述的薄膜電路之接合構 _ 造’其中前述鋁合金電極層含有〇. 5 at%至25 at%的鎳。 42·如申請專利範圍第1〇項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有〇. 5 at%至25 at%的鎳。 43·如申請專利範圍第n項所述的薄膜電路之接合構 造,其中前述鋁合金電極層含有〇.5 at%至25 at%的鎳。 44. 如申請專利範圍第12項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有0.5 at%至25 at%的鎳。 45. 如申請專利範圍第13項所述的薄膜電路之接合構 2169-6972-PF 36 129^351 , 造’其中前述鋁合金電極層含有〇· 5 at%至25 at%的鎳。 46·如申請專利範圍第14項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有〇. 5 at%至25 at%的鎳。 47·如申請專利範圍第15項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有〇· 5 at%至25 at%的鎳。 48·如申請專利範圍第16項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有〇· 5 at%至25 at%的鎳。 49·如申請專利範圍第17項所述的薄膜電路之接合構 φ 造’其中前述鋁合金電極層含有0. 5 at%至25 at%的鎳。 50·如申請專利範圍第18項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有〇·5 at%至25 at%的鎳。 51·如申請專利範圍第19項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有〇· 5 at%至25 at%的鎳。 52. 如申請專利範圍第2〇項所述的薄膜電路之接合構 造’其中前述銘合金電極層含有〇. 5 at%至25 at%的鎳。 53. 如申請專利範圍第21項所述的薄膜電路之接合構 φ 造’其中前述銘合金電極層含有0.5 at%至25 at%的錄。 54·如申請專利範圍第22項所述的薄膜電路之接合構 造’其中前述鋁合金電極層含有〇·5 at%至25 at%的錄。 55·如申請專利範圍第23項所述的薄膜電路之接合構 造’其中前述無合金電極層含有〇·5 at%至25 at%的錄。 56·如申請專利範圍第24項所述的薄膜電路之接合構 — 造’其中前述銘合金電極層含有0·5 at%至25 at%的鎳。 - 57·如申請專利範圍第25項所述的薄膜電路之接合構 2169-6972-PF 37 口98351 - 造’其中前述銘合金電極層含有0· 5 at%至25 at%的鎳。 58.如申請專利範圍第26項所述的薄膜電路之接合構 造’其中前述銘合金電極層含有0· 5 at%至25 at%的鎳。 59·如申請專利範圍第27項所述的薄膜電路之接合構 造’其中前述銘合金電極層含有〇·5 at%至25 at%的鎳。 60·如申請專利範圍第28項所述的薄膜電路之接合構 ,造’其中前述銘合金電極層含有〇·5 at%至25 at%的鎳。 61·如申請專利範圍第29項所述的薄膜電路之接合構 籲 造’其中前述銘合金電極層含有0.5 at%至25 at%的鎳。 62·如申請專利範圍第3〇項所述的薄膜電路之接合構 造’其中前述銘合金電極層含有〇·5 &1:%至25 at%的鎳。 6 3 ·如申睛專利範圍第31項所述的薄膜電路之接合構 - 造’其中前述鋁合金電極層含有0· 5 at%至25 at%的鎳。 _ 6 4 ·如申晴專利範圍第3 2項所述的薄膜電路之接合構 造’其中前述紹合金電極層含有〇·5 at%至25 at%的鎳。 6 5 ·如申請專利範圍第1至6 4項中任一項所述的薄膜 • 電路之接 合構造’其中前述鋁合金電極層含有〇. 1 &1:%至 7· 0 at%的鈷及/或鐵。 66·如申請專利範圍第33至64項中任一項所述的薄膜 電路之接合構造,其中前述鋁合金電極層更含有〇. 1 at% 至3.0 at%的歛。 67.如申請專利範圍第65項所述的薄膜電路之接合構 造,其中前述銘合金電極層更含有〇·1 at%至3· 0 at%的鈇。 • 68·如申請專利範圍第33至64項中任一項所述的薄與 2169-6972-PF 38 1298351 ' 電路之接合構造,其中前述鋁合金電極層含有0.1 at%至 ~ 3. 0 at%的碳。 , 69.如申請專利範圍第65項所述的薄膜電路之接合構 造,其中前述鋁合金電極層含有0. 1 at %至3. 0 at%的碳。 70.如申請專利範圍第66項所述的薄膜電路之接合 構造,其中前述紹合金電極層含有0.1 at%至3.Oat%的石炭。The bonding structure of the thin film circuit according to the seventh aspect of the invention, wherein the aluminum alloy electrode layer is formed on the surface of the aluminum alloy electrode layer after heat treatment at 300 ° C for 1 hour. Less than 3.0. [24] The bonding structure of the thin film circuit according to the eighth aspect of the invention, wherein the aluminum alloy electrode layer is formed on the surface of the aluminum alloy electrode layer after heat treatment at 3 degrees Celsius and i hour, and a rate of occurrence of bismuth is formed. For the percentage of 3. 〇 below. The bonding structure of the thin film circuit according to the ninth aspect of the invention, wherein the aluminum alloy electrode layer is formed on the surface of the aluminum alloy electrode layer after heat treatment at 3 degrees Celsius and i hour, For the percentage of 3. 〇 below. The bonding structure of the thin film circuit according to the first aspect of the invention, wherein the aluminum alloy electrode layer is formed on the surface of the aluminum alloy electrode layer after heat treatment at 3 degrees Celsius and i hour. The incidence rate is 3.3% below. [27] The bonded circuit of the invention of claim 5, wherein the aluminum alloy electrode layer is formed on the surface of the alloy electrode layer after heat treatment at 300 ° C for 1 hour. The incidence of sputum is 3.0% or less. 28. The bonding structure of the thin film circuit according to claim 12, wherein the aluminum alloy electrode layer is formed on the surface of the alloy electrode layer after heat treatment at 300 ° C for 1 hour, and the incidence of defects is 100. 3 or less. 29. The bonding structure of the thin film circuit according to claim 13, wherein the aluminum alloy electrode layer is formed on the surface of the alloy electrode layer after heat treatment at 3 degrees Celsius and 1 hour heat treatment. It is below 3.0%. 3 〇 接合 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如The rate is 3.0% or less. 31. The joint structure of the thin film circuit as described in the fifth paragraph of the patent application, wherein the occurrence of bismuth is formed on the surface of the alloy electrode layer after the heat treatment of the first alloy electrode layer at 3 degrees Celsius and 1 hour heat treatment. The system is 3.0% or less. 32. The joint structure of the thin film circuit according to claim 16, wherein the occurrence of bismuth on the surface of the electrode layer of the alloy electrode layer after the heat treatment at 300 ° C for 1 hour is 100. 3 or less. 33. The bonded film construction of 2169-6972-PF 35 1298351 according to claim 1, wherein the aluminum alloy electrode layer contains at·5 at% to 25 at% of nickel. 34. The bonding structure of a thin film circuit according to claim 2, wherein the aluminum alloy electrode layer contains at·5 at% to 25 at% of nickel. The bonding structure of the thin film circuit as described in claim 3, wherein the aforementioned aluminum alloy electrode layer contains 0.5 at% to 25 at% of nickel. The bonding structure of the thin film circuit according to claim 4, wherein the aluminum alloy electrode layer contains at·5 at% to 25 at% of nickel. 37. The bonding structure of the thin film circuit according to claim 5, wherein the aluminum alloy electrode layer contains at·5 at% to 25 at% of nickel. 38. The bonded structure of the thin film circuit of claim 6, wherein the aluminum alloy electrode layer contains at. 5 at% to 25 at% of nickel. 39. The bonding structure of a thin film circuit according to claim 7, wherein the aluminum alloy electrode layer contains 0.5 at% to 25 at% of nickel. The bonding structure of the thin film circuit as described in claim 8 wherein the aluminum alloy electrode layer contains at. 5 at% to 25 at% of nickel. The bonding structure of the thin film circuit according to claim 9 wherein the aluminum alloy electrode layer contains 0.5 at% to 25 at% of nickel. 42. The bonding structure of the thin film circuit according to the first aspect of the invention, wherein the aluminum alloy electrode layer contains at. 5 at% to 25 at% of nickel. 43. The bonded structure of a thin film circuit according to claim n, wherein the aluminum alloy electrode layer contains at.5 at% to 25 at% of nickel. 44. The bonded structure of a thin film circuit according to claim 12, wherein the aforementioned aluminum alloy electrode layer contains 0.5 at% to 25 at% of nickel. 45. The bonding structure 2169-6972-PF 36 129^351 of the thin film circuit according to claim 13, wherein the aluminum alloy electrode layer contains at·5 at% to 25 at% of nickel. 46. The bonded structure of the thin film circuit of claim 14, wherein the aluminum alloy electrode layer contains at. 5 at% to 25 at% of nickel. 47. The bonded structure of a thin film circuit according to claim 15, wherein the aluminum alloy electrode layer contains at·5 at% to 25 at% of nickel. 48. The bonding structure of a thin film circuit according to claim 16, wherein the aluminum alloy electrode layer contains at·5 at% to 25 at% of nickel. The aluminum alloy electrode layer contains 0.5 to 5% to 25 at% of nickel, as described in the above. The bonding structure of the thin film circuit as described in claim 18, wherein the aluminum alloy electrode layer contains at·5 at% to 25 at% of nickel. The bonding structure of the thin film circuit as described in claim 19, wherein the aluminum alloy electrode layer contains at·5 at% to 25 at% of nickel. 52. The bonded structure of the thin film circuit according to the second aspect of the invention, wherein the foregoing alloy electrode layer contains at. 5 at% to 25 at% of nickel. 53. The bonding structure of the thin film circuit according to claim 21, wherein the foregoing alloy electrode layer contains 0.5 at% to 25 at%. 54. The bonded structure of a thin film circuit according to claim 22, wherein the aforementioned aluminum alloy electrode layer contains at·5 at% to 25 at%. The bonding structure of the thin film circuit as described in claim 23, wherein the aforementioned alloy-free electrode layer contains at·5 at% to 25 at%. The bonding structure of the thin film circuit as described in claim 24, wherein the foregoing alloy electrode layer contains 0.5 to 15 at% of nickel. - 57. The bonding structure of the thin film circuit as described in claim 25, 2169-6972-PF 37, 98935 - wherein the aforementioned alloy electrode layer contains 0.5 to 5% to 25 at% of nickel. 58. The bonded structure of a thin film circuit according to claim 26, wherein the aforementioned alloy electrode layer contains 0.5 to 20 at% of nickel. The bonding structure of the thin film circuit as described in claim 27, wherein the aforementioned alloy electrode layer contains at·5 at% to 25 at% of nickel. 60. The joint structure of a thin film circuit according to claim 28, wherein the electrode layer of the foregoing alloy contains at·5 at% to 25 at% of nickel. 61. The bonding structure of the thin film circuit according to claim 29, wherein the foregoing alloy electrode layer contains 0.5 at% to 25 at% of nickel. 62. The bonded structure of a thin film circuit according to the third aspect of the invention, wherein the foregoing alloy electrode layer contains 〇·5 & 1:% to 25 at% of nickel. 6 3 - The bonding structure of the thin film circuit as described in claim 31, wherein the aluminum alloy electrode layer contains 0.5 to 20 at% of nickel. _ 6 4 · The bonding structure of the thin film circuit as described in the third paragraph of the Shen Qing patent scope, wherein the aforementioned electrode layer contains at·5 at% to 25 at% of nickel. The bonding structure of the film and the circuit according to any one of claims 1 to 4, wherein the aluminum alloy electrode layer contains 〇. 1 & 1:% to 7.5 at% of cobalt And / or iron. The bonding structure of the thin film circuit according to any one of claims 33 to 64, wherein the aluminum alloy electrode layer further contains at. 1 at% to 3.0 at%. The bonding structure of the thin film circuit according to claim 65, wherein the foregoing alloy electrode layer further contains at·1 at% to 3.0 at% of ruthenium. The bonding structure of the thin and 2169-6972-PF 38 1298351' circuit according to any one of claims 33 to 64, wherein the aforementioned aluminum alloy electrode layer contains 0.1 at% to ~ 3. 0 at % carbon. The carbon alloy layer has a carbon content of 0.1 to % to 3.00% by weight. The bonded structure of a thin film circuit according to claim 66, wherein the electrode layer of the above-mentioned alloy contains 0.1 at% to 3.Oat% of charcoal. 2169-6972-PF 392169-6972-PF 39
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