1297976 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種電壓轉換器，特別是關於一種應用 在電壓棒換器的驅動電路及方法。 ^ 【先前技術】 , 近年來，在切換式調節器的應用上，同步降壓式轉換 器顯得越來越重要。第一圖係傳統的同步降壓式轉換器 10，其中驅動電路12根據信號IN輸出驅動信號UG及LG 驅動輸出級14。在輸出級14中，高位側電晶體1402及低 位側電晶體1404串聯在輸入電壓Vin及接地GND之間， 驅動信號UG及LG切換高位側及低位側電晶體1402及1404 產生電流I經電感L對電容Co充電，得到輸出電壓Vout。 在驅動電路12中，信號IN連接至及閘1204，以及經一反 相器1202連接至及閘1208，驅動信號LG經反相器1206 〇 連接至及閘1204的另一輸入端，根據信號IN及反相器 1206的輸出，及閘1204輸出驅動信號UG經驅動器1212 驅動高位側電晶體1402,相節點1403經反相器1210連接 ’ 至及閘1208的另一輸入端，根據反相器1202及1210的 、 輸出，及閘1208產生驅動信號1^經驅動器1214驅動低 位側電晶體1404。 然而，在傳統的設計中，為了避免高位侧及低位側電 晶體1402及1404被同時導通，在高位侧及低位側切換之 間切換導通狀態的延遲是必要的，例如，當信號IN由高 1297976 準位轉換低準位時，及閘1204所輸出的驅動信號UG，參 照第二圖的波形15,將轉換低準位，以截止高位侧電晶體 1402’相節點1403上的電壓信號pH的準位在電晶體丨4〇2 截止後也跟著轉為低準位，參照第二圖的波形16，使得反 相益1210的輸出為高準位，此時及閘12〇8所輪出的驅動 信號LG’參照第二圖的波形π，才由低準位轉為高準位， 導通低位側電晶體1404,因此，低位側電晶體14〇4在高 •位侧電晶體1402截止後，再經一延遲時間τι，參照第二 圖的波形18，才被導通。同樣地，當信號IN由低準位轉 為局準位，反相斋1202的輸出轉為低準位，因此及閘 !2〇8所輸出的驅動信號LG轉為低準位，故低位側電晶體 1404截止，此時，反相器12〇6的輸出才由低準位轉為高 準位，使得及閘1204所輸出的驅動信號UG轉為高準位， 導通高位側電晶體1402，換言之，高位側電晶體丨4〇2也 必須在低位侧電晶體1404截止後，經一延遲時間T2才被 〇 導通。 ..... 然而，在延遲週期的期間，輸出級藉由傳統内建在低 位側電晶體1404的二極體整流器1406導通電流I，又傳 _ 統的二極體整流器1406具有高阻抗，所以延遲將造成一 些效率的損失，為了最大化電源效率，適當地切換高位側 及低位侧電晶體1402及1404的導通時間是很重要的。在 已知的技術中，有人使用數位計數器來最佳化延遲時間， 例如美國專利號6, 396, 250所提出的「減少基體導通以及 反相回復損失的控制方法（control method to reduce 1297976 body diode conduction and reverse recovery losses)」，然而，此種數位調整方式是有限制的，例如只 能調整N><2ns(N=l，2, 3,…），假如延遲時間不在調整範圍 内時，例如3ns，便無法達成最佳化。 因此，一種能最佳化高位側及低位侧電晶體切換時間 的驅動電路及方法，乃為所冀。 【發明内容】 本發明的目的之一，在於提出一種應用在電壓轉換器 的驅動電路及方法。 根據本發明，一種應用在電壓轉換器的驅動電路及方 法，包括根據一第一控制信號及一第二控制信號產生一第 一驅動信號及一第二驅動信號驅動該電壓轉換器的高位 側開關及低位側開關，以及藉由一第一信號、一第二信 號、該第一及第二控制信號，控制該第一及第二驅動信號 的延遲，該第一信號係該第一驅動信號或是與該第一驅動 信號具有相同相位的信號，該第二信號係該第二驅動信號 或是與該第二驅動信號具有相同相位的信號，當該第一或 第二驅動信號的延遲過短，使得該第一及第二驅動信號的 工作週期重疊時，延長該第一或第二驅動信號的延遲時 間，當該第一或第二驅動信號的延遲過長，使得該第一及 第二驅動信號的非工作週期重疊時，縮短該第一或第二驅 動信號的延遲時間。 1297976 【實施方式】 第三圖係應用本發明的同步降壓式轉換器20,其中驅 動電路22輸出驅動信號UG及LG至輸出級24切換開關SW1 及SW2，以轉換輸入電壓Vin成為輸出電壓Vout供應至負 載RL。在驅動電路22中，及閘2202連接控制信號U及調 節信號0U，據以輸出信號Sa至驅動器2208，以產生驅動 信號UG驅動開關SW1，及閘2206連接控制信號L及調節 信號0L，據以輸出信號Sb至驅動器2210，以產生驅動信 號 LG 驅動開關 SW2，鎖相電路（phase lock circuit)2204 根據相節點2402上的電壓信號PH、驅動信號LG、控制信 號U及L，輸出調節信號0U及0L。由於電壓信號PH與驅 動信號UG的相位幾乎完全一樣，因此在此實施例中係以 電壓信號PH代替驅動信號UG連接至鎖相電路2204,在其 他實施例中，也可以直接將驅動信號UG或是與驅動信號 UG具有相同相位的信號連接至鎖相電路2204，同樣地， 也可以用與驅動信號LG具有相同相位的信號連接至鎖相 電路2204。 第四圖係第三圖中鎖相電路2204的一個實施例，其 中邏輯電路30利用反或閘3002連接驅動信號LG及電壓 信號PH得到信號S1，驅動信號LG及電壓信號PH也連接 至及閘3004，以得到信號S2，及閘3006及3008分別根 據信號S1及S2以及控制信號U輸出信號S3及S4切換充 放電電路32中的開關3204及3206，以充放電電容3210 產生充電電電VI，電壓控制電流源36根據充電電壓VI供 1297976 應一充電電流ii至充放電電路40，控制信號切換開關 4002以充放電電容4〇〇4產生調節信號〇u。另一方面，反 及閑3010及3012分別根據信號S1及％以及控制信號[ 產生信號S5及S6至充放電電路34中，切換開關34〇4及 3406以充放電電容341〇產生充電電壓V2，電壓控制電流 源38根據充電電壓V2供應充電電流12至充放電電路42, 控制信號U切換開關4202以充放電電容4204產生調節信 號OL 〇1297976 IX. Description of the Invention: [Technical Field] The present invention relates to a voltage converter, and more particularly to a driving circuit and method applied to a voltage bar converter. ^ [Prior Art] In recent years, synchronous buck converters have become increasingly important in the application of switching regulators. The first figure is a conventional synchronous buck converter 10 in which the drive circuit 12 outputs drive signals UG and LG to drive the output stage 14 based on the signal IN. In the output stage 14, the high side transistor 1402 and the low side transistor 1404 are connected in series between the input voltage Vin and the ground GND, and the driving signals UG and LG switch the high side and the low side transistors 1402 and 1404 to generate a current I via the inductor L. The capacitor Co is charged to obtain an output voltage Vout. In the driving circuit 12, the signal IN is connected to the AND gate 1204, and is connected to the AND gate 1208 via an inverter 1202. The driving signal LG is connected to the other input terminal of the AND gate 1204 via the inverter 1206, according to the signal IN. And the output of the inverter 1206, and the gate 1204 output drive signal UG is driven by the driver 1212 to drive the high side transistor 1402, and the phase node 1403 is connected via the inverter 1210 to the other input of the gate 1208, according to the inverter 1202. And the output of the 1210, and the gate 1208 generates a driving signal 1 to drive the lower side transistor 1404 via the driver 1214. However, in the conventional design, in order to prevent the high-side and low-side transistors 1402 and 1404 from being simultaneously turned on, it is necessary to switch the conduction state between the high side and the low side switching, for example, when the signal IN is high by 1297976. When the level is converted to the low level, the driving signal UG outputted by the gate 1204, referring to the waveform 15 of the second figure, will be converted to a low level to cut off the pH of the voltage signal on the node 1403 of the high side transistor 1402'. The bit turns to the low level after the transistor 丨4〇2 is turned off. Referring to the waveform 16 of the second figure, the output of the reverse phase benefit 1210 is at a high level, and the drive of the gate 12〇8 is turned on. The signal LG' is switched from the low level to the high level by referring to the waveform π of the second figure, and the low side transistor 1404 is turned on. Therefore, the low side transistor 14〇4 is turned off after the high side transistor 1402 is turned off. After a delay time τι, the waveform 18 of the second figure is referred to. Similarly, when the signal IN is changed from the low level to the local level, the output of the inverted inverter 1202 is turned to the low level, so the driving signal LG outputted by the gate!2〇8 is turned to the low level, so the low side The transistor 1404 is turned off. At this time, the output of the inverter 12〇6 is turned from the low level to the high level, so that the driving signal UG outputted by the gate 1204 is turned to a high level, and the high side transistor 1402 is turned on. In other words, the high-side transistor 丨4〇2 must also be turned on after a delay time T2 after the low-side transistor 1404 is turned off. However, during the delay period, the output stage conducts the current I by the diode rectifier 1406 which is conventionally built in the lower side transistor 1404, and the diode rectifier 1406 of the transmission system has a high impedance. Therefore, the delay will cause some loss of efficiency. In order to maximize the power efficiency, it is important to appropriately switch the on-times of the high-side and low-side transistors 1402 and 1404. In the known art, a digital counter is used to optimize the delay time. For example, the control method for reducing the substrate conduction and the reverse recovery loss proposed by the US Patent No. 6,396,250 (control method to reduce 1297976 body diode). Conduction and reverse recovery losses)" However, such a digital adjustment method is limited. For example, only N><2ns(N=l, 2, 3,...) can be adjusted, if the delay time is not within the adjustment range, For example, 3ns, you can't achieve optimization. Therefore, a driving circuit and method capable of optimizing the switching timing of the high-side and low-side transistors are preferable. SUMMARY OF THE INVENTION One object of the present invention is to provide a driving circuit and method applied to a voltage converter. According to the present invention, a driving circuit and method for applying a voltage converter includes: generating a first driving signal and a second driving signal according to a first control signal and a second control signal to drive a high side switch of the voltage converter And a low side switch, and controlling a delay of the first and second driving signals by a first signal, a second signal, the first and second control signals, the first signal being the first driving signal or a signal having the same phase as the first driving signal, the second signal being the second driving signal or a signal having the same phase as the second driving signal, when the delay of the first or second driving signal is too short Extending a delay time of the first or second driving signal when the working periods of the first and second driving signals overlap, and when the delay of the first or second driving signal is too long, the first and second When the non-working periods of the driving signals overlap, the delay time of the first or second driving signals is shortened. 1297976 [Embodiment] The third diagram is a synchronous buck converter 20 to which the present invention is applied, wherein the driving circuit 22 outputs the driving signals UG and LG to the output stage 24 switching switches SW1 and SW2 to convert the input voltage Vin into an output voltage Vout. Supply to the load RL. In the driving circuit 22, the gate 2202 is connected to the control signal U and the adjustment signal 0U, and the output signal Sa is output to the driver 2208 to generate the driving signal UG to drive the switch SW1, and the gate 2206 is connected to the control signal L and the adjustment signal 0L. The output signal Sb is output to the driver 2210 to generate the driving signal LG to drive the switch SW2. The phase lock circuit 2204 outputs the adjustment signal 0U according to the voltage signal PH, the driving signal LG, the control signals U and L on the phase node 2402. 0L. Since the voltage signal PH and the phase of the driving signal UG are almost exactly the same, in this embodiment, the voltage signal PH is used instead of the driving signal UG to be connected to the phase locking circuit 2204. In other embodiments, the driving signal UG or the driving signal UG or A signal having the same phase as the drive signal UG is connected to the phase lock circuit 2204, and similarly, a signal having the same phase as the drive signal LG may be connected to the phase lock circuit 2204. The fourth figure is an embodiment of the phase lock circuit 2204 in the third figure, wherein the logic circuit 30 uses the inverse OR gate 3002 to connect the driving signal LG and the voltage signal PH to obtain the signal S1, and the driving signal LG and the voltage signal PH are also connected to the gate. 3004, to obtain the signal S2, and the gates 3006 and 3008 switch the switches 3204 and 3206 in the charging and discharging circuit 32 according to the signals S1 and S2 and the control signal U output signals S3 and S4, respectively, to generate the charging electric power VI by the charging and discharging capacitor 3210. The control current source 36 supplies a charging current ii to the charging and discharging circuit 40 according to the charging voltage VI, and the control signal switching switch 4002 generates the adjustment signal 〇u by the charging and discharging capacitor 4〇〇4. On the other hand, the anti-free and idle 3010 and 3012 generate the charging voltage V2 according to the signals S1 and % and the control signal [generating the signals S5 and S6 to the charging and discharging circuit 34, and the switching switches 34〇4 and 3406 generate the charging voltage VDD by the charging/discharging capacitor 341? The voltage control current source 38 supplies the charging current 12 to the charging and discharging circuit 42 according to the charging voltage V2, and the control signal U switches the switch 4202 to generate the adjustment signal OL by the charging and discharging capacitor 4204.
進一步將第四圖中用以產生調節信號OU的電路獨立 出來如第五圖所示。第六圖顯示驅動信號UG的延遲時 間過紐日$各仏麵時序圖。參照第三圖、第五圖及第六 二同在k間丨1 ¥ ’控制信號U由低準位轉高準位，如第 進:的波，5〇所7K，驅動信號UG及電壓信號PH仍為低 持言進如第二圖的波形52及54所示，驅動信號LG也維 及中如第六圖的波形56所示，因此及閘3006 及3〇〇8所輸出的信猙 及3206打開，充4均為低準位，所以開關3204 圖的波形60所示，心心，原來的錢準位，如第六 得開關4002打開，故二士號L由高準位轉低準位使 而產生的充電電流流源36根據充電電壓V1 加的準位電容4嶋充電，使調節信號 時，調節信號OU連到古圖的波形62所示。在時間t2 :為高準位以導通開關：位因動:=UG由低準位 位，然而，驅動信號 也轉為高準The circuit for generating the adjustment signal OU in the fourth figure is further separated as shown in the fifth figure. The sixth graph shows the delay time of the drive signal UG. Referring to the third, fifth and sixth two in the k-between 1 ¥ 'the control signal U is turned from the low level to the high level, such as the first: wave, 5 〇 7K, drive signal UG and voltage signal The PH is still low. As shown in waveforms 52 and 54 of the second figure, the drive signal LG also maintains the waveform 56 as shown in the sixth figure, and therefore the signals output by the gates 3006 and 3〇〇8. And 3206 is turned on, and the charge 4 is low level, so the waveform 60 of the switch 3204 is shown, the heart, the original money level, such as the sixth switch 4002 is turned on, so the second grade L is turned from the high level to the low level The charging current source 36 generated by the bit is charged according to the level capacitance 4 加 added by the charging voltage V1, and when the signal is adjusted, the adjustment signal OU is connected to the waveform 62 of the ancient figure. At time t2: high level to turn on the switch: bit shift: = UG is low level, however, the drive signal is also converted to high level
為网準位，這表示驅動信號UG 1297976 的延遲時間不足，由於驅動信號LG及電壓信號PH均為高 準位，所以及閘3008輸出的信號S4為高準位，如第六圖 的波形58所示，以導通開關3206使電流源3208對電容 3210放電，降低充電電壓VI的準位，進而讓電壓控制電 流源36輸出的充電電流II變小，延長對電容4〇〇4的充 電時間，使得下次在控制信號U由低準位轉為高準位後， 需要更長的延遲時間才能使驅動信號UG由低準位轉為高For the grid level, this means that the delay time of the driving signal UG 1297976 is insufficient. Since the driving signal LG and the voltage signal PH are both at a high level, the signal S4 output by the gate 3008 is at a high level, as shown in the waveform 58 of the sixth figure. As shown, the current switch 3208 is discharged to the capacitor 3210 by the conduction switch 3206 to lower the level of the charging voltage VI, thereby making the charging current II outputted by the voltage control current source 36 smaller, and prolonging the charging time of the capacitor 4〇〇4. So that after the control signal U is turned from the low level to the high level next time, a longer delay time is required to make the driving signal UG change from the low level to the high level.
準位。假如在下次控制信號U由低準位轉為高準位後，驅 動h號UG及LG的工作週期仍重疊時，重複上述步驟再次 對電容3210放電，降低充電電壓VI的準位，以延長驅動 信號UG的延遲時間，直至驅動信號UG與LG的工作週期 不重疊為止。 / 第七圖顯示驅動信號UG的延遲時間過長時各传號的 時序圖，其中波形7〇係控制信號U，波形72係驅^^號 UG，波形74係電壓信號PH，波形76係驅動信號J ^ 形78係及閘3006輸出的信號S3,波形80係充電電壓π =準位’波形82係調節信號OU。參照第三圖、第五固及 第七圖，在時間tl時，控制信號U由低準位轉為高準j立， =時驅動信號UG及電壓信號PH均為低準位，^動㈣ 準^高準位，因此及閘3006及3008所輸出的信號均 立，故開關3204及3206均打開，充電電壓n 盾 準Γ又控制信號L由高準位轉低準位使得開關 打開，因此電壓控制電流源36根據充電電壓n 的充電電流II開始對電容4004充電，使調節信號〇u 1297976 始上升。在時_時，驅動信號LG由高準位轉 ’此時調節信號0U仍未達到高準位，因此驅動 ^ UG及電壓信號PH仍為低準位，這表示驅動作 =遲時間過長，故及閘屬輸出的信號S3轉為高狗立 ¥通開關3204,使得電流源3202開始對電容321〇充電 以，高充電電壓V1的準位，進而增加充電電流u，加快 電容4004的充電，縮短驅動信號卯的延遲時間。假如在 I次控制信號u由低準位轉為高準位後，驅動信號1仍 …、法在驅動信號LG由高準位轉低準位時轉為高準位，重 I上述步驟再次對電容3210充電，提高充電電壓W的準 位，進一步縮短驅動信號UG的延遲時間，直至驅動信號 此在驅動仏號LG由高準位轉低準位時立即轉為高準位。 參照第四圖，同樣地當驅動信號LG的延遲時間過短， 使驅動信號UG還未從高準位轉為低準位，驅動信^^便 轉為高準位時，反及閘3〇1〇輸出高準位的信號通開 關3404，使電親3402對電容_充電，提高充電電^ 的準位，進而增加充電電流12,縮短調節信號〇 =位升到高準位的時間，以延長驅動信號LG的延遲時間一。 =驅動信號LG的延遲時間過長，使驅動信號此從高準曰位 為：準位後，驅動信號LG還未轉為高準位時，反及閘 私2輪出高準位的信號S6導通開關3406，使電流源34〇8 少。對電容3410放電’降低充電電壓V2的準位，進而減 ^電電流12 ’增加調節信號QL從低準位升到高準位的 、 从縮短驅動信號LG的延遲時間。 11 1297976 【圖式簡單說明】 第一圖係傳統的同步降壓式轉換器； 第二圖顯示第一圖中各信號的時序圖； 第三圖係應用本發明的同步降壓式轉換器； 第四圖係第三圖中鎖相電路的一個實施例； 第五圖係第四圖中用以產生調節信號0U的電路； 第六圖顯示驅動信號UG的延遲時間過短時各信號的 時序圖；以及 第七圖顯示驅動信號UG的延遲時間過長時各信號的 時序圖。 【主要元件符號說明】Level. If the duty cycle of driving h UG and LG overlaps after the next control signal U is turned from the low level to the high level, repeat the above steps to discharge the capacitor 3210 again, and lower the level of the charging voltage VI to extend the driving. The delay time of the signal UG is not until the duty cycle of the drive signal UG and LG does not overlap. / The seventh figure shows the timing chart of each mark when the delay time of the drive signal UG is too long, wherein the waveform 7 is the control signal U, the waveform 72 is the drive number UG, the waveform 74 is the voltage signal PH, and the waveform 76 is driven. Signal J^ is 78 and signal S3 is output from gate 3006. Waveform 80 is the charging voltage π = level 'waveform 82 is the adjustment signal OU. Referring to the third figure, the fifth solid and the seventh figure, at time t1, the control signal U is changed from the low level to the high level, and the = drive signal UG and the voltage signal PH are both low level, (4) The high-level position is correct, so the signals output by the gates 3006 and 3008 are all equal, so the switches 3204 and 3206 are both turned on, and the charging voltage n is shielded and the control signal L is turned from the high level to the low level to make the switch open. The voltage controlled current source 36 begins to charge the capacitor 4004 based on the charging current II of the charging voltage n, causing the adjustment signal 〇u 1297976 to rise. At time _, the drive signal LG is turned from the high level. At this time, the adjustment signal 0U has not yet reached the high level, so the drive UG and the voltage signal PH are still at a low level, which means that the drive is too late. Therefore, the signal S3 outputted by the gate is turned into the high dog switch 3204, so that the current source 3202 starts to charge the capacitor 321 ,, the level of the high charging voltage V1, thereby increasing the charging current u, and accelerating the charging of the capacitor 4004. Shorten the delay time of the drive signal. If the control signal u is turned from the low level to the high level after the I control signal u, the driving signal 1 is still, and the method turns to the high level when the driving signal LG is turned from the high level to the low level, and the step I is again The capacitor 3210 is charged to increase the level of the charging voltage W, and the delay time of the driving signal UG is further shortened until the driving signal is immediately turned to the high level when the driving signal LG is turned from the high level to the low level. Referring to the fourth figure, similarly, when the delay time of the driving signal LG is too short, the driving signal UG has not been changed from the high level to the low level, and the driving signal is turned to the high level, and the gate is turned on. 1〇 output high-level signal pass switch 3404, so that the electric pro 3602 charges the capacitor _, raises the level of the charging electric^, thereby increasing the charging current 12, shortening the time when the adjusting signal 〇= bit rises to the high level, The delay time of the drive signal LG is extended by one. = The delay time of the drive signal LG is too long, so that the drive signal is clamped from the high level: after the level, the drive signal LG has not turned into the high level, and the signal S6 of the high level of the brakes is reversed. The switch 3406 is turned on to make the current source 34 〇 8 small. Discharging the capacitor 3410 reduces the level of the charging voltage V2, and further reduces the electric current 12' to increase the delay time of the shortening of the driving signal LG from the low level to the high level. 11 1297976 [Simple diagram of the diagram] The first diagram is a conventional synchronous buck converter; the second diagram shows the timing diagram of each signal in the first diagram; the third diagram is the synchronous buck converter to which the present invention is applied; The fourth figure is an embodiment of the phase lock circuit in the third figure; the fifth figure is the circuit for generating the adjustment signal 0U in the fourth figure; the sixth figure shows the timing of each signal when the delay time of the drive signal UG is too short; FIG. 7 and FIG. 7 are timing charts showing signals when the delay time of the drive signal UG is too long. [Main component symbol description]
10 同步降壓式轉換器 12 驅動電路 1202 反相器 1204 及閘 1206 反相器 1208 及閘 1210 反相器 1212 驅動器 1214 驅動器 14 輸出級 1402 高位側電晶體 12 1297976 1403 相節點 1404 低位側電晶體 15 驅動信號UG的波形 16 電壓信號PH的的波形 17 驅動信號LG的波形 18 延遲時間的波形， 20 同步降壓式轉換器 22 驅動電路 2202 及閘 2204 鎖相電路 2206 及閘 2208 驅動器 2210 驅動器 24 輸出級 2402 相節點 30 邏輯電路 3002 反或閘 3004 及閘 3006 及閘 3008 及閘 3010 反及閘 3012 反及閘 32 充放電電路 3202 電流源10 synchronous buck converter 12 drive circuit 1202 inverter 1204 and gate 1206 inverter 1208 and gate 1210 inverter 1212 driver 1214 driver 14 output stage 1402 high side transistor 12 1297976 1403 phase node 1404 low side transistor 15 Drive signal UG waveform 16 Voltage signal PH waveform 17 Drive signal LG waveform 18 Delay time waveform, 20 synchronous buck converter 22 drive circuit 2202 and gate 2204 phase lock circuit 2206 and gate 2208 driver 2210 driver 24 Output stage 2402 phase node 30 logic circuit 3002 reverse gate 3004 and gate 3006 and gate 3008 and gate 3010 reverse gate 3012 reverse gate 32 charge and discharge circuit 3202 current source
13 1297976 3204 開關 3206 開關 3208 電流源 3210電容 34 充放電電路 3402 電流源 3404 開關 3406 開關 3408 電流源 3410 電容 36 電壓控制電流源 38 電壓控制電流源 40 充放電電路 4002 開關 4004 電容 42 充放電電路 4202 開關 4204 電容 50 控制信號U的波形 52 驅動信號UG的波形 54 電壓信號PH的波形 56 驅動信號LG的波形 58 信號S4的波形 60 充電電壓VI的波形 1297976 62 70 72 74 76 78 80 82 調節信號OU的波形 控制信號U的波形 驅動信號U G的波形 電壓信號ΡΗ的波形 驅動信號LG的波形 信號S3的波形 充電電壓VI的波形 調節信號0U的波形 1513 1297976 3204 Switch 3206 Switch 3208 Current Source 3210 Capacitor 34 Charge and Discharge Circuit 3402 Current Source 3404 Switch 3406 Switch 3408 Current Source 3410 Capacitor 36 Voltage Control Current Source 38 Voltage Control Current Source 40 Charge and Discharge Circuit 4002 Switch 4004 Capacitor 42 Charge and Discharge Circuit 4202 Switch 4204 Capacitor 50 Control signal U waveform 52 Drive signal UG waveform 54 Voltage signal PH waveform 56 Drive signal LG waveform 58 Signal S4 waveform 60 Charging voltage VI waveform 1297976 62 70 72 74 76 78 80 82 Adjustment signal OU Waveform control signal U waveform waveform signal UG waveform voltage signal ΡΗ waveform drive signal LG waveform signal S3 waveform charge voltage VI waveform adjustment signal 0U waveform 15