JP2573821B2 - Voltage conversion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a monolithic voltage conversion circuit of a switched capacitor type using a field effect transistor (hereinafter abbreviated as FET) as a switching element.

(Prior art)

As for the voltage conversion circuit using the switched capacitor method, a circuit as shown in FIG. 1 is conventionally known. Here, 101, 102 and 103 are N-channel MOSFETs (hereinafter N
Abbreviated as MOS. ), 104 are P-channel MOSFETs (hereinafter PM
Abbreviated as OS. ), 105, 106 are level converters, 107 is a pump-up capacitor, 108 is a smoothing capacitor, 109, 1
10,111 are the switching transistors (101 to 104)
, A complementary MOSFET (hereinafter abbreviated as CMOS) inverter that drives the gate of the CMOS.

FIG. 1 is an example of a double booster circuit, and its operation will be briefly described below. First, the switching transistor 101,
In a state where 104 is turned on and 102 and 103 are turned off, the capacitor 107 is charged with the power supply voltage (−V _IN ) (charging period; corresponding to period B in FIG. 2). Next, the switching
The state of the transistor is inverted, 101 and 104 are turned off, and 10
When 2,103 is turned on, the potential of one end 115 of the capacitor 107 for the -V _IN, and the other end 113 is -2 V _IN becomes the electric charge stored in the charging period, the potential to charge the capacitor 108 through the NMOS 102 (the pump Up period; corresponds to period A in FIG. 2). By alternately repeating the above two states (charging period and pump-up period), the input power supply voltage _VIN is doubled.

Here, when the two states are switched by a single-phase clock, the switching transistors do not instantaneously invert but actually have a delay time.
At the timing when both 102 turn on, the charge stored in the capacitor 108 flows back to the input side at that timing, causing power loss. Therefore, it is generally known to use a two-phase or three-phase multi-phase clock to control the switching transistor so that the above-described on-on timing does not occur due to the delay time (Japanese Patent Publication No. 58-46948). ). FIG. 2 shows an example of a three-phase clock waveform. The waveforms of CL1, CL2, and CL3 shown here are respectively applied to CL1, CL2, and CL3 shown in FIG. The operation will be described. First, at t = t ₀ , the gate potential 116 of the NMOS 101 is at a high level (GND), and the gate potential 117 of the NMOS 101 is at a low level (−).
V _IN ). That is, 101 is in the on state, 102 is in the off state, and the potential of 115 is at a high level. Next, pump up, but at this time, the potential of 115 is inverted before 101 is turned off,
When the potential of 113 is pumped up to -2 V _IN , the charge on capacitor 107 flows back through 101. So here 10
CL is set so that the potential of 115 is inverted after 1 is surely turned off.
A phase difference of (t ₂ -t ₁ ) is provided between 1 and CL3. One more
If 102 turns on before the potential of 15 reverses, capacitor 1
Since the electric charge of 08 flows backward through 102, a phase difference of (t ₃ -t ₂ ) is provided between CL3 and CL2 to prevent it. This charge backflow also occurs when switching from the pump-up period to the charging period.
Is turned off, then the potential of 113 is returned to −V _IN , and then 101
Turn on. That is, as shown in FIG. 2, CL at t = t ₄
Launched a 2, launched a t = t ₅ in CL3, it is necessary to'll provided with a phase difference as that at t = t _6'll fall a CL1.

As a method for providing a phase difference between these clock signals,
As shown in FIG. 3, a method comprising a binary flip-flop circuit and a delayed flip-flop circuit is generally known (Japanese Patent Publication No. 58-46948). FIG. 4 shows this timing chart. In Figure 3, the clock signal CL _O is ,, binary flip-flop circuit 301
Through 308, the frequency is divided up to the clock signal of the required frequency. Further, when the signal is input to the delayed flip-flop circuits 309 and 310 using the output BF1 of 301 as a clock, the output becomes DF1Q of FIG.
And DF2Q. As shown in FIG.
When input to the ND gate 311 and the OR gate 312, the output will be like NAND and OR, respectively, as shown in FIG. Therefore, when NAND, OR and DF1Q are extracted from this output, CL1, C in FIG.
L2 and CL3 timing can be created.

However, this method has the following disadvantages. In a switched-capacitor voltage conversion circuit, its performance (how much output current can be taken out) depends on the amount of electric charge charged to the capacitor. That is, the longer the charging period, the higher the performance. However, as can be seen from FIG. 2, in this method, in one cycle, t ₁ to
t ₃ and t ₄ ~t time of ₆ becomes a loss time without contributing to charging. To this loss time as small as possible, as seen from FIGS. 3 and 4, by increasing the frequency of CL _O, it must be further added that amount binary Lee flip-flop circuit. Increasing the frequency leads to an increase in current consumption, which leads to a reduction in efficiency, which is an important characteristic of the voltage conversion circuit. Also, adding a binary flip-flop circuit not only complicates the circuit but also increases the chip area and cost, considering that it is configured on a monolithic IC.

〔Purpose〕

The present invention solves such a problem, and an object of the present invention is to realize a low-cost, high-performance, high-efficiency voltage conversion circuit.

〔Overview〕

The voltage conversion circuit according to the present invention employs a switched-capacitor system controlled by a multi-phase clock generated by using a transient response time of a transistor.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

FIG. 5 shows an example of a timing generation circuit for a voltage conversion circuit according to the present invention. Where 501, 503, 505 are PMOS, 502, 50
4,506 is an NMOS, 507 is a NAND gate, and 508 is an OR gate. Amplification factor of the PMOS501 (hereinafter abbreviated as beta _P.) Is NMOS5
02 is made larger than β _N , and these two transistors constitute an inverter. Regarding the inverter constituted by the PMOS 503 and the NMOS 504, the β _N of the NMOS 504 is larger than the β _{P of the} PMOS 503, contrary to the inverter.

FIG. 6 is a timing chart of the circuit shown in FIG. The signal CL _A applied to the point _A is a PMOS 501 and an NMOS 50.
Is output as CL _B by inverter composed by 2. This is because, as described above, β _P of the PMOS
_Since it is larger than _N , the rise is faster than the fall. Output waveform CL _C of the inverter constituted by the PMOS503 and NMOS504 Conversely earlier than the rise is falling. The signals CL _B and CL _C thus obtained are applied to the gates of the PMOS 505 and the NMOS 506, respectively. PMOS505
And output waveform C of the inverter composed of NMOS 506
Rise of L _D is, CL _C falls earlier than CL _B (i.e. after the NMOS506 is turned off, PMOS505 begins turns.) Therefore, the timing of PMOS505 is turned on (CL _C threshold V _th waveform is PMOS505 of Timing). Considering the falling edge of CL _{D in} the same way, NMO
S506 at the timing of turning on, CL _D is inverted. Thus, it is possible to obtain a signal CL _D delayed a predetermined time from the input signal CL _A. Further through the same circuit the CL _D as the input signal, the signal CL _G delayed or certain time CL _D is obtained. The signals CL _A , CL _D and CL _G thus obtained correspond to the signals BF8, DF1Q and DF2Q of FIG. 4, respectively. Therefore, signals CL _A and CL _G are supplied to NAND gate 507 and O
If you enter the R gate 508, signal CL _H and CL _I corresponding to the signal NAND and OR of Fig. 4 is obtained. Like this
According to the embodiment shown in FIG. 5, the timing shown in FIG. 2 can be generated without using a multi-stage flip-flop circuit and a high-frequency clock signal.

In FIG. 6, the rising phase difference τ ₁ between the signals CL _A and CL _D can be freely changed by changing the falling time of the signal CL _B (that is, changing β _N of the NMOS 502) as can be seen from the figure. Can be set to Similarly, for the falling phase difference τ ₂ , by changing β _P of the PMOS 503,
Can be set freely. That is, τ ₁ and τ ₂ can be set arbitrarily and independently only by changing the β of the transistor (without adding a transistor and changing the frequency).

Next, in this embodiment, The reason for this is described. Considering the operation described above, However, there is no problem in securing the phase differences τ ₁ and τ ₂ . However, in such a case, in order to secure a phase difference, for the signals CL _B and CL _{C in} FIG. 6, the falling edge of CL _C should be matched to the falling edge of CL _B , and the rising edge of CL _B should be matched to the rising edge of CL _C. There must be. Then, the gate potential of the PMOS 505 and the gate potential of the NMOS 506 change at the same time and slowly, so that both are turned on, and a through current flows between the power supplies through the two transistors. Therefore, in the present embodiment, the difference in β is provided as described above, and the timing of turning on both the PMOS 505 and the NMOS 506 is minimized. In the voltage conversion circuit shown in FIG. 1, the switching transistors 101 to 104 are usually made as low as possible in order to lower the output impedance. As described above, the power lost through the NMOSs 101 and 102 can be prevented by switching at the timing shown in FIG. However, PMOS104 and NMOS103
Cannot suppress the through current of the inverter composed of In particular, since the transistors 103 and 104 are low-resistance transistors, a large through current may flow in some cases, resulting in an increase in current consumption and a deterioration in efficiency.
Therefore, the gate of the inverter constituted by the PMOS 104 and the NMOS 103 is driven by the method described with reference to FIG. 5 (the transistors 505 and 506 in FIG.
The outputs H and I in FIG. 5 are connected to CL1 and CL2 in FIG. 1 instead of 104 and 103), and the through current can be reduced while the timing in FIG. 2 is maintained. Become.

In the embodiment, the timing generation circuit has been described by taking the double boosting circuit as an example. However, this can be applied to an n-fold boosting circuit such as a triple, quadruple or the like. Needless to say, the present invention can be applied to a step-down circuit that operates on the same principle as the step-up circuit.

〔effect〕

As described above, according to the present invention, in order to divide a signal into two systems and drive two transistors constituting an inverter with each signal, the phase difference between clock signals used for switching can be freely set with high accuracy. The dead time required to prevent power loss (second
T ₁ ~t ₃ and t ₄ ~t time ₆₎ can be made as small as possible in the figure, thus it is possible to increase the capacity of the step-up (or down). In addition, the circuit can share the clock generating circuit and the switching circuit of the capacitor, and does not require a multi-stage frequency dividing circuit or a flip-flop circuit. This not only simplifies the circuit, but also reduces the chip area and cost when configuring the circuit on a monolithic IC. Further, according to the present invention, since a clock signal having a frequency higher than the frequency of the clock signal required for switching is not required, current consumption can be reduced. This leads to an increase in efficiency.

Further, since a through current of the switching transistor can be prevented, high efficiency can be achieved.

[Brief description of the drawings]

FIG. 1 is an example of a voltage conversion circuit using a switched capacitor method. FIG. 2 is an example of the time chart of FIG. FIG. 3 shows an example of a conventional timing generation circuit. FIG. 4 is a time chart of FIG. FIG. 5 is an example of a timing generation circuit according to the present invention. FIG. 6 is a time chart of FIG. Hereinafter, the meaning of the symbols in each drawing is shown. 101 to 103 NMOS 104 PMOS 105 and 106 Level converters 107 and 108 Capacitors 109 to 111 Inverters 301 to 308 Binary flip-flop circuits 309 and 310 Delayed flip-flop circuits 311 NAND gates 312 …… OR gate 501,503,505 …… PMOS 502,504,506 …… NMOS 507 …… NAND gate 508 …… OR gate

Claims (1)

(57) [Claims] 1. A voltage conversion circuit for converting a first voltage to a second voltage by switching connection of a capacitor, wherein a clock signal input terminal and an input terminal are connected to the clock signal input terminal, and β _P > β _N. A first inverter having the following relationship, a first transistor of a first conductivity type connected between a first power supply terminal and one end of the capacitor and driven by the first inverter, and an input terminal: A second inverter connected to a clock signal input terminal and having a relationship of β _P <β _N; a second conductive element connected between one end of the capacitor and a second power supply terminal and driven by the second inverter; A third transistor having an input terminal connected to one end of the capacitor and having a relationship of β _P > β _N, and a third transistor connected between the first power supply terminal and the output terminal. A third transistor of the first conductivity type connected by the third inverter, a fourth inverter having an input terminal connected to one end of the capacitor and having a relationship of β _P <β _N, and the output terminal A fourth transistor of a second conductivity type connected between the second power supply terminal and the second power supply terminal and driven by the fourth inverter; a clock signal input to the clock signal input terminal; A logic circuit for generating a multi-phase clock signal based on the output signal; and switching control means for connecting the other end of the capacitor to one of the second power supply terminal and the load based on the multi-phase clock signal. A voltage conversion circuit characterized by the above-mentioned.