1295910 • 九、發明說明： -【發明所屬之技術領域】 本發明係有關於一種佈線方法及系統，更詳而言之， 係有關於一種應用於佈設在電路板上之具球格狀陣列 (Bal 1 Grid Array，BGA)佈線區域之之電路圖騰之佈線 方法及系統。 【先前技術】 鲁 一般’需對印刷電路板進行佈線設計以使設於該印刷 包路板之各元件電性連結並發揮功能。以筆記型電腦之電 路板為例，其尺寸因應電子裝置之微型化趨勢而越來越 小，隨之於該電路板上可進行佈線之空間即十分有限，特 ，別地’係對於電路板之球格狀陣列（Ball Grid Array， _ BGA)之佈線區域而言，欲在如此狹小的空間内進行佈線 設計，難度可想而知。目前，於習知之佈線（Lay〇ut)設計 中，電子工程師係藉由各類佈線軟體程式（例如protel 麝軟體）來完成，一般係依據例如通孔/焊墊（Via/Pad)、通 -孔/線路（Via/Trace)以及線路/線路（Trace/Trace)等最 小間距要求的佈線規則及佈線狀況，於該BGA之佈線區域 上進行通孔（Via)設置及走線（Trace)佈設。 惟，上述佈線作法中，除了須符合佈線規則之最小間 距要求之外，並未對通孔的設置位置及數量進行規定，故 往往會發生如後的情形··因缺乏合理及系統性地佈局，通 孔之數量繁雜且無一定之設置規律，較雜亂無序，相對 地，佈線之空間利用度較低，因而會使得可佈線之空間受 19318 5 1295910 到限制，導致佈線密度較低。 ^上同時，因通孔之繁雜且無序，若需要對現有之佈線 仃5周整’勢必需依據佈線狀況對各通孔重新調整所設置之 位置，而該重新設置之工作量係與所涉及之通孔數=及= 置等密切相關，如此一來，無疑大幅地增加了工作旦、 而影響佈線效率。 里 、兵此外，上述佈線設計中，通孔的設定位置比較雜散舆 :久亂’而，設缝量也沒有較系統地規定，故各通孔整赢 性較差，更影響了電路圖騰之美觀。 月 ,▲因此，如何克服上述先前技術之缺失，進而提供一種 b毹越之佈線方法以提供靈活度較佳的佈線空間並捭 加可佈線空間’從而提高設計效率且降低成本，同時，曰更 可提升通孔之整齊性及美觀度，實為目前所欲亟待 問題。 、 【發明内容】 繁於上述習知技術之缺失，本發明之主要目的係在於 提供-種佈線方法及系統，俾提供靈活度較佳的佈線空間 並增加可佈線空間。 本I月之5目的係在於提供一種佈線方法及系 統，俾提高佈線效率及降低成本。 本么月之再目白勺係在於提供-種佈線方法及系 統，俾使通孔整齊有序，提升美觀度。 為達上述主要目的及其他目的，本發明係揭露一種佈 、方法剌以於—電路板上佈設具複數焊墊（Pad)、通 19318 6 1295910 •孔（Via)以及線路（Trace)之電路圖騰，其中，該電路圖騰 '係預設有佈線規則，該佈線方法係包括：依據該佈線規 則，設置該通孔於同一基準線上，且令該通孔與相對應之 焊墊距離皆為等長；以及依據該電路圖騰上之線路佈設狀 況以及該佈線規則，調整該線路之位置，並相對地於該基 準線上調整該通孔之位置。 於本發明之一實施例中，前述該佈線方法中的電路板 、鲁係具球格狀陣列（Ball Grid Array，BGA)之佈線區域。 該佈線規則係至少包括該通孔與焊墊之間及通孔與 線路之間必須符合最小間距之要求，且線路間亦必須符合 最小間距之要求。 ^ ,對應上揭之佈線方法，本發明復揭露一種佈線系統， 係用以於一電路板上佈設具複數焊墊（pad)、通孔（Vh) 以及線路（Trace)之電路圖騰，其中，該電路圖騰 ^佈線規則，該佈線系統係包括··用以依據該佈線規則口， .又置口亥通孔於同一基準線上，且令該通孔與相對應之焊墊 •距離皆為等長之設置模組；以及用以依據該電路圖騰上之 線路佈设狀況以及該佈線規則，調整該線路之位置，並相 對地於忒基準線上調整該通孔位置之調整模組。 紅上所述，藉由本發明之佈線方法，係依據佈線規則 及線路佈設狀況，周詳考慮到通孔與走線、通孔與焊墊及 f路間之最小間距要求’調整通孔之位置俾提供靈活度較 丄^佈線工間並增加可佈線空間，相對地，更提高了佈線 效率並降低成本，又可提升該複數通孔 之整齊性及美觀 19318 7 1295910 ‘度’以達前述之所有目的。 . 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容_ 瞭解本發明之其他優點及功效。本發明亦可藉由其^不同 -的具體實施例加以施行或應用，本說明書中的各項細節亦 -可基於不同的觀點與應用，在不悖離本發明之精 ' 各種修飾與變更。 進仃 ^ '青茶閱第1圖，其係顯示本發明之佈線方法之較佳實 施例之流程示意圖。本發明之佈線方法係應用於一具球格 狀陣列（Ball Grid Array，BGA)之佈線區域之電路板， 以於該電路板上佈設具複數焊墊（pad)、通孔（Vh)以及線 路（Trace)之電路圖騰，其中，f亥電路圖騰係預設有佈線 規則。於本實施例中，該電路板係應用於例如筆記型電 腦、個人隨身電腦（Handy Pers〇nal c〇mputer，及 泰手持智慧裝置等電子農置中，但並不卩此為？艮。如圖所 •示，首先於步驟S101，讀取該電路板之各焊墊之位置訊 息。於本實施例中，該焊墊之數量及焊墊間之間距係因應 該BGA之類型而具差異性。隨後進至步驟si〇3。 、於步驟S103,依據該佈線規則，設置該通孔於同一 基準線上，且令該通孔與相對應之焊墊距離皆為等長。其 中，該佈線規則係至少包括該通孔與焊墊之間必須符合最 J間距之要求，於本貫施例中，該通孔與焊墊之最小間距 係例如為6密耳（mil);並且，為滿足通孔與相對應之焊 19318 8 1295910 墊距離等長之要求，於本實、^ ^ ^ r ^ , 貝也例中，该通孔係形成於相鄰 知墊之幾何中心線上。如肤， 如此即可確定該通孔之設置範 圍。隨後進至步驟S105。 於步驟S1G5’讀取該電路圖騰上之線路佈設狀況， 隨後進至步驟S107。 >於步驟S1G7,依據該電路圖騰上之線路佈設狀況以 及該佈線㈣，調整該線路之位置，並㈣地於該基準線 .鲁上調㈣通孔之位置。#中，該線路規㈣至少指該通孔 與焊墊之間及該通孔與線路之間必須符合最小間距之要 求，且線路間亦必須符合最小間距之要求。於本實施例 中，該通孔與焊塾之間及該通孔與線路 < 間的最小間距係 例如為6密耳（mil)，該線路間之最小間距係為5密耳 (mi 1) 〇 再請參閱第2圖，係為本發明之佈線系統丨之較佳實 施例之方塊示意圖。如圖所示，於本實施例中，該佈線系 泰統1係應用於一具BGA之佈線區域20之電路板2，以供 -於該電路板2上佈設具複數焊墊、通孔以及線路之電路圖 騰’該佈線系統1係包括設置模組1 〇以及調整模組1 2。 該設置模組10係用以依據該電路板2之BGA佈線區 域20及佈線規則，設置該通孔於同一基準線上，且令該 通孔與相對應之焊墊距離皆為等長。其中，該佈線規則係 至少包括該通孔與焊墊之間必須符合例如為6m丨1之最小 間距之要求。必該調整模組12係用以依據該電路圖騰上 之線路佈設狀況以及該佈線規則，調整該線路之位置，並 9 19318 1295910 相對地於該基準線上調整該通孔之位置。豆 =少包括該通孔與焊墊之間及該通孔與線二^ :付口例如為6mil之最小間距之要求，且線路 合例如為5mil之最小間距之要求。 肩付1295910 • IX. Description of the invention: - [Technical field to which the invention pertains] The present invention relates to a wiring method and system, and more particularly to a ball grid array applied to a circuit board ( Bal 1 Grid Array, BGA) The wiring method and system of the circuit totem of the wiring area. [Prior Art] Lu generally requires wiring of the printed circuit board so that the components provided on the printed circuit board are electrically connected and function. Taking the circuit board of a notebook computer as an example, the size of the electronic device is smaller and smaller according to the trend of miniaturization of the electronic device, and the space available for wiring on the circuit board is very limited, and the other is for the circuit board. In the wiring area of the Ball Grid Array (_BGA), it is difficult to design the wiring in such a small space. At present, in the Lay〇ut design, the electronic engineer is completed by various wiring software programs (such as protel software), which are generally based on, for example, via/pad (via/pass). The wiring rules and wiring conditions required for the minimum pitch such as the via/route (Via/Trace) and the line/route (Trace/Trace) are performed on the wiring area of the BGA through the Via setting and the trace layout. However, in the above wiring method, in addition to the minimum spacing requirements of the wiring rules, the position and number of through holes are not specified, so the situation may occur as follows. · Due to lack of reasonable and systematic layout The number of through holes is complicated and there is no certain setting rule, which is more disorderly and disorderly. In contrast, the space utilization of the wiring is low, so that the space for wiring can be limited by 19318 5 1295910, resulting in low wiring density. At the same time, due to the complicated and disordered through-holes, if it is necessary to re-adjust the positions of the existing through-holes according to the wiring condition, the existing wiring must be re-adjusted according to the wiring condition, and the resetting workload is The number of through holes involved = and = are closely related, which undoubtedly greatly increases the working efficiency and affects the wiring efficiency. In addition, in the above wiring design, the setting position of the through hole is relatively boring: long time chaos, and the amount of seam is not systematically specified, so the through hole of each through hole is poor, which affects the circuit totem. Beautiful. Month, ▲ Therefore, how to overcome the above-mentioned lack of prior art, and thus provide a wiring method to provide a more flexible wiring space and add routable space 'to improve design efficiency and reduce costs, at the same time, It can improve the tidyness and aesthetics of the through hole, and it is really a problem that is currently desired. SUMMARY OF THE INVENTION The main object of the present invention is to provide a wiring method and system that provides a flexible wiring space and increases wiring space. The purpose of this month is to provide a wiring method and system to improve wiring efficiency and reduce cost. The re-emphasis of this month is to provide a kind of wiring method and system, so that the through holes are neat and orderly, and the appearance is improved. In order to achieve the above main purpose and other objects, the present invention discloses a cloth and a method for laying a circuit pad with a plurality of pads (Pad), 19318 6 1295910, a hole, and a trace. The circuit totem system is pre-configured with a wiring rule. The wiring method includes: according to the wiring rule, the through hole is disposed on the same reference line, and the distance between the through hole and the corresponding pad is equal. And adjusting the position of the line according to the circuit layout condition on the circuit totem and the wiring rule, and adjusting the position of the through hole relative to the reference line. In an embodiment of the invention, the circuit board in the wiring method and the wiring area of the Ball Grid Array (BGA) are used. The wiring rule includes at least the requirement of a minimum spacing between the via and the pad and between the via and the line, and the line must also meet the minimum spacing requirement. According to the wiring method of the above, the present invention discloses a wiring system for laying a circuit totem with a plurality of pads, through holes (Vh) and traces on a circuit board, wherein The circuit totem ^ wiring rule, the wiring system includes · according to the wiring rule mouth, and the hole is placed on the same reference line, and the through hole and the corresponding pad and distance are equal a long setting module; and an adjustment module for adjusting the position of the line according to the circuit layout condition of the circuit totem and the wiring rule, and adjusting the position of the through hole relative to the 忒 reference line. According to the wiring method of the present invention, the minimum spacing between the through hole and the trace, the through hole and the pad, and the f path is required to be adjusted according to the wiring rule and the wiring layout condition. Provides flexibility to the wiring room and increases the wiring space. In contrast, it improves the wiring efficiency and reduces the cost, and improves the uniformity and beauty of the plurality of through holes. 19318 7 1295910 'degrees' to achieve all of the foregoing purpose. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can understand the other advantages and effects of the present invention. The present invention may be embodied or applied by the specific embodiments of the invention, and the details of the present invention may be variously modified and modified without departing from the spirit and scope of the invention. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The wiring method of the present invention is applied to a circuit board of a wiring area of a Ball Grid Array (BGA), so as to have a plurality of pads, vias (Vh) and lines on the circuit board. (Trace) circuit totem, in which the fhai circuit totem system is pre-set with wiring rules. In this embodiment, the circuit board is applied to, for example, a notebook computer, a personal portable computer (Handy Pers〇nal c〇mputer, and a Thai handheld smart device, etc., but this is not the case. In the first step, in step S101, the position information of each pad of the circuit board is read. In this embodiment, the number of the pads and the distance between the pads are different due to the type of BGA. Then, proceeding to step si〇3, in step S103, according to the wiring rule, the through hole is disposed on the same reference line, and the distance between the through hole and the corresponding pad is equal. The method includes at least a requirement that the through hole and the pad must meet a maximum J pitch. In the present embodiment, the minimum distance between the through hole and the pad is, for example, 6 mils; and The hole and the corresponding welding 19318 8 1295910 pad distance requirements are the same length, in the real, ^ ^ ^ r ^, shell also in the case, the through hole is formed on the geometric center line of the adjacent known mat. Such as skin, so The setting range of the through hole can be determined. Then, the flow proceeds to step S105. Step S1G5' reads the line layout condition on the circuit totem, and then proceeds to step S107. > In step S1G7, according to the circuit layout condition on the circuit totem and the wiring (4), the position of the line is adjusted, and (4) The reference line. Lu is up (4) the position of the through hole. In the #, the line gauge (4) at least means that the minimum spacing between the through hole and the pad and between the through hole and the line must be met, and the line must also meet The minimum spacing between the through holes and the pads and the minimum spacing between the through holes and the wires is, for example, 6 mils, and the minimum spacing between the lines is 5 The mil (mi 1) 〇 again refers to the second diagram, which is a block diagram of a preferred embodiment of the wiring system of the present invention. As shown in the figure, in the present embodiment, the wiring is a system of the Thai system 1 The circuit board 2 of the wiring area 20 of a BGA is provided for the circuit board 2 to be provided with a circuit pad with a plurality of pads, through holes and lines. The wiring system 1 includes a module 1 and a mode adjustment module. Group 1 2. The setting module 10 is used to be based on the electricity The BGA wiring area 20 of the circuit board 2 and the wiring rule are disposed on the same reference line, and the distance between the through hole and the corresponding pad is equal. The wiring rule includes at least the through hole and the through hole. The pads must meet the minimum spacing of, for example, 6 m 丨 1. The adjustment module 12 is used to adjust the position of the line according to the wiring layout on the circuit totem and the wiring rules, and 9 19318 1295910 Relatively adjusting the position of the through hole on the reference line. The bean = less includes the requirement between the through hole and the pad, and the through hole and the wire 2: the minimum distance of the wire is, for example, 6 mil, and the line is, for example, 5 mil minimum spacing requirements. Shoulder payment
猎由上述佈線方法及系統’係透過將各通孔設置於 令其與相對應之烊墊距料為#長之同—基準線上，且依 據佈線規則及線路佈設狀況，合理調整線路及對應通孔^ :置’以於滿足佈線規則之最小間距之要求下，盡可能節 省佈線工間’藉以提供靈活度較佳的佈線空間並增加可佈 線空間，俾提高佈線效率及降低成本，更可提升該複數通 孔之整齊性及美觀度。 具體實施你丨： 凊麥閱第3圖，其係顯示本發明之佈線方法之電子元 件結構模型之示意圖。 於本實施例中，該電路板係具球格狀陣列（BaU Grid Array，BGA)之佈線區域，該佈線區域具有複數規則排列 之知墊。於本實施例中，係將該通孔設置於同一基準線 上，且令該通孔（以V卜V2標示）與相對應之焊墊（以A1、 A2標不）距離皆為等長，並依據佈線規則之通孔與焊墊所 允淬的最小間距要求來確定該通孔之位置範圍。具體而 吕，假設佈線規則之通孔與焊墊所允許的最小間距係為6 密耳（mil)，則該通孔V1至焊墊A1及A2的間距χι、χ2 最小係為6密耳（mil);若焊墊之半徑係為Η，通孔之半 徑係為r2(令焊墊和通孔都為一點，即焊墊的半徑『1 = 〇， 19318 10 1295910 通孔半徑如），焊塾A1與通孔V1之間距為χ1，而相鄰 焊墊之間距係為a，即A1至A2之距離=A1至M之距離=a， 此日守’该通孔VI至焊墊A1及B1之連線v〇的最小間距係 1 |36 十2 為·· V0V1 丨min: 藉此’可確定各通孔之位置範圍。 接著二依據相鄰通孔V1及V2間之走線之線寬(令該 走線之線寬係為w)而調整通孔V1及V2之位置。 百先假設通孔V1、V2至焊墊A1、A2之間距各別係為 XI及X2，則相鄰通孔V1及V2之間距係為： V1V2 = ^ 2The above-mentioned wiring method and system's are arranged by placing the through holes so that they are spaced from the corresponding mats, which are the same as the reference line, and according to the wiring rules and the layout of the lines, the lines and corresponding passages are reasonably adjusted. Hole ^ : Set to meet the minimum spacing requirements of the wiring rules, save the wiring space as much as possible 'to provide more flexible wiring space and increase the wiring space, improve wiring efficiency and reduce costs, but also improve The uniformity and aesthetics of the plurality of through holes. DETAILED DESCRIPTION OF THE INVENTION: FIG. 3 is a schematic view showing an electronic component structure model of the wiring method of the present invention. In this embodiment, the circuit board has a wiring area of a BaGe Array (BGA), and the wiring area has a plurality of regularly arranged pads. In this embodiment, the through holes are disposed on the same reference line, and the distance between the through holes (indicated by V bu V2) and the corresponding pads (labeled by A1 and A2) are equal. The position range of the through hole is determined according to the minimum spacing requirement of the through hole and the pad to be quenched by the wiring rule. Specifically, assuming that the minimum spacing allowed by the vias of the wiring rules and the pads is 6 mils, the pitch of the vias V1 to pads A1 and A2 χι, χ2 is a minimum of 6 mils ( Mil); if the radius of the pad is Η, the radius of the through hole is r2 (so that the pad and the through hole are both a point, that is, the radius of the pad 11 = 〇, 19318 10 1295910 through hole radius, for example), welding The distance between the 塾A1 and the through hole V1 is χ1, and the distance between the adjacent pads is a, that is, the distance from A1 to A2=the distance from A1 to M=a, this day s' the through hole VI to the pad A1 and The minimum spacing of the connection of B1 to v〇 is 1 | 36. Twelve is ··· V0V1 丨min: This can be used to determine the position range of each through hole. Next, the positions of the via holes V1 and V2 are adjusted according to the line width of the trace between the adjacent via holes V1 and V2 (the line width of the trace is w). Assuming that the distance between the vias V1 and V2 to the pads A1 and A2 is XI and X2, the distance between adjacent vias V1 and V2 is: V1V2 = ^ 2
’α、 2 fa) UJ 5-&6<xl< V〇^ 36?6 <x2< Va2 -36 但同時 依據該佈線規則之通孔與走線所允許的最小間距係為 密耳（mU)的要求，則相鄰通孔π及V2走過該線寬的最 小間距 r2+wl+w+w2+r2|min=2r2 + 12+w=i2+w(令 r2 = 0)。 ,通過該電子元件之焊墊及通孔之位置資料，應用程式 對其進行分析，在滿足^，“的條件下，自動調整w孔， v2孔，使其間距離為12+w，以達到走線的最佳尺寸。 請-併參閱f 4及帛5圖，其係顯示透過本發明之佈 線方法之應用實施例。 如圖所示，複數通孔Π、V2及V3係設於對應走線平 行之相鄰焊墊A1及B1、A2及B2、A3及β3及A4及β4 的幾何_心線上，且與該通孔”及V2、V3間各別佈 設有走線Π 1T2。必需注意的是’此時，該複數通孔係 19318 11 1295910 完全符合佈線規則之通孔與焊墊及通孔與走線之最小間 距要求。 為有效利用走線空間，且必需符合佈線規則之例如通 孔/焊墊（Via/Pad)、通孔/線路（Via/Trace)以及線路/線 路（Trace/Trace)等最小間距要求，若要求於該走線T2 旁復佈設一走線Τ3，則可調整該走線Τ2及Τ3之間距， 並1該通孔V2及V3以遠離走線Τ2及Τ3之方向而移動， 同日寸，通孔VI亦因受到通孔V2的臨近而與通孔V2作同 >方向之移動調整，俾使焊墊（Pad)、通孔（Via)以及線路 (Trace)均符合佈線規則之間距要求。 、’上所述本务明之佈線方法及系統，係依據佈線規 則，將各通孔設置於可令其與相對應之焊塾距離皆為等長 之同一基準線上，且依據佈線規則及線路佈設狀況，合理 调整線路及對應通孔之位置，以於滿足佈線規則之最小間 =要求下’盡可能節省佈線”，藉以提供靈活度較佳 的佈線空間並增加可佈線空間；並由於將通孔之合理 ►於與相對應之焊墊距離皆為等長 線，且相應減少通孔之數便於佈 同時，夢由㈣孔之線效率及降低成本； ^猎由μ通孔之权置方式，更可提升該複數通孔之整 背性及美觀度，相對已解決先前技術之缺失。 上述實施例僅為例示性說明本發明之 效，而非用於限制本發明，亦即，本實，乃、力 他改變。因此，任何熟習此項技藝 可：：= 發明之精神及㈣下，對上述實施例 2在不迷月本 明之權利保護範圍，應如後述。因此本發 〜f明專利範園所列。 19318 12 1295910 【圖式簡單說明】 第1圖係顯示本發明之佈線方法之較佳實施例之流 程示意圖； 之佈線糸統之較佳實施例之方 之佈線方法之電子元件結構模 第2圖係顯示本發明 塊示意圖； 弟3圖係顯示本發明 型之示意圖；以及'α, 2 fa) UJ 5-&6<xl<V〇^ 36?6 <x2< Va2 -36 but the minimum distance allowed by the through hole and the trace according to the wiring rule is mil ( The requirement of mU) is that the adjacent vias π and V2 go through the minimum spacing of the line widths r2+wl+w+w2+r2|min=2r2 + 12+w=i2+w (let r2 = 0). Through the position information of the solder pads and through holes of the electronic component, the application analyzes it, and under the condition of satisfying ^, "automatically adjusts the w hole, the v2 hole, and the distance between them is 12+w, so as to reach The optimum size of the line. Please refer to the diagrams of f 4 and 帛 5, which show application examples through the wiring method of the present invention. As shown, the plurality of through holes V, V2 and V3 are provided in corresponding lines. Parallel adjacent pads A1 and B1, A2 and B2, A3 and β3, and A4 and β4 are arranged on the geometry_heart line, and a trace Π 1T2 is disposed between the through holes ” and V2 and V3. It must be noted that at this time, the plurality of through-holes 19318 11 1295910 fully meet the wiring requirements of the vias and the pads and the minimum spacing between the vias and the traces. In order to effectively utilize the wiring space, it is necessary to meet the wiring rules such as Via/Pad, Via/Trace, and Trace/Trace. Between the trace T2 and the trace T3, the distance between the traces Τ2 and Τ3 can be adjusted, and the through holes V2 and V3 move away from the traces Τ2 and Τ3, the same day, the through hole The VI is also adjusted in the same direction as the through hole V2 by the proximity of the through hole V2, so that the pad, the via, and the trace conform to the wiring rule. [The above-mentioned wiring method and system of the present invention are based on the wiring rules, and the through holes are arranged on the same reference line which can be equal to the corresponding soldering distance, and arranged according to the wiring rules and the lines. Condition, reasonably adjust the position of the line and the corresponding through hole, so as to meet the minimum requirements of the wiring rules = 'saving wiring as much as possible', thereby providing more flexible wiring space and increasing the wiring space; and Reasonable ►The distance between the corresponding pads and the corresponding pads is equal to the length of the line, and the number of through holes is reduced to facilitate the cloth at the same time. The dream is based on the efficiency of the line and the cost is reduced. ^ Hunting is the right way of the through hole, The invention can improve the integrity and the aesthetics of the plurality of through holes, and the prior art is relatively eliminated. The above embodiments are merely illustrative of the effects of the present invention, and are not intended to limit the present invention, that is, Therefore, any skill in this skill can be::= the spirit of the invention and (4), the scope of protection of the above-mentioned embodiment 2 in the absence of the moon should be as follows. 19318 12 1295910 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing a preferred embodiment of a wiring method of the present invention; an electronic circuit of a wiring method of a preferred embodiment of the wiring system FIG. 2 is a block diagram showing the present invention; FIG. 3 is a schematic view showing the type of the present invention;
苐4及苐5圖係顯示透過本發明 施例。 之佈線方法之應用實 【主11012 要元件符號說明】 佈線系統 設置模組 調整模組 220 S101〜S109 電路板 佈線區域 步驟 售 A卜 A2 、 A3 、 A4 、 Bl 、 B2 、 B3 、 B4 V1 ^ V2 ^ V3 通孔 X1、X2 通孔至焊墊之間距 T1、T2、T3 走線 rl 焊墊之半徑 r2 通孔之半徑 焊塾 相鄰通孔之間距 相鄰通孔之連線 走線之線寬 19318 13Figures 4 and 5 show the embodiments of the present invention. The application of the wiring method [main 11012 element description] wiring system setting module adjustment module 220 S101 ~ S109 circuit board wiring area step sale A Bu A2, A3, A4, Bl, B2, B3, B4 V1 ^ V2 ^ V3 Through Hole X1, X2 Through Hole to Pad Between T1, T2, T3 Trace rl Pad Radius r2 Through Hole Radius Solder Between Adjacent Through Holes Between Lines of Adjacent Through Holes Width 19318 13