CN105868454B

CN105868454B - A kind of PCB design method of the embedded system based on A20

Info

Publication number: CN105868454B
Application number: CN201610177435.2A
Authority: CN
Inventors: 鄂鸿飞; 吕端秋; 仇骁
Original assignee: Aerospace Hi Tech Holding Group Co Ltd
Current assignee: Aerospace Hi Tech Holding Group Co Ltd
Priority date: 2016-03-24
Filing date: 2016-03-24
Publication date: 2019-04-02
Anticipated expiration: 2036-03-24
Also published as: CN105868454A

Abstract

A kind of PCB design method of the embedded system based on A20, is related to a kind of PCB design method.Existing manufacturing cost is higher when the present invention is to solve the problems, such as that the PCB for being directed to smaller size is manufactured according to existing PCB design method.The embedded system based on A20 is designed, mainly includes core controller A20, DDR3, NAND Flash, clock chip and power module；In veneer integral planar layout, DDR3 and NAND FLASH is separately designed in the two sides up and down of core controller A20 or the left and right sides, it is preferentially routed；Power module and clock chip are laid out at left and right sides of core controller A20 respectively or upper and lower two sides, and clock chip is close to core controller A20 design；The PCB stack-design of embedded system based on A20 is 8 layers, includes 5 routing layers, 2 GND layers and 1 bus plane.The present invention is suitable for the design field of PCB.

Description

A kind of PCB design method of the embedded system based on A20

Technical field

The present invention relates to a kind of PCB design methods.

Background technique

With the continuous development of electronic industry, being that control embedded system is more and more applied in automotive electronics with ARM Field, such as vehicle mounted guidance, the equipment such as audio-visual amusement, in order to reach better user experience, the speed of service of embedded system is got over Carry out more block, performance and stability requirement are also higher and higher, but cause the design and manufacture cost of its PCB also higher and higher therewith, mirror In Automobile Electronic Industry to the rigors of system stability and cost, on the premise of ensuring performance, it is embedded to reduce high speed The demand of the design and manufacture cost of system PCB is increasingly prominent.

The PCB of high speed embedded system is usually multi-layer board, and system performance is higher, and the speed of service is faster, then system is multiple Miscellaneous degree is higher, and corresponding PCB layer number is also more, usually differs for 6-16 layers.It is set generally directed to the PCB of larger size Meter, needs the wiring of the elements such as DDR3, NAND Flash of HW High Way relatively easily to design, but when PCB size is less than When 70mm × 50mm, there are many wires design relative difficulty of HW High Way, and DDR3, NAND in lesser size Flash's etc. interferes with each other also than more serious.So increasingly prominent for the demand of the PCB design of smaller size.

Summary of the invention

The present invention is to solve to be directed to exist when the PCB of smaller size is manufactured according to existing PCB design method The higher problem of manufacturing cost.

A kind of PCB design method of the embedded system based on A20, specific design method are as follows:

Design the embedded system based on A20, mainly include core controller A20, DDR3 (data cache), NAND Flash (mass data storage), clock chip and power module；

As shown in Figure 1, in veneer integral planar layout, since DDR3 and NAND FLASH has more high speed signal Line, therefore DDR3 and NAND FLASH is separately designed in the two sides up and down of core controller A20 or the left and right sides, it is excellent to its First it is routed；Power module and clock chip are laid out at left and right sides of core controller A20 respectively or upper and lower two sides, clock Chip is close to core controller A20 design；

The PCB stack-design of embedded system based on A20 is 8 layers, includes 5 routing layers, 2 GND layers and 1 power supply Layer.

Fig. 3 show 10 layers of conventional PCB stacked graph, and Fig. 2 is 8 layers of PCB stacked graph of the invention, and the two includes 5 Routing layer and 1 bus plane, therefore can achieve unanimously in wiring space.But the manufacturing cost of 8 layers of PCB of the invention is more It is low.

The present invention has the effect that

For the PCB design of smaller size, the present invention is not only able to by reasonable PCB placement-and-routing and stack-design Guarantee the stability of high speed embedded system, and reduce PCB layer number, greatly reduce PCB designs and manufactures cost.Phase Than existing 10 layers of PCB lamination design method, 8 layers of PCB stack-design of the invention can guarantee under performance the same terms, Design and manufacture cost is reduced by 35% or more.

Detailed description of the invention

Fig. 1 is PCB schematic layout pattern of the invention；

Fig. 2 is PCB stacked graph of the invention (including 5 routing layers)；

Fig. 3 is usual pcb board stacked graph (including 5 routing layers).

Specific embodiment

Specific embodiment 1:

1, a kind of PCB design method of the embedded system based on A20, it is characterised in that specific design method is as follows:

Specific embodiment 2:

PCB lamination described in present embodiment is designed by following principle:

It is preferential in terms of PCB lamination to guarantee that high speed signal (100MHz or more) line has complete reference horizontal plane of manufacturing, power supply signal It is handled as far as possible by power plane, guarantees enough through-current capabilities, low speed signal (10MHz or less) or level signal can be adopted It is routed with adjacent layer, to reduce PCB layer number, reduces cost.

Other steps and parameter are same as the specific embodiment one.

Specific embodiment 3:

The specific design method of PCB lamination described in present embodiment is as follows:

PCB stack-design is 8 layers, is followed successively by TOP layers, GND layers, L3 layers, L4 layers, POWER layers, L6 layers, GND from top to bottom Layer, BOTTOM layers；

DDR3 data line and address line rate highest, it is maximum up to 1Gsps, therefore in layout by DDR3 separately as one Block will that is, in plane figure by DDR3 far from NAND Flash, clock chip and power module design in plane figure The distance between DDR3 and NAND Flash, clock chip and power module maximize design, are exactly the case where space allows Under it is remote as far as possible, the signal wire spacing that both final purpose is ensuring that is greater than 5 times of PCB trace width；

Decision design is in L3, L6 layers, TOP layers and BOTTOM layers progress DDR3 wiring, and routing of layout length is short as far as possible, between line Away from big as far as possible；All data lines, address wire, clock line do equal length treatment respectively, and error is less than ± 100mil, between differential pair Isometric error is less than 5mil；

NAND Flash data line is another group of HW High Way on plate, and maximum rate is up to 200Msps, in order to avoid it Interference is generated with DDR3, design NAND Flash is as far as possible far from DDR3 in layout；By NAND FLASH and DDR3 cloth in the present invention Office had both avoided interfering with each other between them, while can be realized NAND FLASH in the two sides of A20 core controller in this way With DDR3 in identical layer wires design, routing layer is saved；All data lines and address wire do equal length treatment respectively, and error ± 200mil, isometric error is less than 5mil between differential pair；

For clock chip close to core controller A20 chip clock pin design, cabling is short as far as possible, and not pass through perception member Part bottom, as far as possible far from DDR3, NAND Flash；

Power module mainly spreads the form design of power plane at POWER layers, has not only guaranteed through-flow, but also can be used as signal The reference planes of line.

Other steps and parameter are the same as one or two specific embodiments.

Specific embodiment 4:

Line spacing when present embodiment carries out DDR3 wiring is greater than 3-5 times of PCB trace width.

Other steps and parameter are identical as one of specific embodiment one to three.

Specific embodiment 5:

Line spacing when present embodiment carries out NAND FLASH wiring is greater than 3-5 times of PCB trace width.

Other steps and parameter are identical as one of specific embodiment one to four.

Claims

1. a kind of PCB design method of the embedded system based on A20, it is characterised in that specific design method is as follows:

Design the embedded system based on A20 comprising core controller A20, DDR3, NAND Flash, clock chip and electricity Source module；

In veneer integral planar layout, DDR3 and NAND FLASH is separately designed in the two sides up and down of core controller A20 Or the left and right sides, it is preferentially routed；Power module and clock chip are laid out respectively in core controller A20 or so two Side or upper and lower two sides, clock chip are close to core controller A20 design；

The PCB stack-design of embedded system based on A20 is 8 layers, includes 5 routing layers, 2 GND layers and 1 bus plane；

PCB stacked arrangement is followed successively by TOP layers, GND layers, L3 layers, L4 layers, POWER layers, L6 layers, GND layers, BOTTOM from top to bottom Layer；

It, i.e., will in plane figure by DDR3 far from NAND Flash, clock chip and power module design in plane figure The distance between DDR3 and NAND Flash, clock chip and power module maximize design；

Decision design is in L3, L6 layers, TOP layers and BOTTOM layers progress DDR3 wiring；All data lines, address wire, clock line point Equal length treatment is not done, and error is less than ± 100mil, and isometric error is less than 5mil between differential pair；

NAND FLASH and DDR3 are laid out in the two sides of A20 core controller, can be realized NAND FLASH and DDR3 in phase Same layer wires design；All data lines and address wire do equal length treatment respectively, error ± 200mil, isometric mistake between differential pair Difference is less than 5mil；

Clock chip not pass through inductive element bottom close to core controller A20 chip clock pin design, cabling；

Power module spreads the form design of power plane at POWER layers.

2. a kind of PCB design method of embedded system based on A20 according to claim 1, it is characterised in that carry out Line spacing when DDR3 is routed is greater than 3-5 times of PCB trace width.

3. a kind of PCB design method of embedded system based on A20 according to claim 2, it is characterised in that carry out Line spacing when NAND FLASH is routed is greater than 3-5 times of PCB trace width.