1293775 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體晶片封裝結構及其製造方法， 詳言之，係關於一種將晶片置入矽基材上之容置洞内之封 裝結構及其製造方法。 【先前技術】 參考圖la至lc，顯示習用覆晶接合方法之步驟示意圖。 首先，參考圖la，提供一晶片1〇,該晶片1〇具有一線路面 11及一非線路面12，其中該線路面U具有複數個晶片銲墊 13，每一晶片銲墊13上具有一凸塊14。 接者’提供一基板20，該基板20具有一上表面21及一下 表面22。該上表面21具有複數個基板銲墊23及一導電線路 層（圖中未示）’该荨基板鲜塾23之位置係相對於該等凸塊 14 〇 接著’參考圖lb，對準該晶片1 〇及該基板2〇，即以該晶 片10之線路面11面對該基板20上表面21，且將該等凸塊14 對準該等基板銲墊23。之後，壓合該晶片1〇及該基板2〇， 使得該等凸塊14接觸該等基板銲墊23。接著，再加熱該晶 片10及該基板20，使得該等凸塊14電氣連接至該等基板銲 墊23，此即迴銲製程。 接著，參考圖lc，由於迴銲製程後，該晶片1〇之線路面 11與該基板20上表面21間會有一間隙之產生，在高溫時晶 片10及基板20不同之熱膨脹係數會導致破壞，因此必須再 填充一底膠（underfill)30於該晶片10之線路面11與該基板 99050.doc 1293775 '20上表面21間之間隙。如此，完成習用之覆晶接合結構1。 上述之覆晶接合方式之缺點如下，第一，其必須填充該 底^30,此-填充底膠之步驟，在實際操作上十分困難且 f時°第二，該晶片1G與該基板2G接合後之總高度不易縮 ' + ’因為其中間具有該等凸塊Η。第三，此種接合方式後 之接合強度不大’該晶片10與該基板20間容易產生橫向之 相對位移。 • 因此’有必要提供一種創新且具進步性的半導體晶片封 裝結構及其製造方法，以解決上述問題。 【發明内容】 本發明之目的在於提供—種半導體晶片封裝結構及其製 造方法，其係直接將晶片i入石夕基材上之容置、洞，因此不 需使用底膠，可省卻習用填充底膠之步驟，使製程更為簡 單。此外，可減小封裝結構之總高度。 本發明之目的在於提供一種半導體晶片封裝結構及其製 • 丨π》，其係將晶片#同材質之矽基材封裝成一封裝結 構，因此可避免因材質不同及熱膨脹係數不同所產生之熱 - 應力而導致該晶片之破裂。 ， 為達上述目的，本發明提供一種半導體晶片封裝結構之 製造方法，包括： (a)提供一矽基材，該矽基材具有一上表面、一下表面及 w 複數個容置洞； . 提供複數個晶片，每一晶片具有一主動面及一背面， 其中5亥主動面具有複數個晶片輝墊，該等晶片係與該石夕基 99050.doc * 6 - 1293775 材同材質； (C)將該等晶片以主動面朝上之方式置入該矽基材之容置 洞内； (d) 形成一介電層於該晶片主動面及該石夕基材上表面； (e) 形成複數個第一開口於該介電層上，該等第一開口之 位置係對應該等晶片銲墊； (f) 形成一導電層於該介電層上，該導電層係透過該等第 一開口連接至該等晶片銲墊，且該導電層上具有複數個球 銲墊； (g) 形成一保護層於該介電層及該導電層上； (h) 形成複數個第二開口於該保護層上，該等第二開口之 位置係對應該等球銲墊； (i) 形成複數個導電元件於該等球銲墊上；及 ⑴切割該矽基材以形成複數個個別封裝結構。 【實施方式】 參考圖2至圖13，顯示本發明半導體封裝結構之製造流程 示意圖。首先，參考圖2及圖3，提供一矽基材30，該矽基 材30具有一上表面301、一下表面302、複數個容置洞32、 複數條切割線34及複數個凹槽36。該矽基材30係與所欲封 裝之晶片同材質，且其無訊號功能，以避免因材質不同及 熱膨脹係數不同所產生之熱應力而導致該晶片之破裂。較 佳地，該石夕基材30係為一虛晶圓（dummy wafer)。 在本實施例中，該矽基材30上之容置洞32係不貫穿該矽 基材30。然而在其他應用中，如圖4及圖5所示，該石夕基材 99050.doc 1293775 30上之容置洞32係貫穿該矽基材30，因此需要貼合一保護 膜33於該矽基材30下表面302之步驟。 接著，參考圖6，提供複數個晶片38及複數個被動元件 40，每一晶片38具有一主動面381及一背面382，其中該主BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor chip package structure and a method of fabricating the same, and more particularly to a package structure for placing a wafer in a receiving hole on a substrate. And its manufacturing method. [Prior Art] Referring to Figures la to lc, a schematic diagram of the steps of a conventional flip chip bonding method is shown. First, referring to FIG. 1a, a wafer 1 is provided, the wafer 1 has a line surface 11 and a non-line surface 12, wherein the line surface U has a plurality of wafer pads 13 each having a protrusion on the pad 13 Block 14. The connector 'provides a substrate 20 having an upper surface 21 and a lower surface 22. The upper surface 21 has a plurality of substrate pads 23 and a conductive circuit layer (not shown). The position of the substrate slabs 23 is relative to the bumps 14 and then referenced to FIG. 1 and the substrate 2, that is, the circuit surface 11 of the wafer 10 faces the upper surface 21 of the substrate 20, and the bumps 14 are aligned with the substrate pads 23. Thereafter, the wafer 1 and the substrate 2 are pressed together such that the bumps 14 contact the substrate pads 23. Then, the wafer 10 and the substrate 20 are heated to electrically connect the bumps 14 to the substrate pads 23, which is a reflow process. Next, referring to FIG. 1c, after the reflow process, there is a gap between the line surface 11 of the wafer 1 and the upper surface 21 of the substrate 20. At different temperatures, the thermal expansion coefficients of the wafer 10 and the substrate 20 may cause damage. Therefore, an underfill 30 must be refilled between the line surface 11 of the wafer 10 and the upper surface 21 of the substrate 99050.doc 1293775 '20. Thus, the conventional flip chip bonding structure 1 is completed. The disadvantages of the above-described flip chip bonding method are as follows. First, it is necessary to fill the substrate 30. This step of filling the primer is very difficult in practical operation and f is second. The wafer 1G is bonded to the substrate 2G. The total height afterwards is not easy to shrink '+' because there are such bumps in between. Third, the bonding strength after such bonding is not large. The lateral displacement of the wafer 10 and the substrate 20 is likely to occur. • Therefore, it is necessary to provide an innovative and progressive semiconductor wafer package structure and its manufacturing method to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor chip package structure and a method for fabricating the same, which directly enclose a wafer i into a substrate and a hole on a substrate, thereby eliminating the need for a primer and eliminating the need for conventional filling. The primer step makes the process simpler. In addition, the overall height of the package structure can be reduced. The object of the present invention is to provide a semiconductor chip package structure and a system thereof, which are used to package a wafer of the same material as a package structure, thereby avoiding heat generated by different materials and different coefficients of thermal expansion - Stress causes cracking of the wafer. In order to achieve the above object, the present invention provides a method for fabricating a semiconductor chip package structure, comprising: (a) providing a substrate having an upper surface, a lower surface, and a plurality of receiving holes; a plurality of wafers each having an active surface and a back surface, wherein the 5 Hz active surface has a plurality of wafer embossing pads, and the wafers are of the same material as the Shi Xiji 99050.doc * 6 - 1293775; (C) And placing the wafers into the receiving holes of the germanium substrate in an active face-up manner; (d) forming a dielectric layer on the active surface of the wafer and the upper surface of the substrate; (e) forming a plurality a first opening is formed on the dielectric layer, and the first openings are aligned with the wafer pads; (f) forming a conductive layer on the dielectric layer, the conductive layer passing through the first openings Connecting to the wafer pads, and having a plurality of ball pads on the conductive layer; (g) forming a protective layer on the dielectric layer and the conductive layer; (h) forming a plurality of second openings for the protection On the layer, the positions of the second openings are corresponding to the ball pads; (i) forming a complex Conductive elements to such a ball bonding pad; ⑴ and cutting the silicon substrate to form a plurality of individual package. [Embodiment] Referring to Figures 2 to 13, there is shown a schematic diagram of a manufacturing process of a semiconductor package structure of the present invention. First, referring to Figures 2 and 3, a crucible substrate 30 is provided having an upper surface 301, a lower surface 302, a plurality of receiving cavities 32, a plurality of cutting lines 34, and a plurality of grooves 36. The base material 30 is made of the same material as the wafer to be packaged, and has no signal function to avoid cracking of the wafer due to thermal stress caused by different materials and different thermal expansion coefficients. Preferably, the stone substrate 30 is a dummy wafer. In the present embodiment, the receiving hole 32 on the crucible base material 30 does not penetrate the crucible base material 30. However, in other applications, as shown in FIG. 4 and FIG. 5, the receiving hole 32 of the stone substrate 99050.doc 1293775 30 penetrates the base material 30, so that a protective film 33 needs to be attached thereto. The step of the lower surface 302 of the substrate 30. Next, referring to FIG. 6, a plurality of wafers 38 and a plurality of passive components 40 are provided. Each wafer 38 has an active surface 381 and a back surface 382, wherein the main
動面381具有複數個晶片銲墊383。之後，將該等晶片38以 主動面381朝上之方式置入該矽基材30之容置洞32内，且利 用一膠層將該等晶片38之背面382黏附於該容置洞32之底 部。之後’將該等被動元件40置入該石夕基材30之凹槽36内。 接著’參考圖7，形成一介電層42於該晶片38主動面381 及該矽基材30上表面301上。 接著，參考圖8,形成複數個第一開口 421及第三開口 422 於該介電層42上，該等第一開口421之位置係對應該等晶片 銲墊383，該等第三開口 422之位置係對應該等被動元件4〇。 接著，參考圖9，形成一導電層44於該介電層42上，該導 電層44係透過該等第一開口421連接至該等晶片銲墊， 且透過該等第三開口 422連接至該等被動元件4〇。該導電層 44上具有複數個球銲墊44ι。 接著多考圖，形成一保護層46(例如一防銲層）於該 介電層42及該導電層44上。 、 接著：參考圖u，形成複數個第二開口461於該保護層46 上’該等第二開0461之位置係對應該等球鋒墊441。 接著’參考圖12,形錢數料電元件48，例如錫球 H1)，該f球銲墊441上。此外，如果為了減小該 石土 U度，可以利用研磨或是蚀刻等方式移除一預 99050.doc 1293775 疋厚度之碎基材30下表面302。此外，如果為了增加散熱效 果，可以形成一金屬層於該矽基材30下表面3〇2。或是為了 列印圖案，可以形成一高分子材料層於該矽基材3〇下表面 302。 最後’沿著該等切割線34切割該矽基材30以形成複數個 個別封裝結構50，如圖13所示。 參考圖13，顯示本發明之半導體晶片封裝結構之示意 圖。該半導體晶片封裝結構5〇包括··一晶片38、一矽基材 3〇、一介電層42、一導電層44、一保護層46及複數個導電 元件48。該晶片38具有一主動面381及一背面3 82，其中該 主動面381具有複數個晶片銲墊383。該矽基材3〇係與該晶 片38同材質，該矽基材3〇具有一上表面3〇1、一下表面3〇2、 一容置洞32及複數個凹槽36，該容置洞32係用以容置該晶 片38，該等凹槽36係用以容置被動元件4〇。 該介電層42位於該晶片38主動面381及該矽基材30上表 面301上，該介電層42具有複數個第一開口 421及第三開口 422,該等第一開口421之位置係對應該等晶片銲墊383，該 4第三開口 422之位置係對應該等被動元件4〇。 該導電層44係位於該介電層42上，該導電層44係透過該 專第一開口 421連接至該等晶片銲墊3 83，且透過該等第三 開口 422連接至該等被動元件4〇。該導電層44上具有複數個 球銲墊441。 該保護層46(例如一防銲層）係位於該介電層42及該導電 層44上，該保護層46具有複數個第二開口 461，該等第二開 99050.doc 1293775 口 461之位置係對應該等球銲墊441。 該等導電元件48(例如錫球）係位於該等球銲墊441上。 在本實施例中，該矽基材30上之容置洞32係不貫穿該石夕 基材30。然而在其他應用中’該梦基材30上之容置洞32係 貫穿該矽基材30。此外，如果為了增加散熱效果，該矽基 材30下表面302更包括一金屬層。或是為了列印圖案，該石夕 基材30下表面302更包括一高分子材料層。 惟上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士可在不違背本發 明之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖la至lc顯示習用覆晶接合方法之步驟示意圖及 圖2至圖13顯示本發明半導體封裝結構之製造流程示意 圖。 【主要元件符號說明】 1 習用之覆晶接合結構 10 晶片 11 線路面 12 非線路面 13 晶片鲜塾 14 凸塊 20 基板 21 上表面 99050.doc 1293775 22 • 23 30 32 *. 33 34 36 Φ 38 40 42 44 46 48 50 301 •302 381 ' 382 ’ 383 421 422 441 461 下表面 基板銲墊 矽基材 容置洞 保護膜 切割線 凹槽 晶片 被動元件 介電層 導電層 保護層 導電元件 個別封裝結構 上表面 下表面 主動面 背面 晶片銲墊 第一開口 第三開口 球銲墊 第二開口 99050.docThe moving surface 381 has a plurality of wafer pads 383. Then, the wafers 38 are placed in the receiving holes 32 of the base material 30 with the active surface 381 facing upward, and the back surface 382 of the wafers 38 is adhered to the receiving holes 32 by a glue layer. bottom. The passive elements 40 are then placed into the recesses 36 of the stone substrate 30. Next, referring to FIG. 7, a dielectric layer 42 is formed on the active surface 381 of the wafer 38 and the upper surface 301 of the substrate 30. Next, referring to FIG. 8 , a plurality of first openings 421 and third openings 422 are formed on the dielectric layer 42 . The positions of the first openings 421 are corresponding to the wafer pads 383 , and the third openings 422 are The position is the same as the passive component. Next, referring to FIG. 9, a conductive layer 44 is formed on the dielectric layer 42. The conductive layer 44 is connected to the die pads through the first openings 421, and is connected to the die through the third openings 422. Wait for the passive component 4〇. The conductive layer 44 has a plurality of ball pads 44ι thereon. Next, a protective layer 46 (e.g., a solder resist layer) is formed on the dielectric layer 42 and the conductive layer 44. Next, referring to FIG. u, a plurality of second openings 461 are formed on the protective layer 46. The positions of the second openings 0461 correspond to the ball edge pads 441. Next, referring to Fig. 12, a charge element 48, such as solder ball H1, is formed on the f ball pad 441. In addition, if the U-degree of the grit is reduced, a lower surface 302 of the crushed substrate 30 of a pre-99050.doc 1293775 疋 thickness may be removed by grinding or etching. Further, if a heat dissipation effect is increased, a metal layer may be formed on the lower surface 3〇2 of the tantalum substrate 30. Alternatively, in order to print a pattern, a polymer material layer may be formed on the lower surface 302 of the crucible substrate 3. Finally, the tantalum substrate 30 is cut along the cut lines 34 to form a plurality of individual package structures 50, as shown in FIG. Referring to Figure 13, there is shown a schematic view of a semiconductor wafer package structure of the present invention. The semiconductor chip package structure 5 includes a wafer 38, a germanium substrate 3A, a dielectric layer 42, a conductive layer 44, a protective layer 46, and a plurality of conductive elements 48. The wafer 38 has an active surface 381 and a back surface 382, wherein the active surface 381 has a plurality of wafer pads 383. The crucible substrate 3 is made of the same material as the wafer 38. The crucible substrate 3 has an upper surface 3〇1, a lower surface 3〇2, a receiving hole 32, and a plurality of grooves 36. The 32 series is for accommodating the wafers 38, and the grooves 36 are for accommodating the passive components. The dielectric layer 42 is located on the active surface 381 of the wafer 38 and the upper surface 301 of the substrate 30. The dielectric layer 42 has a plurality of first openings 421 and third openings 422. The positions of the first openings 421 are Corresponding to the wafer pad 383, the position of the fourth opening 422 is corresponding to the passive component 4〇. The conductive layer 44 is disposed on the dielectric layer 42. The conductive layer 44 is connected to the die pads 3 83 through the first opening 421, and is connected to the passive components 4 through the third openings 422. Hey. The conductive layer 44 has a plurality of ball pads 441 thereon. The protective layer 46 (eg, a solder resist layer) is disposed on the dielectric layer 42 and the conductive layer 44. The protective layer 46 has a plurality of second openings 461, and the positions of the second openings 99050.doc 1293775 461 The pair should be equal to the ball pad 441. The conductive elements 48 (e.g., solder balls) are located on the ball pads 441. In the present embodiment, the receiving hole 32 on the base material 30 does not penetrate the stone substrate 30. However, in other applications, the receiving hole 32 on the dream substrate 30 extends through the crucible substrate 30. In addition, if the heat dissipation effect is increased, the lower surface 302 of the base material 30 further includes a metal layer. Or in order to print the pattern, the lower surface 302 of the stone substrate 30 further comprises a layer of polymer material. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1a to 1c are schematic diagrams showing steps of a conventional flip chip bonding method and FIGS. 2 to 13 are views showing a manufacturing process of a semiconductor package structure of the present invention. [Main component symbol description] 1 Conventional flip chip bonding structure 10 Wafer 11 Line surface 12 Non-line surface 13 Chip fresh 塾 14 Bump 20 Substrate 21 Upper surface 99050.doc 1293775 22 • 23 30 32 *. 33 34 36 Φ 38 40 42 44 46 48 50 301 •302 381 ' 382 ' 383 421 422 441 461 Lower surface substrate pad 矽 Substrate receiving hole protective film Cutting line Groove chip Passive component Dielectric layer Conductive layer Protective layer Conductive component Individual package structure Upper surface lower surface active surface back wafer pad first opening third opening ball pad second opening 99050.doc