129260.1 ^VQTtwf.doc/g 玖、發明說明： 【發明所屬之技術領域】 本發明是有關於-種缺陷檢測元件及其檢測方 元件且及=1 於一麵電子束檢測之缺崎測 【先前技術】129260.1 ^VQTtwf.doc/g 发明, invention description: [Technical field of the invention] The present invention relates to a defect detecting component and its detecting component and 1 = one side of the electron beam detecting technology】
大型積體電路技術的持續發展，積體電路 的積集度也日漸提昇，而於製程中所產生之極微小的 缺陷現在就成為影響積體電路品質之關鍵缺陷。在過 去十年間，用來檢測製程中所產生之缺陷的缺陷檢 已成為製程中的一標準步驟，而缺陷檢測是以晶圓在 製程中易於形成缺陷處或對缺陷特別敏感的步 用一統計取樣基礎來實施的。 習知一種缺陷檢測方法為嘗試錯誤法 error)，其先設定一缺陷檢測參數，並進行一掃瞄 晶圓的動作，再由操作人員將偵測出有缺陷訊號^ ，件剖開，進行檢測，確認此元件是否為缺陷元;。 若確認為缺陷元件，則此缺陷檢測參數可適用於檢 測同一批次的晶圓，若確認不是缺陷元件，則需再 设定另一缺陷檢測參數來檢測，直到偵測出有缺陷 訊號之元件確實為缺陷元件為止。然而，上述之嘗 試錯誤法在找尋檢測參數的過程中可說是相當地^ 瑣且費時。 $ 習知另一種檢測方法如美國專利第6,451，185 B1號所揭露，其係利用光學檢測裝置來檢測刻意形 1292601 1 3 797twf. doc/g 成於晶圓上的缺p自構件’從而得到合適的缺陷檢測 參數，並將此參數應用於後續之檢測中。狹而，在 此檢測方法中，這些刻意形成於晶圓上的缺陷構件 由於受限於光學檢測裝置的限制，因此其必須具有 可反射的上表面，從而這些缺陷構件在材質的選擇 上會受到諸多的限制。而且，為了製作這些缺陷構 件也會使得原本的製程變得更為複雜。 【發明内容】 有鑑於此，本發明的目的就是提供一種缺陷檢測 7L件的檢測方法，以解決f知缺陷檢測流程費時的問 題0 制、本發明，另一目的是提供一種缺陷檢測元件的 =造方法，藉由於—般製程中同時形成缺陷檢測元 件，來簡化缺陷檢測元件的製程。 ^制本毛明的再一目的是提供另一種缺陷檢測元件 丛衣造^法，藉由於一般製程中同時形成缺陷檢測元 件，來簡化缺陷檢測元件的製程。 #本，月的又目的是提供一種缺陷檢測元件之 :冓’藉由此缺陷檢測元件之結構，可以使得檢測缺 k件的流程更為迅速，且結果更為精確。 本發明的目的是提供另一種缺陷檢測元件之結 一丛猎由此缺陷檢測元件之結構，可以使得檢測缺陷 ^的流程更為迅速，且結果更為精確。 本毛明提出一種缺陷檢測元件的檢測方法，包 於曰曰圓上形成多數個缺陷檢測元件，且各缺 1292601 13797twf.doc/g 陷檢測兀件係由下層之絕緣層與上層之導電層堆漫 而成。（b)設定一缺陷檢測參數，並且利用電子^ (e-beam)掃瞄晶圓，以得到多數個缺陷訊號。（幻確認 缺陷訊號的數目是否至少等於缺陷檢測元件的數 目。若缺陷訊號的數目小於缺陷檢測元件的數目，貝q 重新调整缺陷檢測參數，並重複步驟（b)〜(c”直到缺 陷訊號的數目至少等於缺陷檢測元件的數目為止。 、本發明又提出一種缺陷檢測元件的製造方法，此 方法係先於晶圓上形成多數個導電結構。然後，在晶 圓上形成間隙壁材料層，以覆蓋導電結構。接著，= 除部分間隙壁材料層，以於導電結構的側 ==壁，並且保留下相鄰二導電結構其上 相對的間隙壁之間的間隙壁材料層。之後，再於 t形成絕緣層’覆蓋導電結構，且絕緣層具有多數個 f陷接觸窗開口，以暴露出間隙壁材料層。繼之，於 各缺陷接觸窗開口中填入導電材料。 方丰^再提出一種缺陷檢測元件的製造方法，此 以供一晶圓，且此晶圓具有多數條切割道， 層：ί:;二Γ二接著’於晶圓上依序形成絕緣 曰厂層。然後，定義絕緣層與導電層，以於 上形成多數料電堆4結構，並且於切㈤道上妒 缺陷檢測之多數個缺陷堆疊結構。之後，再‘ 7且層’ ί蓋導電堆#結構與缺陷堆疊結 H層至少具有多數個缺陷接觸窗開口，以a “缺陷堆4結構。繼之，於各缺陷接觸& 1292601 1 3 797twf.doc/g 入一導電材料。 ^發明另提出—種缺陷檢測元件之結構，此 已括基底、缺陷接觸窗、間隙壁與絕緣層。 f：f包括有多數個導電結構，且缺陷接觸窗“ 窗此外’間隙壁配置於缺陷接觸 i底ΐί 而絕緣層配置於缺陷接觸窗與 本發明又提出另一種缺陷檢測元件之、纟士 構包括第一絕緣層、導電 >、第一 … 兹甘士斤 净电層弟一絕緣層與缺陷接觸 声配；：弟，絕緣層配置於晶圓之切割道上，而導電 f配置於弟—絕緣層上。此外，第二絕緣層覆蓋導電 上而缺陷接觸窗配置於第二絕緣層中，且位 卜夕本發明之檢測方法係利用刻意形成於晶圓 制„測兀件，並搭配電子束來掃描這些缺陷檢 二、目丨2而决定出適用於之後的晶圓缺陷檢測的缺 參數。因此，本發明之檢測方法較習知之方法 ，為間便快速，從而可以節省檢測缺陷的時間與成 此外本舍明之缺陷檢測元件的製作可與一般元 件製作同時進行，因此可以簡化缺陷檢測元件的製 程。 為讓本發明之上述和其他目的、特徵、和優點能 更明顯易懂，下文特舉較佳實施例，並配合所附圖 式，作詳細說明如下。 【實施方式】 1292601 1 3 797twf. doc/g 圖1所繪示為本發明一較佳實施例之缺陷檢測 元件的檢測流程圖。 本發明之缺陷檢測元件的檢測方法係先於一晶 圓上形成多數個缺陷檢測元件（步驟100)，且各缺 陷檢測元件係由下層之一絕緣層與上層之一導電層 堆疊而成。 在一較佳實施例中，缺陷檢測元件之結構，如圖 2所示，且其位於晶圓之晶粒（如圖5所示，520) 上。此結構是由基底200、缺陷接觸窗206、間隙壁 204與絕緣層204a所構成。而且，於此所提及之基 底200即為上述之晶圓，且在其上具有多數個導電結 構202。此外，缺陷接觸窗206配置於相鄰二個導電 結構202之間，且缺陷接觸窗206的材質例如是導電 材料。另外，間隙壁204配置在此缺陷接觸窗206 與各導電結構202之間。此外，絕緣層204a配置於 缺陷接觸窗206與基底200之間。在一較佳實施例 中，間隙壁204與絕緣層204a的材質例如是相同。 在另一較佳實施例中，缺陷檢測元件之結構更包括有 絕緣層208，其係覆蓋基底200與導電結構202，且 有缺陷接觸窗206位於絕緣層208中。 而形成上述如圖2所示之缺陷檢測元件的製造 方法，例如是與一般元件之接觸窗製程同時進行，如 圖3 A至圖3D所示。首先，請參照圖3A，在一晶圓 300上形成多數個導電結構302，其中導電結構302 可 例如是 一金氧 半導體 1292601 1 3 797twf.doc/g (Metal-Oxide-Semiconductor，MOS)元件。接著， 在晶圓300上形成一間隙壁材料層304，以覆蓋於導 電結構302表面上，其中間隙壁材料層304的材質例 如是氮化石夕，而形成間隙壁材料層3 04的方法例如是 化學氣相沈積法（CVD)。 之後，請參照圖3B，移除部分的間隙壁材料層 304，以於導電結構302的侧壁形成間隙壁306，並 且保留間隙壁材料層304a。其中，所保留之間隙壁 材料層304a為後續預定形成缺陷接觸窗的位置，而 二導電結構302之間後續預定形成接觸窗的間隙壁 材料層304則會被移除。 上述的形成方法，例如是在間隙壁材料層304 上利用旋轉塗佈法形成光阻層（未繪示）。之後，進 行一微影製程，以於相鄰二導電結構302之間其預定 形成缺陷接觸窗的位置形成圖案化光阻層。接著，進 行一蝕刻製程，移除部分的間隙壁材料層304，以於 導電結構302的側壁形成間隙壁306，並且形成間隙 壁材料層304a。然後，去除光阻層。 接著，請參照圖3C，在晶圓300上形成絕緣層 308，其中絕緣層308例如是介電層，介電層的材質 例如是氧化矽、氮化矽及氮氧化矽，形成方法例如是 化學氣相沈積法（CVD)。 然後，請參照圖3D，在絕緣層308中形成缺陷 接觸窗開口 310與接觸窗開口 312，且缺陷接觸窗開 口 310暴露出間隙壁材料層304a。其中缺陷接觸窗 1292601 13 79 7 twf. d 〇 c/g 開口 310與接觸窗開口 312的形成方法例如是對絕緣 層308進行微影以及银刻製程，以於導電結構3〇2 之間形成開口。 接著’在晶圓300上的缺陷接觸窗開口 31〇與接 ，窗開口 312中填入一導電材料，以形成一缺陷接觸 自310a與接觸窗312a。其中導電材料例如是金屬或 金屬合金，金屬例如是鎢、鋁及銅，金屬合金例如是 矽化鎢。而形成缺陷接觸窗31〇a與接觸窗312a的方 法例如是在絕緣層308上沈積一導電材料層，以填滿 缺陷接觸窗開口 310與接觸窗開口 312，之後並移除 缺陷接觸窗開口 310與接觸窗開口 312以外的導電材 料層。 由於本發明之缺陷檢測元件的製造可在製造元 件的過程中同時形成，因此有利於節省製程的成本。 此外，在另一較佳實施例中，缺陷檢測元件之結 構二如圖4所示，其係位於晶圓之切割道（如圖5 所示，510)上。此結構包括一絕緣層、導電層 404、另一絕緣層406與缺陷接觸窗4〇8。其中絕緣 層402係配置於基底4〇〇上（即晶圓之切割道），而導 電層4?么係配置在此絕緣層4〇2上。此外，絕緣層 406復盍‘電層404與基底4〇〇，而缺陷接觸窗4〇8 配置於此絕緣層406中，且位於導電層4〇4上，其中 缺陷接觸窗408的材質係為導電材料。 形成上述如目4所示之缺陷檢測元件的製造方 /列如是與一般元件之接冑窗及切割道上的測試 1292601 1 3797twf.doc/g 鍵製程同時進行，如圖6A至圖6C所示。請同時參 一 照圖5與圖6A，首先提供一晶圓500，於晶圓500 上形成多數個切割道510,以定義出多數個晶粒520。 然後，於晶圓500的切割道區510a、510b與晶 粒區520a上形成一絕緣層602與一導電層604。其 中絕緣層602的材質例如是氧化矽，形成方法例如是 熱氧化法。而導電層604的材質例如是多晶矽，形成 方法例如是化學氣相沈積法。 • 接著，請參照圖6B，定義絕緣層602與導電層 604以於晶粒區520a上形成多數個導電堆疊結構 606,及於切割道區510a其預定形成測試鍵（test key) 之部分位置512上形成多數個缺陷堆疊結構608。而 、 切割道區510a、510b之其他測試鍵位置514上則未 形成缺陷堆疊結構。其中形成導電堆疊結構606與缺 ' 陷堆疊結構608的方法例如是對絕緣層602與導電層 604進行一微影製程與蝕刻製程。接著，以導電堆疊 結構606與缺陷堆疊結構608為罩幕，進行離子植入 • 步驟，以於晶圓500内形成摻雜區516。 然後，請參照圖6C，於晶圓500上形成一絕緣 層610，覆蓋導電堆疊結構606、缺陷堆疊結構608 與晶圓500表面。其中絕緣層610的材質例如是氧化 石夕，而形成方法例如是化學氣相沈積法。 接著，在絕緣層610上形成多數個接觸窗開口 612與缺陷接觸窗開口 614。其中接觸窗開口 612係 位於晶粒區的晶圓500上與其他預定形成測試鍵的 1292601 1 3 797twf.doc/g 位置514上，而缺陷接觸窗開口 614係位於預定形成 缺陷接觸窗的位置512上，即為位於缺陷堆疊結構 608 上。 然後’於開口中填入導電材料’以於晶粒區5 2 0 a 中形成接觸窗612a，於切割道區510a、510b中形成 測試鍵613缺陷接觸窗614a。其中導電材料的材質 例如是銅、鋁或鎢，而形成接觸窗612a、測試鍵613 與缺陷接觸窗614a的方式例如是在絕緣層上沈積導 電材料層，以填滿接觸窗開口 612與缺陷接觸窗開口 614,接著移除接觸窗開口 612與缺陷接觸窗開口 614 以外的導電材料層，並暴露出絕緣層610。 接著，繼續進行缺陷檢測元件的檢測。請再次參 照圖1，設定一缺陷檢測參數，並且利用一電子束 (e-beam)以掃瞄晶圓（步驟110)，以得到多數個掃 描訊號。並經由缺陷檢測裝置分析比較晶圓上導電元 件與缺陷檢測元件所得之掃描訊號的不同，藉以檢測 出缺陷訊號。檢測方法中使用電子束作為檢測的入射 源，當電子束撞擊欲測物時，會激發出欲測物的二次 電子（Secondary Electron，SE )，其方法包括以電子 束撞擊一導電結構，會激發出呈通路（close)狀態的導 電結構的二次電子，以電子束撞擊一缺陷檢測元件， 會激發出呈斷路（open)狀態的缺陷檢測元件的二次 電子。接著，經由影像處理系統觀察，激發出的二次 電子量較多的位置為亮點（Bright )，而激發出的二 次電子量較少的位置為陰暗的（Dark )不明顯影像。 13 1292601 13797twf.doc/g 此亮暗不同的對比影像以作為判斷檢測缺 夫-=以同圖3〇所得之缺陷為例做說明，請同時 且2與圖7。*晶圓5〇〇上具有多數個 二粒 且其中之一晶粒區522上係形成有至少一 = =7Γ此缺陷檢測元件7〇2例如是缺陷 接觸囪310a(如圖3D所示），且圖7所繪示為豆 盤座办要u日广拉 6等等之相同 對應位置上則形成有導電元件7〇4，此導電元件7料 例如是接觸窗312a(如圖3D所示），且圖7所繪示亦 ，其上視示意圖。當利用一電子束進行缺陷檢測掃瞄 ，’電子曰束打到導電元件7〇4會激發呈通路狀態的二 次電子量，而電子束打到缺陷檢測元件7〇2時，因元 件，部為一不導通的狀態，則會激發出呈斷路狀態的 二次電子量，比較相同對應位置上之導電元件7〇4 與缺陷檢測元件7 〇 2所得之掃瞄訊號，則可以有一明 暗影像的不同以檢測出缺陷訊號。 另外，以圖6C所得之缺陷檢測元件作另一種檢 測的說明，請同時參照圖5、圖6C與圖8。在晶圓 500上具有多數條切割道51〇，且在其中之一切割道 區510a上係形成有至少一缺陷檢測元件8〇2，此缺 陷檢測元件802例如是缺陷接觸窗614a(如圖6C所 示）’且圖8所緣示為其上視示意圖。此外，在其他 切割道區510b、51〇c等等之相同對應位置上則形成 有導電元件804,導電元件804例如是測試鍵613(如 14 1292601 13797twf.d〇c/g /圖6C所示），而圖8所繪示為其上視示意圖。當在進 行電子束掃瞄時，電子束打到導電元件8〇4會激發呈 通路狀態的二次電子量，而電子束打到缺陷檢測元件 80^時，因元件底部為一不導通的狀態，則會激發出 呈斷路狀恶的二次電子量，同樣地比較相同對應位置 ^之導電元件804與缺陷檢測元件8〇2所得之掃瞄訊 唬，則可以有一明暗影像的不同以檢測出缺陷訊號。 然後，繼續進行缺陷檢測元件的檢測，請參照^圖 1，確認缺陷訊號的數目是否至少等於缺陷檢測元 的數目（步驟120)。若缺陷訊號的數目小於缺陷檢 測το件的數目，則重新調整缺陷檢測參數，並重複: 驟110和步驟120，直到缺陷訊號的數目至少等於二 陷檢測兀件的數目為止。當這些缺陷訊號的數目至乂 等於此些缺陷檢測元件的數目時，所設 二 參數即為適用於缺陷檢測裝置的參數，而不會 測缺陷產生過於靈敏或不靈敏的情況，因此找的= 陷檢測參數可直接套用於之後的晶圓檢測上。、、 綜上所述，本發明之檢測方法，係利用 瞄晶圓，以檢測晶圓上之缺陷檢測元件，以一 ^ 佳的缺陷檢測參數。因此，此方法可更快速找 ^ 合的缺陷檢測參數，以使得檢測缺陷所需的時 ^ 為縮短，並提高製程的良率。 更 而且，在本發明之檢測方法中，可於製程 形成缺陷檢測元件，以降低製程的複雜性， = 製程的成本與人力 咕’ 1292601 1 3 797twf.doc/g 雖然本發明已以較佳實施例揭露如上，然其並非 ^ 用以限定本發明，任何熟習此技藝者，在不脫離本發 明之精神和範圍内，當可作些許之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定 者為準。 【圖式簡單說明】 圖1所繪示為本發明一較佳實施例之缺陷檢測 元件的檢測流程圖。 • 圖2所繪示為本發明一較佳實施例的缺陷檢測 元件之結構的剖面示意圖。 圖3A至圖3D所繪示為依照本發明一較佳實施 例的缺陷檢測元件的製造流程剖面示意圖。 _ 圖4所繪示為本發明另一較佳實施例的缺陷檢 測元件之結構的剖面示意圖。 ’ 圖5所繪示為本發明一實施例的晶圓之上視示 意圖。 圖6A至圖6C所繪示為依照本發明另一較佳實 ® 施例的缺陷檢測元件的製造流程剖面示意圖。 圖7所繪示為本發明晶圓上之數個晶粒區的元 件之上視圖。 圖8所繪示為本發明晶圓上之數個切割道區的 元件之上視圖。 【圖式標示說明】 100、110、120 :步驟 200 :基底 16 1292601 1 3797twf.doc/g 202、302 :導電結構 206、310a、408、614a :缺陷接觸窗 204、306 :間隙壁 204a、208、308、402、406、602、610 ··絕緣層 300、500 :晶圓 304、304a :間隙壁材料層 310、614 :缺陷接觸窗開口 312、612 :接觸窗開口 • 312a、612a :接觸窗 404、604 :導電層 510 :切割道 510a、510b ··切割道區 512、514 :測試鍵位置 516 :摻雜區 • 520 :晶粒 520a、522、524、526 ··晶粒區 606 :導電堆疊結構 • 608 :缺陷堆疊結構 613 :測試鍵 702、802 :缺陷檢測元件 704、804 :導電元件With the continuous development of large-scale integrated circuit technology, the accumulation of integrated circuits is also increasing, and the extremely small defects generated in the process are now a key defect affecting the quality of integrated circuits. In the past decade, defect inspection used to detect defects in the process has become a standard step in the process, and defect detection is a step-by-step process in which wafers are prone to defects or particularly sensitive to defects in the process. Sampling basis to implement. A conventional defect detection method is to try the error method error), first setting a defect detection parameter, and performing a scan of the wafer, and then the operator detects the defective signal ^, and the piece is cut and tested. Confirm that this component is a defective element; If it is confirmed as a defective component, the defect detection parameter can be applied to detect the wafer of the same batch. If it is confirmed that it is not a defective component, another defect detection parameter needs to be set to detect until the component with the defective signal is detected. It is indeed a defective component. However, the above-mentioned trial error method can be said to be quite trivial and time consuming in the process of finding the detection parameters. Another conventional detection method is disclosed in U.S. Patent No. 6,451,185 B1, which uses an optical detecting device to detect a deliberate shape of 1292601 1 3 797 twf. doc/g on a wafer. Appropriate defect detection parameters and apply this parameter to subsequent tests. Narrowly, in this detection method, the defective members deliberately formed on the wafer are limited by the optical detecting device, so they must have a reflective upper surface, so that the defective members are subject to material selection. Many restrictions. Moreover, the fabrication of these defective components can complicate the original process. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a method for detecting a defect detecting 7L member, which solves the problem that the defect detecting process is time-consuming, and the present invention provides another defect detecting component. The manufacturing method simplifies the process of the defect detecting element by simultaneously forming defect detecting elements in the general process. A further object of the present invention is to provide another defect detecting component assembly method for simplifying the process of the defect detecting component by simultaneously forming defect detecting elements in a general process. The purpose of #本,月 is to provide a defect detecting component: by the structure of the defect detecting component, the flow of detecting the missing component can be made more rapid and the result is more accurate. SUMMARY OF THE INVENTION It is an object of the present invention to provide a structure for another defect detecting element which is structured as a defect detecting element, which makes the process of detecting a defect ^ more rapid and more accurate. Ben Maoming proposed a method for detecting a defect detecting component, which comprises forming a plurality of defect detecting elements on a circle, and each of the missing 1292601 1 797 twf.doc/g trapping elements is composed of an insulating layer of the lower layer and a conductive layer stack of the upper layer. It’s made up. (b) Setting a defect detection parameter and scanning the wafer with an electron (e-beam) to obtain a plurality of defect signals. (Improve whether the number of defect signals is at least equal to the number of defect detection elements. If the number of defect signals is less than the number of defect detection elements, re-adjust the defect detection parameters and repeat steps (b) to (c) until the defect signal The number is at least equal to the number of defect detecting elements. The present invention further provides a method for manufacturing a defect detecting device, which is to form a plurality of conductive structures on a wafer. Then, a spacer material layer is formed on the wafer to Covering the electrically conductive structure. Next, = a portion of the spacer material layer, such that the side of the electrically conductive structure == wall, and retaining the layer of spacer material between the opposing spacers on the adjacent two electrically conductive structures. The insulating layer is formed to cover the conductive structure, and the insulating layer has a plurality of opening windows for exposing the material of the spacer. Then, the conductive material is filled in the opening of each defect contact window. A method of manufacturing a defect detecting component for supplying a wafer having a plurality of dicing streets, a layer: ί:; two Γ followed by ' 晶The insulating germanium layer is formed in sequence. Then, the insulating layer and the conductive layer are defined to form a majority of the stack 4 structure, and the defect stacking structure of the defect detection is performed on the cut (5) track. Layer ' 盖盖电堆堆# Structure and defect stacking layer H layer has at least a plurality of defective contact window openings, a "defective stack 4 structure. Then, in each defect contact & 1292601 1 3 797twf.doc / g into one Conductive material. The invention further proposes a structure of a defect detecting element, which comprises a substrate, a defect contact window, a spacer and an insulating layer. f:f includes a plurality of conductive structures, and the defect contact window "window addition" spacer Disposed on the defect contact layer ΐί and the insulating layer is disposed on the defect contact window and the invention further proposes another defect detecting element, the gentleman structure includes the first insulating layer, the conductive layer, the first... the zhanshijin net layer The insulation layer is in contact with the defect and the sound is matched; the younger one, the insulating layer is disposed on the dicing street of the wafer, and the conductive layer f is disposed on the dian-insulating layer. In addition, the second insulating layer covers the conductive surface and the defect contact window is matched. Placed in the second insulating layer, and the detection method of the present invention is determined by deliberately forming on the wafer, and using the electron beam to scan the defects, and the target 2 is determined to be applicable after The lack of parameters for the detection of wafer defects. Therefore, the detection method of the present invention is faster than the conventional method, so that the time for detecting defects can be saved, and the fabrication of the defect detecting component of the present invention can be made simultaneously with the general component fabrication. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. [Embodiment] 1292601 1 3 797 twf. doc/g FIG. 1 is a flow chart showing the detection of a defect detecting element according to a preferred embodiment of the present invention. The detecting method of the defect detecting element of the present invention forms a plurality of defect detecting elements on a wafer (step 100), and each of the defect detecting elements is formed by stacking one insulating layer of the lower layer and one conductive layer of the upper layer. In a preferred embodiment, the structure of the defect sensing element is as shown in Figure 2 and is located on the die of the wafer (shown in Figure 5, 520). This structure is composed of a substrate 200, a defect contact window 206, a spacer 204, and an insulating layer 204a. Moreover, the substrate 200 referred to herein is the wafer described above and has a plurality of conductive structures 202 thereon. In addition, the defect contact window 206 is disposed between the adjacent two conductive structures 202, and the material of the defect contact window 206 is, for example, a conductive material. Additionally, a spacer 204 is disposed between the defect contact window 206 and each of the conductive structures 202. Further, the insulating layer 204a is disposed between the defect contact window 206 and the substrate 200. In a preferred embodiment, the spacers 204 and the material of the insulating layer 204a are, for example, the same. In another preferred embodiment, the structure of the defect detecting element further includes an insulating layer 208 covering the substrate 200 and the conductive structure 202, and the defective contact window 206 is located in the insulating layer 208. The manufacturing method for forming the defect detecting element shown in Fig. 2 described above is, for example, performed simultaneously with the contact window process of the general element, as shown in Figs. 3A to 3D. First, referring to FIG. 3A, a plurality of conductive structures 302 are formed on a wafer 300. The conductive structures 302 can be, for example, a MOS 1292601 1 3 797 twf.doc/g (Metal-Oxide-Semiconductor, MOS) device. Next, a spacer material layer 304 is formed on the wafer 300 to cover the surface of the conductive structure 302. The material of the spacer material layer 304 is, for example, nitride nitride, and the method of forming the spacer material layer 304 is, for example, Chemical vapor deposition (CVD). Thereafter, referring to FIG. 3B, a portion of the spacer material layer 304 is removed to form a spacer 306 on the sidewall of the conductive structure 302 and to retain the spacer material layer 304a. Wherein, the remaining spacer material layer 304a is a position for subsequently forming a defect contact window, and the spacer material layer 304 between the two conductive structures 302 which is subsequently intended to form a contact window is removed. In the above-described formation method, for example, a photoresist layer (not shown) is formed on the spacer material layer 304 by spin coating. Thereafter, a lithography process is performed to form a patterned photoresist layer at a location between adjacent two conductive structures 302 that is intended to form a defect contact window. Next, an etching process is performed to remove a portion of the spacer material layer 304 to form a spacer 306 on the sidewall of the conductive structure 302, and a spacer material layer 304a is formed. Then, the photoresist layer is removed. Next, referring to FIG. 3C, an insulating layer 308 is formed on the wafer 300. The insulating layer 308 is, for example, a dielectric layer. The material of the dielectric layer is, for example, hafnium oxide, tantalum nitride, and hafnium oxynitride. The forming method is, for example, chemistry. Vapor deposition (CVD). Then, referring to FIG. 3D, a defect contact opening 310 and a contact opening 312 are formed in the insulating layer 308, and the defective contact opening 310 exposes the spacer material layer 304a. The defect contact window 1292601 13 79 7 twf. d 〇c/g The opening 310 and the contact window opening 312 are formed by, for example, lithography and silver etching of the insulating layer 308 to form an opening between the conductive structures 3〇2. . Next, the defective contact opening 31 on the wafer 300 is joined, and a conductive material is filled in the window opening 312 to form a defect contact 310a and a contact window 312a. The conductive material is, for example, a metal or a metal alloy, the metal is, for example, tungsten, aluminum, and copper, and the metal alloy is, for example, tungsten telluride. The method of forming the defect contact window 31A and the contact window 312a is, for example, depositing a conductive material layer on the insulating layer 308 to fill the defect contact window opening 310 and the contact window opening 312, and then removing the defective contact window opening 310. A layer of conductive material other than the contact window opening 312. Since the manufacture of the defect detecting element of the present invention can be simultaneously formed in the process of manufacturing the element, it is advantageous to save the cost of the process. Further, in another preferred embodiment, the structure of the defect detecting element is as shown in Fig. 4, which is located on the dicing street of the wafer (shown in Fig. 5, 510). The structure includes an insulating layer, a conductive layer 404, another insulating layer 406, and a defect contact window 4'8. The insulating layer 402 is disposed on the substrate 4 (ie, the dicing street of the wafer), and the conductive layer 4 is disposed on the insulating layer 4〇2. In addition, the insulating layer 406 is embossed with the 'electric layer 404 and the substrate 4', and the defect contact window 4〇8 is disposed in the insulating layer 406 and located on the conductive layer 4〇4, wherein the material of the defect contact window 408 is Conductive material. The manufacturer/column forming the defect detecting element shown in the above item 4 is simultaneously performed with the test 1292601 1 3797 twf.doc/g key process on the joint window of the general component and the scribe line, as shown in Figs. 6A to 6C. Referring to FIG. 5 and FIG. 6A simultaneously, a wafer 500 is first provided, and a plurality of dicing streets 510 are formed on the wafer 500 to define a plurality of dies 520. Then, an insulating layer 602 and a conductive layer 604 are formed on the scribe line regions 510a, 510b of the wafer 500 and the grain region 520a. The material of the insulating layer 602 is, for example, ruthenium oxide, and the formation method is, for example, a thermal oxidation method. The material of the conductive layer 604 is, for example, polycrystalline germanium, and the formation method is, for example, chemical vapor deposition. • Next, referring to FIG. 6B, an insulating layer 602 and a conductive layer 604 are defined to form a plurality of conductive stack structures 606 on the die regions 520a, and a portion 512 of the test track region 510a that is predetermined to form a test key. A plurality of defect stack structures 608 are formed thereon. However, the defect stack structure is not formed on the other test key positions 514 of the scribe line regions 510a, 510b. The method for forming the conductive stack structure 606 and the missing stack structure 608 is, for example, performing a lithography process and an etching process on the insulating layer 602 and the conductive layer 604. Next, ion implantation is performed with the conductive stack structure 606 and the defect stack structure 608 as a mask to form a doped region 516 in the wafer 500. Then, referring to FIG. 6C, an insulating layer 610 is formed on the wafer 500 to cover the conductive stack structure 606, the defect stack structure 608, and the surface of the wafer 500. The material of the insulating layer 610 is, for example, oxidized stone, and the forming method is, for example, chemical vapor deposition. Next, a plurality of contact opening 612 and defective contact opening 614 are formed on insulating layer 610. The contact window opening 612 is located on the wafer 500 of the die region and at other locations 121251 1 3 797 twf.doc/g locations 514 where the test keys are predetermined to be formed, and the defective contact window openings 614 are located at locations 512 where the defect contact windows are predetermined to be formed. Above, it is located on the defect stack structure 608. Then, a conductive material is filled in the opening to form a contact window 612a in the die region 520a, and a test contact 613 defect contact window 614a is formed in the scribe region 510a, 510b. The material of the conductive material is, for example, copper, aluminum or tungsten, and the contact window 612a, the test key 613 and the defect contact window 614a are formed, for example, by depositing a layer of conductive material on the insulating layer to fill the contact opening 612 and contact the defect. The window opening 614 then removes the layer of conductive material other than the contact opening 612 and the defective contact opening 614 and exposes the insulating layer 610. Next, the detection of the defect detecting element is continued. Referring again to Figure 1, a defect detection parameter is set and an electron beam (e-beam) is used to scan the wafer (step 110) to obtain a plurality of scan signals. And detecting, by the defect detecting device, the difference between the scanning signals obtained by the conductive elements on the wafer and the defect detecting elements, thereby detecting the defect signals. In the detection method, an electron beam is used as an incident source of detection. When an electron beam strikes an object to be detected, a secondary electron (SE) of the object to be tested is excited, and the method includes impinging on a conductive structure by an electron beam. The secondary electrons that excite the conductive structure in a close state, impinging on a defect detecting element with an electron beam, excite secondary electrons of the defect detecting element in an open state. Next, it is observed through the image processing system that the position where the amount of secondary electrons excited is large is bright, and the position where the amount of secondary electrons excited is small is a dark (invisible) image. 13 1292601 13797twf.doc/g This contrasting image with different brightness and darkness is used as a judgment to detect the defect -= to take the defect obtained in Figure 3 as an example. Please also 2 and Figure 7. * There are a plurality of two particles on the wafer 5 and one of the grain regions 522 is formed with at least one ==7. The defect detecting element 7〇2 is, for example, a defect contact bony 310a (as shown in FIG. 3D). And the conductive element 7〇4 is formed on the same corresponding position of the bean tray seat, such as the contact panel 312a (as shown in FIG. 3D). And FIG. 7 also shows a schematic view of the upper view. When an electron beam is used for defect detection scanning, the 'electron beam hitting the conductive element 7〇4 will excite the amount of secondary electrons in the path state, and when the electron beam hits the defect detecting element 7〇2, due to the element, the part In a non-conducting state, the amount of secondary electrons in the open state is excited, and the scanning signals obtained by comparing the conductive elements 7〇4 and the defect detecting elements 7 〇2 at the corresponding corresponding positions may have a light-dark image. Different to detect the defect signal. Further, the description of the defect detecting element obtained in Fig. 6C for another type of detection is also referred to Fig. 5, Fig. 6C and Fig. 8. There are a plurality of dicing streets 51 在 on the wafer 500, and at least one of the dicing regions 510a is formed with at least one defect detecting element 8 〇 2, such as a defect contact window 614a (see FIG. 6C). The figure is shown in FIG. 8 and its schematic view is taken as a top view. In addition, conductive elements 804 are formed at the same corresponding positions of the other dicing streets 510b, 51〇c, etc., and the conductive elements 804 are, for example, test keys 613 (as shown in FIG. 14 1292601 13797 twf.d〇c/g / FIG. 6C) ), and FIG. 8 is a schematic diagram of the upper view. When the electron beam scanning is performed, the electron beam hitting the conductive element 8〇4 excites the amount of secondary electrons in the path state, and when the electron beam hits the defect detecting element 80^, the bottom of the element is in a non-conducting state. Then, the amount of secondary electrons in the form of a broken path is excited, and the scanning signals obtained by comparing the conductive elements 804 and the defect detecting elements 8〇2 of the same corresponding position can be detected by a difference between the light and dark images. Defect signal. Then, the detection of the defect detecting element is continued. Referring to Figure 1, it is confirmed whether the number of defective signals is at least equal to the number of defective detecting elements (step 120). If the number of defect signals is less than the number of defect detections, the defect detection parameters are readjusted, and steps 110 and 120 are repeated until the number of defect signals is at least equal to the number of defective detection components. When the number of these defect signals is equal to the number of such defect detecting elements, the two parameters set are the parameters applicable to the defect detecting device, and the defects are not detected to be too sensitive or insensitive, so the found = The trap detection parameters can be applied directly to subsequent wafer inspections. In summary, the detection method of the present invention utilizes an aiming wafer to detect a defect detecting component on a wafer to detect a defect defect parameter. Therefore, this method can find the defect detection parameters more quickly, so that the time required to detect the defects is shortened and the yield of the process is improved. Moreover, in the detection method of the present invention, the defect detecting component can be formed in the process to reduce the complexity of the process, and the cost and labor of the process are as follows: 1292601 1 3 797 twf.doc/g Although the present invention has been preferably implemented The above disclosure is not intended to limit the invention, and any person skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the invention, so that the scope of protection of the present invention is attached. The scope of the patent application is subject to change. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing the detection of a defect detecting element according to a preferred embodiment of the present invention. Figure 2 is a cross-sectional view showing the structure of a defect detecting element in accordance with a preferred embodiment of the present invention. 3A to 3D are cross-sectional views showing the manufacturing process of a defect detecting element in accordance with a preferred embodiment of the present invention. Figure 4 is a cross-sectional view showing the structure of a defect detecting element according to another preferred embodiment of the present invention. Figure 5 is a schematic illustration of a wafer on top of an embodiment of the invention. 6A to 6C are schematic cross-sectional views showing a manufacturing process of a defect detecting element according to another preferred embodiment of the present invention. Figure 7 is a top plan view of the elements of a plurality of die regions on a wafer of the present invention. Figure 8 is a top plan view of the components of a plurality of dicing streets on a wafer of the present invention. [Description of Patterns] 100, 110, 120: Step 200: Substrate 16 1292601 1 3797twf.doc/g 202, 302: Conductive structures 206, 310a, 408, 614a: Defective contact windows 204, 306: Clearance walls 204a, 208 308, 402, 406, 602, 610 · Insulation layer 300, 500: wafers 304, 304a: spacer material layers 310, 614: defect contact window openings 312, 612: contact window openings • 312a, 612a: contact windows 404, 604: conductive layer 510: dicing streets 510a, 510b · dicing track regions 512, 514: test key locations 516: doped regions • 520: dies 520a, 522, 524, 526 · die area 606: conductive Stack Structure • 608: Defect Stack Structure 613: Test Keys 702, 802: Defect Detection Elements 704, 804: Conductive Components