JP2004259851A - Evaluation method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an evaluation method of a semiconductor device, which can measure quickly and statistically the dimensions of each part formed in a semiconductor wafer. <P>SOLUTION: Parallel electron beams ESW passing the aperture of an electron gun arranged in a measurement device are made to radiate in the shape of shower on the surface of a semiconductor wafer, and substrate current Ik is generated with this radiation. In the radiation region of the parallel electron beams ESW, a plurality of resist patterns REG1(1)-REG(4) which correspond to a plurality of gate electrodes in which variation of dimensions may be generated are contained, the variation of each dimension of the plurality of resist patterns is reflected on the substrate current Ik. As a result, dimension of each part of the resist patterns REG can be evaluated statistically by measuring the substrate current Ik. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an evaluation method for evaluating the size of a microfabricated product formed on a semiconductor wafer, and in particular, for measuring a size variation by observing a substrate current generated in a substrate due to irradiation with an electron beam. About technology.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor device that requires high speed, it is important to manage a gate length dimension, a contact / via dimension, a wiring width dimension, and a wiring interval dimension. In particular, as for the gate length dimension, a dimension smaller than the minimum design rule determined by the exposure light source is required, and it is necessary to strictly manage the resist pattern. That is, when forming a gate electrode, a method of once performing an exposure process within the limit of the resolution of the current semiconductor exposure apparatus to form a resist pattern, and then narrowing the resist pattern to a desired size by a so-called trimming process. Is adopted. In this trimming process, since the resist pattern is ashed, the finished dimensions are likely to vary, which causes the gate length dimension to vary. Therefore, in such a case, it becomes more important to control the dimensions of the resist pattern.
[0003]
As a conventional device for managing the above-described critical dimension, a CDSEM (Critical Dimension SEM) is generally used. According to this conventional device, the size of the measured portion can be measured in a non-contact manner by irradiating the measured portion with the electron beam and detecting the secondary electrons emitted from the surface.
As another conventional apparatus of this kind, there is an apparatus that measures a dimension such as a hole diameter in a non-contact manner by observing a substrate current generated when an electron beam is irradiated on a surface of a semiconductor wafer (Patent Document 1). reference). According to this conventional device, since the substrate current due to the electrons reaching the substrate of the semiconductor wafer is observed, the internal shape of the hole is more accurate than when the above-mentioned secondary electrons emitted to the surface side are observed. Can be measured well.
[0004]
[Patent Document 1]
JP-A-2002-83849 (paragraph numbers 0062 to 0081, FIGS. 6 to 12)
[0005]
[Problems to be solved by the invention]
By the way, with the recent miniaturization, it has become necessary to statistically manage the dimensional variation of the microfabricated product of each part formed on the semiconductor wafer. That is, for example, when managing gate dimensions, several sites on the same semiconductor wafer were sampled and measured, and the overall gate length dimension was controlled by the limited measurement values. As the number of elements per unit area increases dramatically, the sampling population also increases dramatically. For this reason, the measured value obtained by sampling is not always representative of the entire gate length dimension formed on the same semiconductor wafer, and it is necessary to increase the number of samplings and measure the dimensions of more parts. .
[0006]
However, according to the above-described conventional technique of observing secondary electrons, there is a problem in that the dimensions of each part must be measured individually, and it takes a lot of time to measure many parts. In addition, since it is necessary to observe the secondary electrons and set the acceleration energy of the electron beam (primary electrons) high or increase the irradiation amount, the object to be measured may be damaged. In particular, when the object to be measured is a resist pattern, irradiation with such an electron beam may cause chemical deformation and shrinkage, which may promote variations in dimensions.
Further, according to the conventional technique of observing the above-described substrate current, the irradiation energy of the electron beam is set low, and the irradiation amount of the electrons can be suppressed, so that the damage to the object to be measured can be suppressed. As in the above-described conventional case, since the dimensions of each part are individually measured, there is a problem that a large measurement time is required when the sampling population increases.
[0007]
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device evaluation method capable of quickly and statistically evaluating the size of each part formed on a semiconductor wafer.
[0008]
[Means for Solving the Problems]
The present invention has the following configuration in order to solve the above problems.
That is, in the method for evaluating a semiconductor device according to the first aspect, a conductive layer serving as a gate electrode of a MOS field-effect transistor is formed, and a resist pattern serving as a mask for processing the conductive layer into the gate electrode is formed. A first step of irradiating electrons to the surface of the semiconductor wafer in a processed state in a shower shape, and measuring a substrate current generated in the substrate of the semiconductor wafer by the irradiation of the electrons in the first step. A second step. In the above-described method for evaluating a semiconductor device, for example, in the first step, the predetermined area of the surface of the semiconductor wafer including a plurality of portions of the resist pattern is irradiated with the electrons.
[0009]
According to a second aspect of the present invention, there is provided a method for evaluating a semiconductor device, wherein a conductive layer serving as a gate electrode of a MOS field effect transistor is formed and a resist pattern serving as a mask for processing the conductive layer into the gate electrode is formed. A first step of irradiating an electron beam toward the surface of the semiconductor wafer in a state, and scanning the surface of the semiconductor wafer with the electron beam; and scanning the semiconductor wafer with the electron beam in the first step. A second step of measuring a substrate current generated in the substrate. The semiconductor device evaluation method may further include, for example, a third step of integrating the substrate current measured in the second step. Further, for example, in the first step, a predetermined region on the surface of the semiconductor wafer including a plurality of portions of the resist pattern is scanned by the electron beam. The method may further include, for example, forming an image of the resist pattern from the substrate current measured in the second step, and correcting acceleration energy of the electron beam based on a state of formation of the image. . The method may further include, for example, evaluating a size of the resist pattern from the substrate current measured in the second step.
[0010]
The method for evaluating a semiconductor device according to a third aspect of the present invention is directed to a method for evaluating a surface of a semiconductor wafer in a process state in which a conductive layer serving as a wiring is formed and a resist pattern serving as a mask for processing the conductive layer into the wiring is formed. And a second step of measuring a substrate current generated in the substrate of the semiconductor wafer with the irradiation of the electrons in the first step. In the above-described method for evaluating a semiconductor device, for example, in the first step, the predetermined area of the surface of the semiconductor wafer including a plurality of portions of the resist pattern is irradiated with the electrons.
[0011]
The method for evaluating a semiconductor device according to a fourth aspect of the present invention is the method of the present invention, wherein a conductive layer serving as a wiring is formed and a resist pattern serving as a mask for processing the conductive layer into the wiring is formed. A first step of irradiating an electron beam toward the substrate and scanning the surface of the semiconductor wafer with the electron beam, and a substrate current generated on the substrate of the semiconductor wafer by the scanning of the electron beam in the first step Measuring a second step. The semiconductor device evaluation method may further include, for example, a third step of integrating the substrate current measured in the second step. Further, for example, in the first step, a predetermined region on the surface of the semiconductor wafer including a plurality of portions of the resist pattern is scanned by the electron beam. The method may further include, for example, forming an image of the resist pattern from the substrate current measured in the second step, and correcting acceleration energy of the electron beam based on a state of formation of the image. . The method may further include, for example, evaluating a size of the resist pattern from the substrate current measured in the second step.
[0012]
A method for evaluating a semiconductor device according to a fifth aspect includes a first step of irradiating electrons in a shower shape toward a surface of a semiconductor wafer in a process state in which wiring is formed, and a step of irradiating the electrons by the first step. A second step of measuring a substrate current generated in the substrate of the semiconductor wafer with the irradiation. In the above-described method for evaluating a semiconductor device, for example, in the first step, the predetermined area of the surface of the semiconductor wafer including a plurality of portions of the wiring is irradiated with the electrons.
[0013]
According to a sixth aspect of the present invention, in the method for evaluating a semiconductor device, the first method includes irradiating an electron beam toward a surface of the semiconductor wafer in a process state where wiring is formed, and scanning the surface of the semiconductor wafer with the electron beam. And a second step of measuring a substrate current generated in the substrate of the semiconductor wafer in accordance with the scanning of the electron beam in the first step. The semiconductor device evaluation method may further include, for example, a third step of integrating the substrate current measured in the second step. Further, for example, in the first step, a predetermined region on the surface of the semiconductor wafer including a plurality of portions of the wiring is scanned by the electron beam. Further, for example, the method further includes a step of evaluating an interval between the wiring patterns from the substrate current measured in the second step. Further, for example, the wiring has a damascene structure.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(1st Embodiment)
FIG. 1 is a schematic configuration diagram of a measuring device 100 according to the first embodiment of the present invention. In FIG. 1, an electron gun 10 emits electrons, and is installed with an electron emission port facing downward. A condenser lens 11 is disposed below the electron gun 10 and converts an electron beam emitted from the electron gun 10 into a parallel electron beam. This parallel electron beam is formed by a semiconductor formed of a semiconductor substrate on which an object to be measured is formed. Irradiation is performed toward the surface of the wafer WF. The cross-sectional area of the parallel electron beam that has passed through the condenser lens 11 is set relatively wide, for example, the beam diameter is set to several tens to several hundreds microns.
[0015]
An aperture 12 having a predetermined opening 120 is arranged below the condenser lens 11 to block a part of the parallel electron beam that has passed through the condenser lens 11, and the rest is actually formed as a parallel electron beam ESW on the surface of the semiconductor wafer WF. Irradiation. FIG. 2 is a top view of the aperture 12 and shows an example of the opening 120 described above. FIG. 7A shows a case where the opening 120 is formed in a circular shape, and FIG. 7B shows a case where the opening 120 is formed in a square shape. The area of the opening 120 is set to a value smaller than the cross-sectional area of the beam of the parallel electron beam that has passed through the condenser lens 11, and the aperture 12 sets the irradiation area of the parallel electron beam on the surface of the semiconductor wafer WF to a predetermined area. Set to. The aperture 12 is made of metal or the like, and is grounded so that electrons do not accumulate. In this embodiment, as shown in FIG. 2B, the opening 120 is formed in a square shape.
[0016]
A movable stage 14 for mounting the semiconductor wafer WF is arranged in the direction of irradiation of the parallel electron beam passing through the aperture 12. The movable stage 14 places the semiconductor wafer WF such that the parallel electron beam ESW passing through the aperture 12 is irradiated substantially perpendicularly to the surface of the semiconductor wafer WF, and is substantially in the emission direction of the parallel electron beam EWS. It is configured to be able to move in an orthogonal plane (XY plane). Further, an electrode 13 for collecting a substrate current is attached to the front surface of the movable stage 14 so as to be in contact with the back surface of the semiconductor wafer WF. Although not shown, the movable stage 14 is provided with a mechanism for adsorbing the wafer WF, and the semiconductor wafer WF is adsorbed and fixed while being placed on the electrode 13. The electrode 13 is electrically connected to an ammeter 15, and the ammeter 15 measures a substrate current Ik generated in a substrate SUB of a semiconductor wafer described later.
[0017]
FIG. 3A shows an appearance of a semiconductor wafer WF made of a silicon single crystal. On the main surface of the semiconductor wafer WF, a plurality of chips having the same pattern are formed in a matrix. FIG. 3B is an enlarged view of a region WFA on the semiconductor wafer WF. The area WFA is a part of one chip on the semiconductor wafer, and another chip on the same semiconductor wafer has an area having the same pattern as the area WFA. In the first embodiment, the region WFA is the irradiation region of the parallel electron beam ESW shown in FIG. 1 described above, and the shape of the opening 120 of the aperture 12 that defines the irradiation region matches the shape of the region WFA described above. Is set to Further, the irradiation area WFA is an area where an object to be measured exists, and is a predetermined area determined in advance for measurement.
[0018]
In the example shown in FIG. 3B, active areas ACP1, ACP2, and ACP3 of p-channel MOS field-effect transistors and active areas ACN1 and ACN2 of n-channel MOS field-effect transistors are formed in the area WFA. A polysilicon layer POL (not shown in FIG. 3) which will be described later as a gate electrode of a MOS field effect transistor is formed over the entire surface of the semiconductor wafer WF, and a mask for forming the gate electrode is further formed thereon. Is formed. In the first embodiment, as described above, the polysilicon layer which is the conductive layer serving as the gate electrode of the MOS field effect transistor is formed on the entire surface of the semiconductor wafer, and the mask for processing the polysilicon layer into the gate electrode is formed. The semiconductor wafer WF in the process state where the resist pattern REG to be formed is formed is an object to be measured.
[0019]
By etching the polysilicon layer using the resist pattern REG as a mask in a step after the formation of the resist pattern REG, the polysilicon layer in a region covered by the resist pattern REG remains as a gate electrode. Accordingly, variations in the size of the resist pattern REG appear as variations in the size of the gate electrode. For this reason, managing the dimensional variation of the resist pattern REG is extremely important in managing the product yield. In this example, the predetermined region WFA irradiated with the parallel electron beam ESW includes a plurality of portions of the resist pattern REG that affect the measured value of the substrate current Ik described later and that affect the gate length dimension. Have been. The plurality of portions coincide with portions that affect a measured value of substrate current Ik described later.
[0020]
4A and 4B show details of the periphery of the active area ACN1 described above. FIG. 4A is a top view, and FIG. 4B is a cross-sectional view taken along line AA in FIG. FIG. 3C is a sectional view taken along line BB shown in FIG. As shown in FIGS. 7B and 7C, an insulator TR for element isolation is buried in the substrate SUB of the semiconductor wafer, and a region surrounded by the insulator becomes the above-described active region ACN1. . A gate oxide film OX is formed on the surface of the substrate SUB on which the insulator TR is formed, and a polysilicon layer POL serving as a gate electrode is stacked thereon. A resist, which is a photoreceptor serving as a mask when etching this polysilicon layer, is formed on the entire surface of the wafer on the polysilicon layer POL, and then a gate pattern is transferred by a semiconductor exposure apparatus to correspond to the gate electrode. A resist pattern REG having a shape is formed by etching. In this example, focusing on the active region ACN1, a state is shown in which resist patterns REG (1 to 4) corresponding to four gate electrodes are formed. Since the current characteristics of a MOS field-effect transistor are proportional to the gate width, when a MOS field-effect transistor having desired current characteristics is formed in a limited area, a plurality of gates are generally provided in one active area as in this example. A technique has been adopted in which electrodes are formed and a plurality of MOS field-effect transistors electrically connected in parallel are formed.
[0021]
Next, the operation (evaluation method) of the measuring apparatus according to the first embodiment will be described with reference to FIGS. FIG. 5 shows the distribution of the substrate current Ik when the region shown in FIG. 4B is irradiated with the parallel electron beam ESW. FIG. 6 shows the removal of the polysilicon POL by etching using the resist REG as a mask. The distribution of the substrate current Ik (broken line) after the removal and the distribution of the substrate current Ik (solid line) before the removal are shown.
First, as shown in FIG. 1, a semiconductor wafer WF is placed on the electrode 13, and a region WFA shown in FIG. 3 is irradiated with a shower-like parallel electron beam ESW. At this time, since the shape of the opening 120 of the aperture 12 matches the shape of the area WFA, the entire area WFA is irradiated with the parallel electron beam ESW, and the other areas are irradiated with the parallel electron beam ESW. Not done. A substrate current Ik is generated in the substrate SUB with the irradiation of the region WFA with the parallel electron beam ESW, and the substrate current Ik is measured by the ammeter 15 through the electrode 13.
[0022]
Here, of the parallel electron beams ESW applied to the region WFA of the semiconductor wafer, the electrons incident on the region excluding the resist pattern REG, that is, the region where the polysilicon layer POL is exposed on the surface are poly-electrodes serving as conductive members. It diffuses quickly throughout the silicon layer POL. Between the polysilicon layer and the substrate SUB, a gate oxide film OX, which is an insulator, exists as an electrical resistance component, but since the polysilicon layer POL is formed over the entire surface of the semiconductor wafer WF, Equivalently, they behave as countless parallel resistors. Therefore, it can be considered that the polysilicon layer POL and the substrate SUB are electrically connected to each other, and electrons incident on the polysilicon layer POL flow into the substrate SUB via the gate oxide film OX, and the substrate current Ik It becomes.
[0023]
If the acceleration energy of the parallel electron beam ESW is appropriately set, the electron beam does not reach the substrate SUB in the region where the resist pattern REG shown in FIG. 5A exists, and the electron beam does not reach the substrate SUB in the region where the resist REG does not exist. It reaches SUB. Therefore, as shown in FIG. 3B, the distribution of the substrate current Ik in the substrate SUB is such that the substrate current in the region where the resist pattern REG exists is small, and the substrate current in the region where the resist pattern REG does not exist is opposite. Become larger. The substrate currents generated in the respective regions merge into a substrate current Ik, which is measured by the ammeter 15. In the example shown in FIG. 5, the substrate current Ik measured by the ammeter 15 is a region R1 between the insulator TR (L) and the resist REG (1) and a region R1 between the resists REG (1) to REG (4). Are the sum of the substrate currents generated in each of the regions R2, R3, R4, and the region R5 between the resist REG (4) and the insulator TR (R).
[0024]
Subsequently, the dimension of the resist pattern REG is evaluated from the value of the substrate current Ik described above. Here, the measured value of the substrate current Ik itself indicates the dimensions of the regions R1 to R5 where the resist pattern REG does not exist, and directly determines the dimensions of the regions of the resist patterns REG (1) to (5). Can be obtained by subtracting the above-described substrate current Ik from the value of the substrate current that would be measured when the resist pattern REG does not exist. However, focusing on the active region ACN1, since the regions R1 to R5 and the regions of the resist patterns REG (1) to REG (5) have a complementary relationship, the substrate current Ik indirectly determines the size of the resist pattern REG. In effect, the dimensions of the resist pattern REG can be evaluated from the measured substrate current Ik.
[0025]
The substrate currents generated in the regions R1 to R5 depend on the area of each region, and the area of each region depends on the dimensions of the resist patterns REG (1) to REG (4). The substrate current Ik measured at 15 is a value of a plurality of portions of the resist pattern REG that affect the measured value of the substrate current Ik (each portion of the resists REG (1) to REG (4) that affect the gate length). This includes all the dimensional variations, and therefore, it is possible to comprehensively grasp the variances of the respective portions of the resist REG from the substrate current Ik.
[0026]
Here, strictly speaking, the substrate current Ik includes the dimensional variation of the active region ACN1 in addition to the dimensional variation of the resist pattern REG. However, by providing a plurality of portions of the resist pattern REG in the electron beam irradiation region, the line segment of the edge of the resist pattern REG can be made relatively large with respect to the outer peripheral length of the active region ACN1. Therefore, the variation in the size of the active region ACN1 can be ignored, and the variation in the size of the resist pattern REG can be effectively grasped from the substrate current Ik. As the number of portions of the resist pattern REG included in the region WFA increases, the influence of the variation in the active region is suppressed, and the variation in the resist pattern can be grasped more accurately.
[0027]
In the first embodiment, since the parallel electron beam ESW is applied to the entire area WFA, the substrate current Ik measured by the ammeter 15 has an effect on the value of the substrate current value Ik in the area WFA. The dimensions of the entire portion of the resist pattern REG (ie, the entire portion of the resist pattern REG that influences the gate length dimension in the region WFA) that reflects the pattern are reflected, and the variation is evaluated in units of the region WFA.
The same measurement is performed on several other chips having the same pattern in the plane of the semiconductor wafer WF, and by comparing the substrate current Ik measured in each region, the same measurement is performed in the plane of the semiconductor wafer WF. Variations in the dimensions of the resist pattern REG can be relatively grasped. If absolute variations are to be evaluated, a substrate current in a region of the same pattern may be measured in advance using a reference semiconductor wafer, and evaluation may be performed based on the substrate current.
[0028]
As described above, by including a plurality of portions of the resist pattern REG that affect the measured value of the substrate current Ik in the irradiation region of the parallel electron beam ESW, the influence of the dimensional variation of the plurality of portions is reduced by the substrate current Ik. Can be included comprehensively. Therefore, the dimensional variation of a plurality of parts can be collectively measured by one measurement, and as a result, even if the sampling population is increased, it is possible to evaluate the statistical variation in a short time. become. In addition, according to the first embodiment, if the irradiation area of the parallel electron beam ESW is enlarged, the variation in more parts is reflected on the measured value of the substrate current Ik, and the number of samplings is greatly increased. It is possible to obtain a measurement result when the number is increased. Therefore, even if the number of elements per unit area increases due to miniaturization, it is possible to accurately evaluate variations in a short time.
[0029]
Further, as shown in FIG. 6, by measuring the substrate current Ik before and after etching the polysilicon POL using the resist pattern REG as a mask, it is also possible to compare and evaluate variations in the size of the resist pattern and the gate size. it can. That is, in FIG. 3A, a broken line indicates a region where the polysilicon layer POL is peeled off by etching, and in FIG. 3B, a substrate current Ik indicated by a broken line is shown in FIG. A current measured after etching the polysilicon layer POL using the resist pattern REG as a mask is shown, and a substrate current Ik indicated by a solid line indicates a substrate current Ik measured before etching the polysilicon layer POL. As can be understood from this figure, if the substrate current Ik before and after etching is measured using the measurement method according to the first embodiment, the variation in only the size of the resist pattern and the variation in the gate size can be compared. Can be evaluated.
[0030]
In the above example, the resist pattern REG serving as a mask when forming a gate electrode has been described as an example. However, as shown in FIG. 7, the same applies to a resist pattern REGH serving as a mask when forming a metal wiring. can do. The example shown in the drawing has a two-layer wiring structure, and a first-layer wiring H1 is formed on an insulating layer F formed on a substrate SUB. A wiring layer H2 serving as a second layer wiring is formed on the entire surface of the semiconductor wafer on the insulating layer F. When the wiring layer H2 is processed into a second layer wiring on the wiring layer H2. A resist pattern REGH serving as a mask is formed. The second wiring layer is connected to the first wiring via a via contact, and the first wiring is also connected to the substrate SUB via the contact. Generally, in the case of a process of forming a wiring using the resist pattern REGH, in a state before the etching in which the wiring layer H2 is formed on the entire surface of the semiconductor wafer, the wiring layer H2 is connected to the first layer somewhere via a via contact. The first-layer wiring H1 is further connected to the substrate SUB on the lower layer side. Therefore, when the wiring H2 is formed on the entire surface of the semiconductor wafer, there is always a path for electrically connecting the uppermost wiring layer H2 and the substrate SUB. This is the same even when the number of wiring layers increases.
[0031]
When the surface of the semiconductor wafer in such a process state is irradiated with the parallel electron beam ESW, the electrons incident on the wiring layer H2 flow into the substrate SUB via the via contact and the first-layer wiring H1, and the substrate current is reduced. Form. Therefore, the substrate current Ik can be measured as in the case of forming the gate electrode described above, and it is possible to evaluate the variation of the resist pattern REGH for forming the second-layer wiring from the measured value. . The present invention is not limited to the example of the two-layer wiring structure, and can be applied to a wiring structure having an arbitrary number of layers. The substrate current Ik may be appropriately measured in a process state in which a resist pattern to be managed is formed. It should be noted that the principle of evaluation is essentially different from the above-described conventional method of measuring the diameter of a hole formed on a substrate in that electrons are guided to the substrate via a wiring layer formed over the entire surface of the semiconductor wafer. are doing. By irradiating electrons with the uppermost wiring layer formed on the entire surface of the semiconductor wafer in this way, the size of the resist pattern can be evaluated without being restricted by the number of wiring layers.
[0032]
Next, with reference to FIG. 8, a method for evaluating the dimensions (width and interval) of the wiring M made of a metal layer will be described. The measuring device for measuring the substrate current is the same as that used for measuring the above-described resist pattern REG.
The example shown in FIG. 8 is an example of a wiring having a so-called damascene structure. That is, an insulating layer F is formed on the substrate SUB, a contact hole CH is opened in the insulating layer F, and a plug serving as a conductive member is embedded in the contact hole CH. A trench CT is formed on the upper surface of the semiconductor wafer so as to be located on the upper end side of the contact hole CH, and a conductive member such as copper serving as a wiring is embedded therein. Thereafter, excess wiring metal is removed by a chemical mechanical polishing method (polishing technique using chemicals together), and a wiring M is formed.
[0033]
When measuring the dimensions of the wiring M having the above-described damascene structure, the surface of the semiconductor wafer in the process state where the wiring M is formed is irradiated with the shower-like parallel electron beam ESW described above, and the substrate current Ik is similarly reduced. Measure. In this case, of the parallel electron beams ESW, electrons incident on the wiring M are collected by the wiring M and flow into the substrate SUB. Therefore, also in this case, the influence of the variation in the dimensions of the wiring M is reflected on the substrate current Ik, and the variation in the dimensions of the wiring M can be grasped from the substrate current Ik. Even when measuring the variation in the dimensions of the wiring M, the irradiation region of the parallel electron beam ESW may be determined to be a predetermined region so as to include a plurality of portions that affect the value of the substrate current Ik.
[0034]
Further, the value of the substrate current Ik itself directly depends on the size (area) of the wiring M. However, in this example, the width and the interval of the wiring M are complementary to each other, and thus are measured. The interval (dimension corresponding to the region RM) of the wiring M can be evaluated from the substrate current Ik thus obtained. In the example shown in FIG. 8, a one-layer wiring structure is shown, but the present invention is not limited to this and can be similarly applied to a multi-layer wiring structure. That is, for example, in the case of a two-layer wiring structure, measurement is performed on the first-layer wiring pattern in the same manner as described above. Similarly, if the second-layer wiring pattern is electrically connected to the first-layer wiring via a via contact or the like, the electrons incident on the second-layer wiring pattern reach the substrate. The substrate current Ik can be measured. Hereinafter, the same measurement is possible regardless of the number of wiring layers. Further, although the damascene structure is shown in the example shown in FIG.
[0035]
(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described.
In the above-described first embodiment, a predetermined region is irradiated with the parallel electron beam ESW. However, in this embodiment, by scanning the region WFA with an electron beam, a variation in the size of the resist REG is similarly reduced. Measure statistically.
FIG. 9 shows a measuring device according to the second embodiment. The measuring apparatus has a function of scanning an area WFA on a semiconductor wafer WF with an electron beam narrowed down to a micron order as compared with the measuring apparatus according to the first embodiment shown in FIG. In this case, the configuration is different in that it has a function of calculating the total current by integrating the substrate current Ik generated in the substrate SUB of the semiconductor wafer.
[0036]
That is, in FIG. 9, the electron gun 20 is the same as the above-described electron gun 10 and emits electrons downward. A first condenser lens 21 similar to the condenser lens 11 described above is disposed below the electron gun 20, and converts an electron beam emitted from the electron gun 20 into a parallel electron beam. An aperture 22 having a smaller opening 220 is disposed below the first condenser lens 21 to convert a parallel electron beam passing through the condenser lens 21 into a parallel electron beam having a smaller beam diameter. A second condenser lens 23 is disposed below the aperture 22, and the beam diameter of the parallel electron beam that has passed through the aperture 22 is narrowed to be incident on the objective lens 24. An electron beam EB having a small beam diameter on the order of 100 angstroms is formed by the objective lens 24, and is applied to the surface of the wafer WF.
[0037]
A movable stage 26 on which the semiconductor wafer WF is mounted is arranged in the irradiation direction of the electron beam EB. The movable stage 26 is basically the same as the movable stage 14 described above, but moves relative to the electron beam EB so that the electron beam EB moves a predetermined region on the surface of the semiconductor wafer WF. It is configured to scan. On the upper surface of the movable stage 26, an electrode 25 for collecting a substrate current similar to the above-described electrode 13 is attached, and this electrode 25 is connected to an ammeter 27 for measuring a substrate current similar to the above-described ammeter 15. Is electrically connected to the Further, an integrator 28 for integrating the current waveform measured by the ammeter 27 is connected to the ammeter 27.
[0038]
The operation of the second embodiment will be described.
It is assumed that the semiconductor wafer WF to be measured is in a process state in which the resist pattern REG is formed as in the first embodiment.
The surface of the semiconductor wafer WF is scanned with the electron beam EB that has passed through the above-described objective lens 24, and the substrate current Ikk generated on the substrate SUB of the semiconductor wafer due to the scanning is measured by the ammeter 27. The scanning area in this case is set to the same irradiation area (predetermined area) as in the first embodiment described above, and the control unit (not shown) controls the moving amount of the movable stage 26 so that the electron beam EB scans this area. Control. Thus, the substrate current Ikk having the same waveform as the substrate current waveform shown in FIG. 5B is measured in time series with the scanning of the electron beam EB. However, in the second embodiment, the surface of the semiconductor wafer is scanned using the electron beam EB having a small beam diameter, instead of the shower-shaped parallel electron beam ESW as in the first embodiment. The measured substrate current Ikk is such that partial current values measured for each scanning position appear in time series.
[0039]
The substrate current Ikk measured in this way is integrated by the integrator 28, and the substrate current Ik including the influence of variations at each part is obtained. In principle, the substrate current Ik obtained by this integration has a value similar to that in the case where the predetermined region is irradiated with the parallel electron beam ESW, as in the first embodiment. From the value of the substrate current Ik, the size of the resist pattern REG is evaluated in the same manner as in the first embodiment. Therefore, according to the second embodiment as well, it is possible to accurately and statistically evaluate the dimensional variation of the resist pattern REG, as in the first embodiment. Further, not only the variation in the resist pattern of the gate electrode but also the variation in the resist pattern of the wiring M described above and the variation in the width and the interval of the wiring M using the substrate current Ik obtained by the integrator 28. Can be evaluated. The principle is the same as in the first embodiment, and a description thereof will be omitted.
[0040]
Next, a modification of the second embodiment will be described.
In the above-described second embodiment, the integrator 28 integrates the substrate current Ikk. However, the integrator 28 may evaluate the variation from the measured substrate current Ikk. Can be used. In this case, the measured substrate current Ikk itself is stored in a storage device as measurement data in association with a scanning position (irradiation position), and by reading and using the measurement data, various types of data as exemplified below can be obtained. Evaluation is possible. That is, as a first example, an image of the resist pattern REG and the wiring M is formed from the above measurement data. For example, an image of a resist pattern is obtained from a waveform obtained by plotting measured values with respect to a scanning position. The acceleration energy of the electron beam is corrected based on the state of image formation. That is, since the above-described measurement data is the substrate current measured for each scanning position, the value depends on the presence or absence of the resist pattern REG (or the wiring M) as in the example shown in FIG. Shows a tendency to increase or decrease. However, since the amount of electrons penetrating through the resist pattern etc. changes according to the acceleration energy of the electron beam, if the acceleration energy is too high or too low, the shape of the resist pattern in the process will match the image based on the measured values. Gone. Therefore, the acceleration energy of the electron beam is optimally corrected so that the image matches the shape of the actual resist pattern. As a result, it is possible to appropriately reflect the actual dimensional variation on the measured value of the substrate current.
[0041]
A second example is to grasp the vertical structure of each resist pattern REG from the above measurement data. In this case, a plurality of scans are performed with the acceleration energy of the electron beam set to a plurality of different values (for example, 500 eV, 1 KeV, etc.). Thereby, a plurality of substrate currents Ikk are measured for the film thickness of the resist pattern REG, and the vertical structure of the resist pattern REG can be grasped from the measured values. As described above, as a result of the trimming process, the resist pattern REG exhibits a rounded and skirted shape as shown in FIG. 6A, and the shape of the skirt greatly affects the variation in gate dimensions. Has become. Therefore, it is important to understand the vertical structure of the resist pattern REG in evaluating the variation of the resist pattern REG. By controlling the acceleration energy of the electron beam as described above, the vertical structure can be analyzed. That is, the dimensions of the true resist pattern REG can be grasped.
[0042]
A third example is to analyze the influence of the density of the resist pattern, the wiring pattern, and the like, that is, the loading effect, from the above-described measurement data. It is known that the loading effect occurs independently at the exposure stage and the etching stage. By analyzing the image of the resist pattern REG obtained from the above measurement data, it is possible to grasp the loading effect that occurs at the stage of exposure. Also, from the measurement data at the stage of etching the polysilicon layer POL using the resist pattern REG as a mask, it is possible to grasp the loading effect that occurs at the stage of etching the polysilicon layer POL. In this way, it is possible to compare and examine the loading effect from the measurement data at each process stage.
[0043]
A fourth example is to improve the S / N ratio of the measurement value at each scanning position by performing scanning with the electron beam a plurality of times on the same region and accumulating the substrate current Ikk for each scanning. . That is, for example, at the stage of measuring the overall variation, one scan is performed, and the measurement result is analyzed. As a result, an area requiring detailed analysis is partially re-scanned, the measured value of the substrate current Ikk in that area is accumulated, and measurement data with a good S / N ratio is obtained. Detailed analysis is performed using the measurement data.
As a fifth evaluation example, for example, p-channel MOS field-effect transistors and n-channel MOS field-effect transistors are separated from the above measurement data, and the substrate current of each resist pattern is separated and analyzed. This makes it possible to separately evaluate the variations in the resist pattern for each of the n-channel and p-channel MOS field-effect transistors. Of course, if the measured value corresponding to a single MOS field-effect transistor is used, it is possible to evaluate the variation corresponding to each transistor, and necessary data may be extracted from the measured data and used according to the evaluation target.
[0044]
Hereinafter, effects of the above-described embodiment will be described.
(1) Since the substrate current is observed, it is possible to specify a portion having a critical thickness at which the resist can act as a mask, and to determine the dimension of the critical dimension from a change in current at that portion. Can be.
(2) A large number of gate dimensions and wiring dimensions serving as critical dimensions can be measured in a short time, and the distribution of variations on the semiconductor wafer surface can be easily obtained. In addition, by combining with a technology such as a 3D CDSEM or an EB scope (three-dimensional structural analysis device) and using these technologies in a review manner, it is possible to more accurately manage the variation.
(3) Measurements before and after the etching of the resist are performed in accordance with the same principle, and mapping of gate dimensions and the like within the wafer surface can be performed.
(4) Since the substrate current is observed, measurement can be performed with the electron acceleration energy set low and the electron beam irradiation amount (dose amount) set small. Therefore, damage to the object to be measured can be extremely small, and damage-free can be practically realized.
(5) According to the second embodiment of scanning with an electron beam, it is possible to statistically evaluate the dimensional variation of a fine workpiece on a semiconductor wafer using a conventional substrate current measuring device. Become. The output of the electron gun may be small.
[0045]
【The invention's effect】
According to the first aspect, electrons are irradiated in a shower shape toward the surface of the semiconductor wafer on which the resist pattern serving as a mask of the gate electrode is formed, and the substrate current generated in the semiconductor wafer is measured. In addition, it is possible to quickly and statistically measure the dimension of a resist pattern serving as a gate electrode.
According to the second aspect, the surface of the semiconductor wafer on which the resist pattern serving as a mask for the gate electrode is formed is scanned with an electron beam, and the substrate current generated in the semiconductor wafer is measured and integrated. Therefore, the size of the resist pattern serving as the gate electrode can be quickly and statistically measured using a small output electron beam.
[0046]
According to the third aspect of the present invention, electrons are emitted in a shower shape toward the surface of the semiconductor wafer on which the resist pattern serving as a wiring mask is formed, and the substrate current generated on the semiconductor wafer is measured. Therefore, it is possible to quickly and statistically measure the dimension of a resist pattern serving as a wiring mask.
According to the fourth aspect, the surface of the semiconductor wafer on which the resist pattern serving as a wiring mask is formed is scanned with an electron beam, and the substrate current generated on the semiconductor wafer is measured and integrated. Using a small output electron beam, it is possible to quickly and statistically measure the dimension of a resist pattern serving as a wiring mask.
[0047]
According to the fifth aspect of the invention, electrons are irradiated in a shower shape toward the surface of the semiconductor wafer on which the wiring pattern is formed, and the substrate current generated on the semiconductor wafer is measured. And it can be measured statistically.
According to the sixth aspect, the surface of the semiconductor wafer on which the wiring pattern is formed is scanned with the electron beam, and the substrate current generated on the semiconductor wafer is measured and integrated. With this, it is possible to measure the dimensions of the wiring quickly and statistically.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a measuring device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of an opening provided in an aperture of the measuring device according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a semiconductor wafer as an object to be measured and a partial area thereof according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a structure of an n-channel MOS field-effect transistor formed on a semiconductor wafer which is an object to be measured according to the first embodiment of the present invention.
FIG. 5 is a diagram for explaining an evaluation method (a method of evaluating a resist pattern) using the measurement apparatus according to the first embodiment of the present invention.
FIG. 6 is a diagram for explaining an evaluation method (an evaluation method before and after etching of polysilicon) using the measuring apparatus according to the first embodiment of the present invention.
FIG. 7 is a diagram for explaining an evaluation method (a wiring evaluation method) using the measuring apparatus according to the first embodiment of the present invention.
FIG. 8 is a diagram for explaining an evaluation method (a method of evaluating a wiring having a damascene structure) using the measurement apparatus according to the first embodiment of the present invention.
FIG. 9 is a diagram showing a configuration of a measuring device according to a second embodiment of the present invention.
[Explanation of symbols]
10; electron gun, 11; condenser lens, 12; aperture, 13; electrode, 14; movable stage, 15; ammeter, 20; electron gun, 21; first condenser lens, 22, aperture, 23; 24, objective lens, 25; electrode, 26; movable stage, 27; ammeter, 28; integrator, ESW; parallel electron beam, EB; electron beam, WF; semiconductor wafer, WFA; Pattern, POL; polysilicon layer, OX; gate oxide film, ACN1; active area, TR; insulator, SUB; substrate, F; insulating layer, M, H1; wiring, H2; .

Claims (21)

Electrons are showered toward a surface of a semiconductor wafer in a process state where a conductive layer serving as a gate electrode of a MOS field effect transistor is formed and a resist pattern serving as a mask for processing the conductive layer into the gate electrode is formed. A first step of irradiating the shape,
A second step of measuring a substrate current generated in the substrate of the semiconductor wafer with the irradiation of the electrons in the first step;
A semiconductor device evaluation method including: 2. The method according to claim 1, wherein in the first step, a predetermined region on the surface of the semiconductor wafer including a plurality of portions of the resist pattern is irradiated with the electrons. 3. An electron beam is directed toward the surface of a semiconductor wafer in a process state where a conductive layer serving as a gate electrode of a MOS field effect transistor is formed and a resist pattern serving as a mask for processing the conductive layer into the gate electrode is formed. Irradiating and scanning the surface of the semiconductor wafer with the electron beam;
A second step of measuring a substrate current generated in the substrate of the semiconductor wafer along with the scanning of the electron beam in the first step;
A semiconductor device evaluation method including: 4. The method according to claim 3, further comprising a third step of integrating the substrate current measured in the second step. 5. The method according to claim 3, wherein in the first step, a predetermined region on the surface of the semiconductor wafer including a plurality of portions of the resist pattern is scanned by the electron beam. 6. 4. The method according to claim 3, further comprising forming an image of the resist pattern from the substrate current measured in the second step, and correcting acceleration energy of the electron beam based on a state of formation of the image. 6. The method for evaluating a semiconductor device according to any one of 5. 7. The method according to claim 1, further comprising the step of: evaluating a size of the resist pattern from a substrate current measured in the second step. A first step of irradiating electrons in a shower shape onto a surface of a semiconductor wafer in a process state where a conductive layer serving as a wiring is formed and a resist pattern serving as a mask for processing the conductive layer into the wiring is formed; Steps and
A second step of measuring a substrate current generated in the substrate of the semiconductor wafer with the irradiation of the electrons in the first step;
A semiconductor device evaluation method including: 9. The semiconductor device evaluation method according to claim 8, wherein in the first step, a predetermined region on the surface of the semiconductor wafer including a plurality of portions of the resist pattern is irradiated with the electrons. A conductive layer serving as a wiring is formed, and an electron beam is irradiated toward a surface of a semiconductor wafer in a process state in which a resist pattern serving as a mask for processing the conductive layer into the wiring is formed. A first step of scanning the surface of the semiconductor wafer;
A second step of measuring a substrate current generated in the substrate of the semiconductor wafer along with the scanning of the electron beam in the first step;
A semiconductor device evaluation method including: 11. The method according to claim 10, further comprising a third step of integrating the substrate current measured in the second step. The method according to claim 10, wherein in the first step, a predetermined region on the surface of the semiconductor wafer including a plurality of portions of the resist pattern is scanned with the electron beam. 11. The method according to claim 10, further comprising forming an image of the resist pattern from the substrate current measured in the second step, and correcting acceleration energy of the electron beam based on a state of formation of the image. 13. The method for evaluating a semiconductor device according to any one of 12. 14. The method according to claim 8, further comprising the step of: evaluating a size of the resist pattern from the substrate current measured in the second step. A first step of irradiating electrons in the form of a shower toward the surface of the semiconductor wafer in a process state where the wiring is formed;
A second step of measuring a substrate current generated in the substrate of the semiconductor wafer with the irradiation of the electrons in the first step;
A semiconductor device evaluation method including: The method according to claim 15, wherein, in the first step, a predetermined region on a surface of the semiconductor wafer including a plurality of portions of the wiring is irradiated with the electrons. A first step of irradiating an electron beam toward a surface of the semiconductor wafer in a process state where wiring is formed, and scanning the surface of the semiconductor wafer with the electron beam;
A second step of measuring a substrate current generated in the substrate of the semiconductor wafer along with the scanning of the electron beam in the first step;
A semiconductor device evaluation method including: The method according to claim 17, further comprising a third step of integrating the substrate current measured in the second step. 19. The semiconductor device evaluation method according to claim 17, wherein in the first step, a predetermined region on the surface of the semiconductor wafer including a plurality of portions of the wiring is scanned by the electron beam. 20. The method for evaluating a semiconductor device according to claim 15, further comprising a step of evaluating an interval between the wiring patterns from a substrate current measured in the second step. 21. The method for evaluating a semiconductor device according to claim 15, wherein the wiring has a damascene structure.

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