1290675 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種設計錯誤的檢查系統及方法，更 詳而言之，係有關於一種使電路板佈線之設計規則檢查 (Design Rules Check ; DRC)後所判定出的錯誤更符合電 路板錯誤檢查之實際需求的設計錯誤的檢查系統及方法。 【先前技術】 近年來對印刷電路板（printed Circuit B〇ard，以 佈局佈線的要求越來越複雜，積體電路中電晶體數量不斷 均加彳之而使得盗件速度更快且每個脈衝緣上升時間縮 -短’同時接腳數也越來越多。相對的隨著積體電路數量的 •密集化，在電路板設計上將產生時脈、阻抗、檢測以及串 擾等方面的問題。-般而言，阻抗、走線長度及間隙等方 =疋影響因素之-，通常稱爲關鍵性節點（net)，而影塑 ^主要是由於參數相關性以及設計要求越來越複雜而』 線路板ΓΓΓ條走線_隔可能取決於—個和節點電壓及 線路板材料都有關的函數，晶片的脈 和低速的設計都會產生影響。 T間減小對同速 。之前，大部份電路板上只有少數節點，1290675 IX. Description of the Invention: [Technical Field] The present invention relates to a design error checking system and method, and more particularly to a design rule check for circuit board wiring (Design Rules Check; The design error detection system and method that the error determined after DRC is more in line with the actual needs of the board error check. [Prior Art] In recent years, the printed circuit board (printed circuit B〇ard, the layout wiring requirements are more and more complicated, the number of transistors in the integrated circuit is constantly increasing, making the stealing speed faster and each pulse The edge rise time is shortened-short' and the number of pins is also increasing. Relatively, with the intensive number of integrated circuits, problems such as clock, impedance, detection, and crosstalk are generated in the board design. In general, the impedance, the length of the trace and the gap, etc., are often referred to as the critical nodes (net), while the shadows are mainly due to the increasing complexity of the parameters and design requirements. The circuit board 走 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ There are only a few nodes on the board,
貝-般先對這些走線進行手H 電路作大規模自動## 再用权體對整個 自動佈線。如今的電路板上常常合古μ贫加 甚至更多的節點，而1中 曰有上4個 外’不僅關鍵性_:=上:^ 在增加。由於面臨著上市時編力，此時=因素也 守如用手工佈線 18868 5 1290675 已很難做到’而必須借助專#軟體進行輔助設計。 佈線2 AUegrQ即是當前#界廣泛使用之一種輔助線路 士盖人紅’ AUegro提供了良好且交互的工作介面和強大 ::的功能，為當前高速、高密度、多層的複雜電路板設 提供了較好解決方案’此外，其擁有強大的影響因 ”设定，用戶只須依據要求設定好佈線規則，在佈線中消 除所有設計規則檢查（Design Rules Gheek;DRG)錯誤就 可以達到佈線的設計要求，從而節省繁;貞的人工檢查時 間’俾提高了工作效率。 <二惟，僅管如此，當前例如AUegr〇之佈線軟體在完成 •設計規則檢查後仍有許多不足之處，首先，其設計規則檢 -查後所有的設計規則檢查錯誤均採用同一種顯示方式進行 顯示，使工程師難以區分具體的設計規則檢查錯誤屬於何 種類型，亦難以分門別類地對、設計規則檢查錯誤進行修 改，此外，佈線軟體之設計規則檢查普遍過於死板，對於 籲一部分貫際上並不是錯誤的佈線，它仍然報告設計規則檢 查錯疾’ 一塊電路板往往會出現幾十上百個這樣的錯誤， 工程師必須將其從真正需要處理的錯誤中加以排除，不但 浪費了大量時間，還可能由於排除的過程出錯而給電路板 設計造成不必要的麻煩。 因此’如何提供一種設計錯誤的檢查系統及方法，以 避免上述習知技術之種種缺失，即是當前業界亟待解決之 問題。 【發明内容】 6 18868 1290675 • 鐾於上述習知技術之問題，本發明之主要目的在於提 供-種設計錯誤的檢查系統及方法，其可對不同之設吁規 則檢查後所會面臨的錯誤予以分類，以提升設計規則檢查 • (DesignRulesCheck;卯c)在錯誤處理上之效率。一 I發明之另-目的在於提供一種設計錯誤的檢查系 統以及方法，以縮短DRC對於錯誤處理之時間，且 大量人力資源。 A達上述及其他目的，本發明即提供—種設計錯誤的 檢查系統以及方法，其得應用於電路板佈線系統中。該設 計錯誤的檢查系統係包括設定模組，係用以供使用者設定 -设計錯誤的·規則；層選擇模組，用以於該電路板上選 •擇需要進行設計規則檢查之佈線層；分類模組，用以對該 層選擇模組選擇之佈線層上進行設計規則檢查（Design 肋1 es Check ;道）後所會面臨的錯誤予以分類；判斷模 組，係用以依據使用者透過該設定模組設定的判斷規則以 及該分類模組所分類的錯誤類別判斷該電路板佈線於設計 規則檢查後所判定出的錯誤是否為可以忽略之錯誤，並據 以f生判斷結果；以及提示模組，係用以於該判斷模組之 判斷結果為不可忽略之錯誤時產生提示訊號，以告知使用 者5玄錯誤係為不可忽略之錯誤。 ，本發明之設計錯誤的檢查系統中，該設定模組設定 之判斷規則係至少包括貫穿通孔間隔（Shape t〇如^ racing)錯誤判斷規則以及線間距（Hne t〇 u狀 spacing)錯誤判斷規則。 7 18868 /〇n 1290675 一另:卜：該提*漁係對何忽略之錯誤該係透過顯示 早兀以r^度的方式提示該設計規則檢查發生錯誤。再 =:模組亦可以語音提示方式或文字訊息提示方式 • 透過本料之設計錯料檢查纟統執狀設計錯誤 -的檢查方法係包括以下步驟：⑴透過該設計錯誤的檢查 系統設定計設錯誤的判斷規則；⑵令該設計錯誤的檢查 籲糸統選擇進行設計規則檢查之佈線層；⑺令該設計料 的檢查系統對所選擇之佈線層上進行設計規則檢查後所會 面l的錯*予以分類；⑷令該設計錯誤的檢查系統藉由 .所設定的判斷規則以及經分類後的錯誤類別判斷該電路板 .佈線於設計規則檢查後所判定出的錯誤是否為可以忽略之 錯誤’若是則結束流程，否則進至步驟⑴；以及 令該設計錯誤的檢查系統產生一提示訊號，以告知使用者 該設計規騎查後㈣定㈣的錯誤㈣何忽略之夢 籲誤。 曰 另外’本發明之設計錯誤的檢查方法復包括將該分類 後的錯誤類別以及對判斷為不可忽略之錯f吳予以導出。 相較於習知技術，本發明之設計錯誤的檢查系统及方 法，係對多數設計規賤查後所會㈣的錯誤進行分類， 以便透過本發明之設計錯誤的檢查系統依據縣設定的判 斷規則以及經分類的錯誤類別判斷該電路板佈線於”規 則檢查後所判定出的錯誤是否為可以忽略之錯誤，、錄該 設計規則檢查後所判定出的錯誤為不可忽略之錯誤時產生 18868 8 1290675 提示訊號，以提示使用者該錯誤係為不可忽略之錯誤，、 便使用者進行修改，俾可提升設計規則檢查在錯^理^ 之效率’且可節約時間及人力。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 式’熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 私的具體實例加以施行或應用，本說明書中的各項細節亦可 基於不同觀點與應、帛，在不惊離本發明之精神下進行各種 修飾與變更。 -請參閲第1圖，其中顯示本發明之設計錯誤的檢查系 -統之方塊圖。如圖所示，本發明之設計錯誤的檢查系統1， 係應用於一電路板之佈線系統中，以於該電路板各佈線層 進行α又汁規則檢查（Design Ruies check ; DRC )後判定為 錯祆時’可即時提示除錯人員該錯誤是否為可忽略或不可 >忽略、’以提升除錯效率。本實施例所述之電路板之佈線系 統係為例如A1 legro佈線軟體。 本發明之設計錯誤的檢查系統1係包括：設定模組 11、層選擇模組12、分類模組13、判斷模組14以及提示 模組15 ’其中’該系統1復可包括導出模組16以及儲存 模组17 °以下即對設定模組11、層選擇模組12、分類模 組13、判斷模組14、提示模組15、導出模組16以及儲存 模組17進行詳細説明。 该設定模組11係用以供使用者設定設計錯誤的判斷 9 18868 1290675 規則。於本發明中，該判斷規則係至少包括貫穿通孔間隔 Shape to thru via spacing)錯誤判斷規則以及線間距 (line to line spacing)錯誤判斷規則。 -般情形下，貫穿通孔間隔錯誤係發生於電路板之電 源層，其為佈線時將貫穿通孔與走線重合佈設情況下而可 能引起錯誤，在電路板佈線系統進行設計規則檢查以提示 貫穿通孔間隔錯誤中，若貫穿通孔與走線的名稱（net >霞）相同，則依此設計成之電路板將會有短路之情形發 生’因此該由貫穿通孔與走線重合佈設引起的錯誤不可被 忽略，反之，若貫穿通孔之名稱與走線名稱不同，則依此 佈線後設計成之電路板並不會出現不良狀況，此時該錯誤 即是可以忽略的錯誤，同時該錯誤亦不必再標記為設計規 則檢查錯誤，即該錯誤可以被消除。於本實施例中，設定 模組11所設定之貫穿通孔間隔錯誤判斷即為貫穿通孔盘 其重合之走線二者名稱相同時該貫穿通孔間隔錯誤視為不 可忽略之錯誤，否則視為可以忽略之錯誤。 而線間距錯誤係發生於電路板之頂層（t〇p !町打） 或者底層（buU〇m layer)，其係由兩條相鄰走線之間的距 離小於使用者預設的間距引起之錯誤，當前之電路板佈線 系統對於電路板走線小於預設距離的狀況，均會提示設計 規則檢查後所判定出的錯誤，然當上述兩條走線均接有接 腳（pin)並且走線長度均小於使用者之預設值時，該錯誤 並不會引起電路板設計的缺失’因此該錯誤被視爲可以曰忽 略之錯誤’其僅在不符合上述條件時才是不可忽略的錯誤 18868 1290675 而必須進行修改。於本實施例中，設定模組u所設定之線 間距錯誤判斷規則係為若兩條走線兩端點坐標與包含接腳 的中心坐標重合’且该兩條走線的長度均小於一預設值則 該線間距錯誤則視為不可忽略之錯誤，否則視為可以忽略 之錯誤’其中’該預設值係可根據使用者根據具體需要之 不同而預先設定。 層選擇模組12用以選擇佈線層，以進行設計規則檢 •查，目前之電路板-般均係為例如五層板、七層板或者更 多層的結構’層選擇模組U係可以從多層中選擇任意一層 或者任意複數層的組合供後續進行設計規則檢查之處理。 . 分類模、组13係用以對層選擇模組11選擇之佈線層依 ，據設計規則檢查後所會面臨的錯誤予以分類，於本實施例 中，該DRC後所會面臨的錯誤係具有複數個類別，例如貫 穿通孔間隔（Shape t0 thru via spacing)錯誤以及線間距 to line spacing)錯誤等，於本發明中，僅以對 '貫穿通孔間隔錯誤以及線間距錯誤進行DRC處理為例進行 説明，然，並非單以此限制本發明。 判斷模組14係用以藉由設定模組11設定之判斷規則 以及t類的錯誤類別判斷該電路板佈線於設計規則檢查後 戶:判定出的錯誤是否為可以忽略之錯誤，並據以產生判斷 結果’以供提*模組15對該處理結果進行後續處理。如上 所述Y若使用者所選之DRC後所會面臨的錯誤屬於貫穿通 孔2錯誤之類別，判斷模組14根據設定模組1丨所設定 的貫穿通孔間隔錯誤判斷規則’比對貫穿通孔及與其重疊 18868 11 1290675 之走線的名稱是否相同，甚士 J右相同則判斷該錯誤為不可夂略 之設計規則檢查錯誤，若不知 ^ 不相同則將該錯誤視為可以忽略 之錯誤，同時可將該可勿畋+ μ μ， ^心、略之錯誤消除而避免花費大量人 力及時間對其進行修改。甚你 、 逆仃i改右使用者所選之DRC後所會面臨 的錯誤屬於線間距錯誤之類別，判斷模組14根據設定模组 11所^的線間距錯誤判斷規則比對兩條走線兩端點的 坐標是否與接腳的中心+ 古击人 τ丄糕有重合，若兩條走線之端點坐Be the first to carry out the manual H circuit for these traces for large-scale automatic ## reuse right to the entire automatic routing. Today's boards are often associated with even more nodes, and there are more than 4 nodes in 1 'not only critical _:= upper: ^ is increasing. Due to the time of the listing, the = factor is also as good as manual wiring 18868 5 1290675 has been difficult to do 'and must rely on the special # software for auxiliary design. Wiring 2 AUegrQ is a kind of auxiliary line that is widely used in the current world. AUegro provides a good and interactive working interface and powerful:: for the current high-speed, high-density, multi-layer complex circuit board A better solution 'in addition, it has a strong impact factor' setting, users only need to set the wiring rules according to the requirements, eliminate all design rule checks (DRG) errors in the wiring to meet the wiring design requirements. This saves the complexity; the manual inspection time '俾 improves the work efficiency. · Second, just like this, the current wiring software such as AUegr〇 still has many shortcomings after the completion of the design rule check. First, its Design rule check-checking All design rule check errors are displayed in the same display mode, making it difficult for engineers to distinguish the specific design rules. What type of error is checked, and it is difficult to modify the design rule check errors in different categories. The design rules of the wiring software are generally too rigid, for the part of the appeal It's not the wrong wiring, it still reports the design rules to check the wrong ones. A board often has dozens of hundreds of such errors, engineers must exclude them from the errors that really need to be processed, not only waste a lot of time, but also It may cause unnecessary trouble to the board design due to the process of the exclusion process. Therefore, 'how to provide a design error checking system and method to avoid the above-mentioned various shortcomings of the prior art is an urgent problem to be solved in the industry. SUMMARY OF THE INVENTION 6 18868 1290675 • In view of the above-mentioned problems of the prior art, the main object of the present invention is to provide an inspection system and method for designing errors, which can classify errors that are faced after different rules are set. In order to improve the design rules check (DesignRulesCheck; 卯 c) in the efficiency of error handling. Another I invention - the purpose is to provide a design error checking system and method to shorten the DRC time for error handling, and a lot of manpower Resources. For the above and other purposes, the present invention provides The error checking system and method are applied to the circuit board wiring system. The design error checking system includes a setting module for the user to set - design error rules; a layer selection module, The wiring layer for selecting a design rule check is selected on the circuit board; the classification module is configured to perform a design rule check on the wiring layer selected by the layer selection module (Design rib 1 es Check ; track) The errors that are faced are classified; the judging module is configured to determine that the circuit board wiring is determined after the design rule check according to the judgment rule set by the user through the setting module and the error category classified by the classification module. Whether the error is a negligible error, and according to the result of the judgment; and the prompting module is used to generate a prompt signal when the judgment result of the judgment module is a non-negligible error, to inform the user of the 5 mystery error. It is a non-negligible error. In the design error detection system of the present invention, the determination rule set by the setting module includes at least a through-hole spacing (Shape t〇such as ^ racing) error determination rule and a line spacing (Hne t〇u-shaped spacing) error determination. rule. 7 18868 /〇n 1290675 One another: Bu: The error of the fisherman's neglect. The system prompts the design rule to check for errors by displaying the early warning. Then =: The module can also be voice prompt or text message reminder • Check the design error of the design through the design of the material. The inspection method includes the following steps: (1) setting the design through the design error check system Wrong judgment rule; (2) making the design error check system select the wiring layer for design rule check; (7) making the inspection system of the design material face the error of the design rule check on the selected wiring layer* (4) The inspection system that makes the design error judges the board by the judgment rule set and the classified error category. Whether the error determined by the wiring after the design rule check is a negligible error 'if Then, the process ends, otherwise the process proceeds to step (1); and the design system that causes the design error generates a prompt signal to inform the user of the error of the design rule (4) (4) and the dream of the ignore. Further, the inspection method of the design error of the present invention includes the classification of the error after the classification and the error f which is judged to be non-negligible. Compared with the prior art, the design error checking system and method of the present invention classify the errors of (4) after the majority of the design rules, so as to be judged according to the county setting rules through the design error checking system of the present invention. And the classified error category determines whether the error determined by the circuit board after the rule check is a negligible error, and the error determined after the design rule check is a non-negligible error occurs 18868 8 1290675 The prompt signal is used to prompt the user that the error is a non-negligible error, and the user can modify it, so that the design rule can be improved in checking the efficiency of the error ^ and save time and labor. [Embodiment] The embodiments of the present invention are described by way of specific specific examples. Those skilled in the art can readily appreciate the advantages and advantages of the present invention as disclosed in the present disclosure. The present invention may also be practiced by other specific embodiments. Or application, the details in this manual can also be based on different opinions and should be Various modifications and changes are made in the spirit of the invention. - Referring to Figure 1, there is shown a block diagram of the design of the design error of the present invention. As shown, the design of the design of the wrong system 1 of the present invention, It is applied to the wiring system of a circuit board, so that when the circuit layer of the circuit board is subjected to the design rule check (DRC), it is determined that the error is correct. Ignoring or not <ignoring, 'to improve the efficiency of debugging. The wiring system of the circuit board described in this embodiment is, for example, A1 legro wiring software. The design of the design of the wrong system 1 includes: setting module 11, The layer selection module 12, the classification module 13, the determination module 14, and the prompt module 15 'where the system 1 includes the export module 16 and the storage module 17 ° or less, that is, the setting module 11 and the layer selection mode The group 12, the classification module 13, the determination module 14, the prompt module 15, the export module 16, and the storage module 17 are described in detail. The setting module 11 is used for the user to set the design error judgment 9 18868 1290675In the present invention, the judging rule includes at least a through-thru via spacing error determination rule and a line to line spacing error judging rule. Occurs in the power supply layer of the circuit board, which may cause errors when the through-holes are overlapped with the traces during wiring. The design rule check is performed in the circuit board wiring system to indicate that the through-hole spacing error occurs. The same as the name of the trace (net > Xia), the circuit board designed according to this will be short-circuited. Therefore, the error caused by the overlap of the through-hole and the trace can not be ignored. The name of the through-hole is different from the name of the trace. Therefore, the circuit board designed after wiring is not in a bad condition. At this time, the error is a negligible error, and the error does not need to be marked as a design rule check. The error is that the error can be eliminated. In this embodiment, the erroneous determination of the through-hole spacing set by the setting module 11 is that the through-hole spacing error is regarded as a non-negligible error when the names of the overlapping lines of the through-hole tray are the same. For errors that can be ignored. The line spacing error occurs on the top layer of the board (t〇p!machi) or the bottom layer (buU〇m layer), which is caused by the distance between two adjacent traces being less than the preset spacing of the user. Wrong, the current circuit board wiring system will prompt the error determined by the design rule check when the board trace is less than the preset distance. However, when the two traces are connected with pins and go When the line length is less than the user's default value, the error does not cause a missing board design 'so the error is considered an error that can be ignored'. It is a non-negligible error only if the above conditions are not met. 18868 1290675 and must be modified. In this embodiment, the line spacing error determination rule set by the setting module u is such that if the coordinates of the two ends of the two lines coincide with the center coordinates of the included pins, and the lengths of the two lines are less than one pre- If the value is set, the line spacing error is regarded as a non-negligible error, otherwise it is regarded as a negligible error 'where' the preset value can be preset according to the user's specific needs. The layer selection module 12 is used to select a wiring layer for design rule checking. The current circuit board is generally a structure such as a five-layer board, a seven-layer board or more layers. Select any layer or a combination of any multiple layers from multiple layers for subsequent design rule checking. The classification module and the group 13 are used to classify the wiring layers selected by the layer selection module 11, and are classified according to errors that are faced after the design rule is checked. In this embodiment, the error that the DRC will face is In a plurality of categories, for example, a through-hole spacing error and a line spacing error, etc., in the present invention, only the DRC processing for the through-hole spacing error and the line spacing error is taken as an example. It is to be noted that the present invention is not limited thereto. The determining module 14 is configured to determine, by the setting rule set by the setting module 11 and the error category of the t type, that the circuit board is wired after the design rule check: whether the determined error is a negligible error, and accordingly The judgment result 'is subsequently processed by the module 15 for the processing result. As described above, if the error faced by the DRC selected by the user belongs to the type of the through-hole 2 error, the determination module 14 determines the rule of the through-hole spacing error set according to the setting module 1丨. The name of the through hole and the trace overlapping with 18868 11 1290675 is the same. If the name is the same, the error is judged to be an unrecognizable design rule check error. If you do not know that ^ is not the same, the error is regarded as a negligible error. At the same time, it is possible to eliminate the error and eliminate the error and avoid a lot of manpower and time to modify it. The error that you will face after changing the DRC selected by the right user belongs to the category of line spacing error. The judgment module 14 compares the two traces according to the line spacing error judgment rule of the setting module 11. Whether the coordinates of the two endpoints coincide with the center of the pin + the ancient hitter τ丄 cake, if the ends of the two traces sit
心句/、接腳的中心坐標重合則比對兩個走線之長度是否均 小=預設值，若是即認爲該設計規則檢查後所判定出的 錯决係為可以忽略之錯誤’若未小於該預S值則認爲其為 不可忽略之錯誤。 - 和1示模、卫15係用以對該判斷模組14之判斷結果進行 處理，若該設計規則檢查的判斷結果為不可忽略之錯誤， 2產生一提示訊號，以告知使用者該設計規則檢查後所判 定出的錯誤係為不可忽略之錯誤，以便使用者對該設計規 鲁則檢查錯誤進行修改以消除該設計規則檢查錯誤。於 施例中^提示模組15將不可忽略之錯誤並;透過例如發光 才°體#顯示單元以高亮度的方式提示除錯人員該設計發 生錯誤，此外，提示模組15亦可以語音提示方式或文字提 不方式作提示動作，惟此些提示方法係為習知，故在此不 再為文追述。 “導出模組16係用以將分類模組13之分類結果以及該 ^斷核組14判斷為不可忽略之設計錯誤導出以形成一外 ^文件而儲存至儲存模組17中，俾方便查閱。一般而言， 12 18868If the center coordinates of the heart/and pins are coincident, then the length of the two traces is smaller than the preset value. If it is, the error determined after the design rule check is considered to be an error that can be ignored. If it is not less than the pre-S value, it is considered to be a non-negligible error. - and 1 model, Wei 15 is used to process the judgment result of the judgment module 14, if the judgment result of the design rule check is a non-negligible error, 2 generate a prompt signal to inform the user of the design rule The error determined after the check is a non-negligible error, so that the user can modify the design rule to check the error to eliminate the design rule check error. In the embodiment, the prompting module 15 will not ignore the error; and the display unit can prompt the debugger to display an error in a high-brightness manner through, for example, the illumination module. In addition, the prompt module 15 can also be voice-activated. Or the text does not provide a prompt action, but these prompt methods are known, so it is no longer traced here. The "export module 16" is used to export the classification result of the classification module 13 and the design error that the core group 14 determines to be non-negligible to form an external file and store it in the storage module 17, for convenient reference. In general, 12 18868
1290675 该儲存模組17所儲存的資料係可包括由該分類模組13針 對该層選擇模組12所選擇之佈線層以及該判斷模組14所 判斷出的設計錯誤等資料。再者，其復可儲存由該設定模 =11所設定的判斷規則。透過本發明之設計錯誤的檢查系 、’先1執仃本發明之設計錯誤的檢查方法之流程如第2圖所 不。如圖所示，本發明之方法係包括以下實施步驟：首先 進行步驟S卜使用者透過設定模組n設定判斷規則，其 中，該判斷規則係至少包括貫穿通孔間隔（Shape t〇 Vla spacing)錯誤判斷規則以及線間距（line 】he 錯誤判斷規則’於本實施例中’貫穿通孔間隔錯 斷規則係為若貫穿通孔間隔錯誤中貫穿通孔之名稱 杳、^合的走線名稱相同則定義為不可忽略之設計規則檢 錯則為可以忽略之設計規則檢查錯誤，而線間距 重人，㈣係為若兩條走線之端點坐標與接腳中心坐標 略：二兩條走線的長度均小於-預設值則定義為不可 :’否則為可以忽略之錯誤’接著進行步驟s2。 擇進行過層選擇模組12於上述電路板中選 選擇之佈線層係可為電路板之任上=::， 組合’接著進行步驟S3。 層成者任思稷數層的 擇之==2 13對層選擇模組12所選 類，接著于 則檢查後所會面臨的錯誤予以分 文耆進至步驟S4。 於步驟S4中，令判斷模組14藉由步驟81中所設定 18868 13 1290675 的判斷規則以及所分類的錯誤類別判斷該電路板佈線於設 計規則檢查後所判定出的錯誤是否為可以忽略之錯誤，若 是’則結束步驟流程，若否，則進至步驟S5。承前所述， .對於貫穿通孔間隔錯誤類別之設計規則檢查所會面臨的錯 .誤，若·I组14比對貫穿通孔之名稱與與其重合之走線 名稱相同，則該設計規則檢查後所判定出的錯誤視為不可 忽略之錯誤，否則為可以忽略之錯誤；對於線間距錯誤類 癱別之設計規則檢查所會面臨的錯誤，若判斷模組14比對兩 條走線端點坐標肖與接腳的中心坐標重合，i兩條走線的 長度均小於-預設值，則該設計規則檢查後所判定出的錯 .誤為不可忽略之錯誤，否則為可以忽略之錯誤。 ，…於步驟S5 ’令提示模組15產生提示訊號以告知使用 者該設計規則檢查後所判定出的錯誤為不可忽略之錯誤。 本發明之設計錯誤的檢查方法復包括令導出模組16 將分類模組13之分類結果及判斷模組14所判斷為不可灰 ♦略之錯誤導出㈣成—外部文件並齡至儲存模組Η中。 綜上所述，本發明之設計錯誤的檢查系統及方法，係 對多數設計規則檢查後所會面臨的錯誤予以分類，以便透 過本發明之設計錯誤的檢查系統依據預先設定的判斷規則 以及分類的錯誤類別判斷該電路板佈線於設計規則檢查後 所判定出的錯誤是否為可以忽略之錯誤，且於該設計規則 檢查錯誤為不可忽略之錯誤時產生一提示訊號以提示使用 者該設計規則檢查所判定的錯誤係為不可忽略之錯誤，以 便使用者進行修改，俾可提升錯誤檢查之效率，且可節約 18868 14 1290675 時間及人力。 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及料下，對上述實施例進行修飾鱼改 ，。因此’本發明之權利保護範圍，應如後述之申請 範圍所列。 【圖式簡單說明】 #第1圖係為一方塊圖，其係用以顯示本發明之設 誤的檢查系統之基本架構方塊示意圖；以及 曰 第2圖係為一流程圖，其係用以顯示本發明之設 誤的檢查方法的運作流程示意圖。 【主要元件符號說明】 1 設計錯誤的檢查系統 11 設定模組 12 層選擇模組 13 分類模組 14 判斷模組 15 提示模組 16 導出板組 17 儲存模組 S1 〜S5 步驟 18868 151290675 The data stored in the storage module 17 may include information such as a wiring layer selected by the classification module 13 for the layer selection module 12 and a design error determined by the determination module 14. Furthermore, it can store the judgment rule set by the setting mode =11. The process of checking the design error by the present invention, and the process of checking the design error of the present invention first is as shown in Fig. 2. As shown in the figure, the method of the present invention includes the following steps: first, step S is performed by the user through the setting module n, wherein the determining rule includes at least a through hole spacing (Shape t〇Vla spacing). The error judgment rule and the line spacing (line) and the error judgment rule 'in the present embodiment' are the same as the through-hole spacing error rule in the through-hole spacing error. The design rule that is defined as non-negligible is the design rule check error that can be ignored, and the line spacing is heavy. (4) If the coordinates of the end points of the two traces and the center coordinates of the pins are slightly: two or two traces The length is less than - the preset value is defined as not: 'otherwise it is an error that can be ignored'. Then step s2 is performed. The layer selection module 12 selects the wiring layer selected from the above circuit board to be a circuit board. Any ==:, combination 'following step S3. The layer is selected by the number of layers == 2 13 pairs of layer selection module 12 selected classes, then the errors that will be faced after the inspection are divided Proceeding to step S4. In step S4, the determination module 14 determines the error determined by the board layout after the design rule check by the judgment rule of 18868 13 1290675 set in step 81 and the classified error category. Whether it is an error that can be ignored, if it is 'then the step flow is finished, if not, then go to step S5. As stated in the previous paragraph, the error of the design rule check for the through-hole spacing error category, if ·I The name of the group 14 through-through hole is the same as the name of the line that coincides with it. The error determined by the design rule check is regarded as a non-negligible error, otherwise it is a negligible error; The design rule checks for errors that are encountered. If the judgment module 14 compares the coordinates of the two end points and the center coordinates of the pins, and the lengths of the two traces are less than - the preset value, the design The error determined by the rule check is a non-negligible error, otherwise it is an error that can be ignored. ,... In step S5', the prompting module 15 generates a prompt signal to inform the user of the setting. The error determined by the rule check is a non-negligible error. The design error check method of the present invention includes the export module 16 determining that the classification result of the classification module 13 and the determination module 14 are not grayed out. The error is derived (4) into the external file and is aged to the storage module. In summary, the design error checking system and method of the present invention classify the errors that are faced after most design rules are checked, so as to The design error detection system of the invention determines whether the error determined by the board layout after the design rule check is a negligible error according to a preset judgment rule and the classified error category, and the error is not negligible in the design rule check error. When the error occurs, a prompt signal is generated to prompt the user that the error determined by the design rule check is a non-negligible error, so that the user can modify the file, thereby improving the efficiency of the error check, and saving 18868 14 1290675 time and labor. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the application described below. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a basic architectural block diagram of an inspection system of the present invention; and FIG. 2 is a flowchart for use in a flowchart. A schematic diagram showing the operational flow of the inspection method of the error of the present invention. [Main component symbol description] 1 Design error checking system 11 Setting module 12 layer selection module 13 Classification module 14 Judging module 15 Prompting module 16 Exporting board group 17 Storage module S1 ~ S5 Step 18868 15