TWI289306B - DRAM with half and full density operation - Google Patents

DRAM with half and full density operation Download PDF

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Publication number
TWI289306B
TWI289306B TW094120927A TW94120927A TWI289306B TW I289306 B TWI289306 B TW I289306B TW 094120927 A TW094120927 A TW 094120927A TW 94120927 A TW94120927 A TW 94120927A TW I289306 B TWI289306 B TW I289306B
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Taiwan
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memory
data
density
column
stored
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TW094120927A
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Chinese (zh)
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TW200606942A (en
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Jeffery W Janzen
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Micron Technology Inc
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/06Address interface arrangements, e.g. address buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4093Input/output [I/O] data interface arrangements, e.g. data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)

Abstract

Methods and apparatus for operating a memory in a half density or a full density mode, and switching between the modes when required. A memory device defaults to half density operation upon startup for lower power consumption, and switches to full density operation when the lower addresses are full. When the upper addresses are once again empty, the devices switches back to half density operation.

Description

1289306 九、發明說明: 【發明所屬之技術領域】 本發明係概括關於記憶體元件,且本發明係特別關於 動恶隨機存取記憶體(DRAM,dynamic rand_ access memory)及其操作。 【先前技術】 動態隨機存取記憶體(DRAM)係可配置為半密度或全 在度於一全雄、度記憶體中,一記憶體陣列之各個内部列 係允許-記憶體單元㈣)之存取,且各個單元係可運用以 供-獨特位元的資料之儲存。於一半密度記憶體中,各個 内部列係與另一個互補列為成對,使得當資料為儲存於一 個記憶體單元時,互補的資料係健存於互補列之相比的單 元。於一半密度記憶體中,二個字组線係同時致n 為於-數字線而一者為於數字線*(其互補者)。此係 相(mverted)的資料於各個單元,其接 弋之一夂老W 1 + Μ 運用作為於差動模 用方;一“度§己憶體中。一記憶體之全密度操 」 數目的單元之完全程度的運用,且因此為可儲存相^ 可相比尺寸的半密度記憶體之更多的資… 存其本身的個別資料,且 们早几係儲 加更新時間。 為個別更新而增 於目前的技術中’方法係存 生諸如記憶體之零件。藉著 乂、々更新時間.而產 曰·^子乂我的更新時 — 於半岔度兄憶體之較低密产於 、 且藉著诸如 乍,—較低的操作電流係被 1289306 使:,且針對於可攜式裝置之電池壽命係已為延長。可押 式裝置係經常為不具有大量的記憶體之“,尤其是於:1289306 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to memory components, and the present invention relates in particular to dynamic DRAM (dynamic rand_access memory) and its operation. [Prior Art] Dynamic Random Access Memory (DRAM) can be configured to be half-density or full-degree in a full-length memory, and each internal column of a memory array is allowed-memory unit (4). Access, and each unit can be used to store the data of the unique bits. In half-density memory, each internal column is paired with another complementary column so that when the data is stored in a memory cell, the complementary data is stored in the complementary column. In half-density memory, the two-word line system simultaneously causes n to be a - digit line and one to be a digit line * (the complement of it). The mverted data is in each unit, and one of the interfaces is used by the old W 1 + Μ as the differential model; a “degree of § memory. a full density operation of a memory” The full extent of the use of the unit, and therefore more storage of the comparable size of the semi-density memory ... save its own individual data, and the early storage and update time. Adding to the current technology for individual updates, the method relies on parts such as memory. By 乂, 々 update time. And 曰 ^ ^ ^ 乂 my update - in the half-degree 兄 忆 忆 之 之 之 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低 较低: and the battery life for portable devices has been extended. The detachable device is often "without a large amount of memory", especially in:

多數的正常操作模+至R m間。然而,某些農置係可能發生為 運用較夕的記憶體’且因此需要全密度記憶體,雖然” 為其並非為一直需要。杏 Ά 且而要 田全岔度記憶體為運用於1除了於 某些情況之外而不需要入玄危 八牙、r於 不而要王雄、度記憶體之構件與裝置,Most of the normal operation mode + to R m. However, some agricultural systems may occur to use the memory of the eve of the day's and therefore require full-density memory, although "it is not always necessary. Apricot 且 而 要 岔 岔 岔 岔 记忆 记忆 运 运 运 运 运 运 运In some cases, it is not necessary to enter the hexagram, and the components and devices of Wang Xiong and the memory are not required.

消耗係高,且針對於右PP t對方、有限的電池電力,該種全時 度操作係較為不合音,而道# 4 "The consumption is high, and for the right PP t counterpart, limited battery power, the full-time operating system is relatively unvoiced, and the road # 4 "

" 而v致較短的電池壽命與類似者。 方面自可攜式應用至類似於可攜式電腦與類似者之 更為強力的可攜式應用,某些應用係需要較大量的記憶 體,但是其仍然具有電力限制。 “ 記憶體係典型為配置為半密度或全密度,且為不可改 變。針對於上述的理由,且針對於熟悉此技藝人士於詳讀 :瞭解本說明書而將成為顯明之下述的其他理由,於此: 蟄係存在需要一種記憶體元件以及操作記憶體之方法,其 為結合半密度與全密度操作之裨益。 【發明内容】 上述的問題與其他的問題係由本發明所解決,且將為 藉由研讀以下的說明書而瞭解。 於一個實施例中,一種於一記憶體操作的一全密度與 半密度模式之間轉換之方、本将句括:也仏a 付佚I万居係匕枯·起始記憶體操作於 半密度模式;以及,監視於半密度操作所使用之位址。當 半密度為不再能夠儲存其待寫入至記憶體的所有資料時, 該記憶體係切換至全密度模式。 ⑧ 1289306 包括於Γ個實施例中,一種操作一記憶體元件之方法係 匕括.起始記憶體操作於一半宓产〃知 憶體單元之使用率;及〜:二、:陣列的記 切換自該半穷产模h入吊的§己憶體操作為需要時而 茨牛名度杈式至一全密度模式。 於又一個實施仓,丨Φ 憶體單元,豆可為由:~種記憶體係包括:-陣列之記 ;:部資料且傳送該資料至該陣列;及,-記憶體控 :4體控編系操作該記憶體於一全〜 ::”之操作的-者’且當半密度操作為不具有足约:: :::其待寫入至記憶雜的所有資料時自該半密;: 知作切換至全密度模式之操作。 、式之 及於再一個實施例中種處理系統係包括:-處理哭. 則,其係•接至該處理器,以儲存由處理哭所 才疋供的貧料且提供資料至兮 的所 陆, +至4處理盗。該記憶體係包括:— :之:憶體單元,其可為由位址電路所定址; 电路’其㈣以接收外部資料且傳送該資料至料列 -記憶體控制器。該記憶體控制器係操广 密度或-半密度模式之操作的-者,且當半密;:::全 具有足夠的密度以容納其待寫入至該記憶體的所有資二 向目该+密度模式之操作切換至,全密度模式之操#。 T 其他的實施例係被描述及主張。 【實施方式】 於本發明之以下詳細說日月,構成本說明的 ” 隨圖式係參照,其中,本發明為可實行於 ::之伴 〜扣疋貫施例 1289306 係作為說明而顯示。於圖式中,類似的參考符號係描述於 數個圖式之實質類似的構件。此等實施例係描述足㈣ 細,以致使熟悉此技藝人士為能夠實行本發明。其他的實 施例係可利用,且結構、邏輯、與電 兒虱的k化係可作成而 未偏離本發明之範®壽。 因此,以下的詳細說明係非為限制意味,且本發明之 範缚係僅為由隨附的申請專利範圍、以及對於該等申請專 利範圍所為賦予至其的均等者之完整範疇而界定。 第1圖係顯示本發明之實施例為可實行於其的一種全 密度記憶體100之結構。印愔鲈〗nn〆^ 苒思脰I00係包含一陣列之記憶 體单70 102’各者係包含一電晶體與—電容器,該等記情 體單元為由個別的内部们04與内部行1G6所定址。如圖 所示的此等列 1 〇4盥杆! # -Γ 士竹 予幻U ,“丁106係可存取八個單元,各者係保 存個別段(piece)的資料。與也丨a 士 . 、 牛例而吕,名人致動單元〇,〇,列〇 與行〇係致動。 弟2圖係顯不本發明每 4 S月之貝施例為可實行於其的一種半 岔度纟己憶體2 0 〇之結構。兮錄士备 再°亥種結構係專效於記憶體丨〇〇之 結構,但是定址方岽在τ η , 木仅不同。記憶體2〇〇係包含相同陣列 之記憶體單元2〇2 ’各者係包含一電晶體與一電容器,該 W憶體早凡為由個別的内部列204與内部行所定 方、半在度"己憶冑200,各列係與一互補列而為 成對’即:圖示為存在二個歹"與二個歹"。舉例而言, 欲致動單元〇,〇,琴-加χϊ 少 個列Q之各者、以及行0係致動。 此命者存反相貧料方\留- 、凡〇,〇與〇,0*。並無奇數列被使用。 ⑧ 8 1289306 灰本發明之實施例中,如同上述的記憶體1 與2〇〇 之相同結構的一種記憶體係被使用,但是該種記憶體之記 體操作係俾使其可操作為一半密度記憶體或一全密度記 ^虹視所期!的運用而定。該操作係運用記憶體之控制 器而達成,以操作該記憶體於下述的方式。於一個實施例 300中,顯示於帛3圖之流程圖,一記憶體之開啟電源(p〇wer ΡΚ·τ'毛生於方塊302。於此實施例中,記憶體之操作係於 方塊304 m設定至半密度(或2Τ)模式以作為—預設者。應 奢。午的疋.丨同於半密度之一預設者(例如:全密度操作) 亦可為設定而未偏離本發明之範疇。於方塊3%中,一位 址係提供至記憶體控制器或類似者,且於決策方塊308中, “決定該位置是否為一奇數内部列。若該位址係非為一 I數内部列’即:其為—偶數内部列,則方法流程係繼續 方、方塊310,於其中,任何偶數(半密度)内部列係可存取。 一六位址係以此方式提供,填充或運用偶數内部列而直到 一奇數内部列為存取於決策方塊3〇8為止。於該時點,於 方塊312中,操作係切換至全密度(或1Τ)模式,且任何的 内部列係可存取於方塊314。再者,白 係隨荽拗^ #者η我〜新柃序⑴而叫) 「、曰加的功率而調整,使得更新操作係發生於適當的 —a.). 於系統設射至最小有效0⑽剛此,内部列以助 :某點,於全密度模式之操作係將不再為需要。如此 “方法3〇〇係繼續為於決策方塊3 16而檢查任何奇數 ⑧ 9 1289306 :部列是㈣為。若奇數㈣㈣仍為㈣,操作係 繼績於全密度模式,且方法治 ’、 方法抓私係繼續為於方塊317而提 …個位址。當不再有任何的奇數内 更新操作係在方法流程為繼續於方塊3〇4之前而實行。" And v causes shorter battery life and similar. From portable applications to more powerful portable applications like portable computers and the like, some applications require a larger amount of memory, but they still have power limitations. "Memory systems are typically configured to be half-density or full-density and are immutable. For the above reasons, and for those skilled in the art, read the following: Other reasons for this description will become apparent. There is a need for a memory component and a method of operating a memory, which is a benefit of combining half density and full density operation. SUMMARY OF THE INVENTION The above problems and other problems are solved by the present invention and will be borrowed. It is understood by studying the following description. In one embodiment, a conversion between a full density and a half density mode of a memory operation, the present sentence includes: also 仏a 佚 I 居 匕 匕 匕The starting memory operates in a half density mode; and, in the half density operation, the memory system is switched to full when the half density is no longer able to store all the data to be written to the memory. Density mode 8 1289306 is included in one embodiment, a method of operating a memory component is included. The initial memory operates in half of the memory cell. The usage rate; and ~: 2: The array of the switch is switched from the semi-poor production model h to the § 忆 体操 体操 体操 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 至 至 至 至 至 至 至 至 至 至 至 至 至 至 至 至 至 至 至 至丨 Φ recall unit, bean can be: ~ memory system includes: - array of records;: part of the data and transfer the data to the array; and, - memory control: 4 body control system operation of the memory A full ~:""-operator' and when the half-density operation does not have enough about ::::: it is to be written to all the data of the memory from the semi-dense;: Known to switch to full density Mode operation. And in another embodiment, the processing system includes: - processing crying. Then, it is connected to the processor to store the poor materials supplied by the crying and provide information to the clinic. Lu, + to 4 to deal with theft. The memory system includes: -: a memory unit, which can be addressed by an address circuit; a circuit '(4) to receive external data and transmit the data to a queue-memory controller. The memory controller is operated in a wide density or - half density mode, and when semi-dense;::: all has sufficient density to accommodate all of its resources to be written to the memory. + Density mode operation switches to, full density mode operation #. Other embodiments are described and claimed. [Embodiment] The following detailed description of the present invention refers to the description of the drawings, and the present invention is applicable to: the accompanying embodiment 1289306 is shown as an explanation. In the drawings, like reference numerals are used to refer to the embodiments of the present invention. The embodiments are described in detail to enable those skilled in the art to practice the invention. The use of the structure, the logic, and the k-system of the electrician can be made without departing from the scope of the present invention. Therefore, the following detailed description is not meant to be limiting, and the scope of the present invention is only The scope of the appended claims is defined by the scope of the claims, and the scope of the application of the invention is defined by the scope of the claims. FIG. 1 shows an embodiment of the present invention as a structure of a full-density memory 100 that can be implemented thereon.愔鲈 愔鲈 〆 〆 苒 脰 脰 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1 The location of G6 is as shown in the figure. 1 〇 4 mast! # -Γ 士竹 幻幻U, "Ding 106 series can access eight units, each of which is to save the data of individual pieces (piece). And also 丨 a 士. , 牛例吕, celebrity actuation unit 〇, 〇, Lennon and lineage actuation. The second embodiment of the present invention is a structure of a half-length 纟 忆 2 2 2 每 每 每 每 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。兮录士备 再°Hai structure is dedicated to the structure of the memory ,, but the addressing is only τ η , the wood is only different. The memory 2 包含 system includes the same array of memory cells 2 〇 2 ' each of which contains a transistor and a capacitor, which is determined by the individual internal column 204 and the internal row, half-degree "Have memorize 200, each column is paired with a complementary column 'that is: there are two 歹" and two 歹". For example, to activate the unit 〇, 〇, 琴-χϊ χϊ fewer columns Q, and line 0 system actuation. This life is stored in the opposite direction of the poor side of the party \ stay -, where 〇, 〇 and 〇, 0 *. No odd columns are used. 8 8 1289306 Gray In the embodiment of the present invention, a memory system having the same structure as the above-described memory 1 and 2 is used, but the memory operation system of the memory is operable to be half density memory. Body or a full density record ^ Hongvision period! Depending on the application. This operation is accomplished using a memory controller to operate the memory in the manner described below. In one embodiment 300, shown in the flowchart of FIG. 3, a memory power-on (p〇wer ΡΚ·τ' is generated in block 302. In this embodiment, the operation of the memory is at block 304. m is set to the half-density (or 2Τ) mode as the pre-set. It should be extravagant. The same as the one of the half-density presets (for example, full-density operation) can also be set without deviating from the present invention. In the box 3%, a single address is provided to the memory controller or the like, and in decision block 308, "determines whether the location is an odd internal column. If the address is not an I The number of internal columns 'that is, it is an even internal column, then the method flow is the continuation, block 310, in which any even (half density) internal column is accessible. A six-bit address is provided in this way, filled Or use even internal columns until an odd internal column is accessed to decision block 3〇8. At this point, in block 312, the operating system switches to full density (or 1Τ) mode, and any internal column can be Access to block 314. Again, the white line follows ^ #者η我The new order (1) is called) ", adjust the power of the adjustment, so that the update operation occurs in the appropriate -a.). Set the system to the minimum effective 0 (10), the internal column to help: a point, in the whole The operation mode of the density mode will no longer be needed. Thus "method 3 continues to check for any odd number 8 9 1289306 for decision block 3 16 : the partial column is (four). If the odd number (4) and (4) are still (4), the operating system will continue to be in the full density mode, and the method will continue to be the address of block 317. When there are no more odds within the update operation, the method flow is performed before proceeding to block 3〇4.

當二全密度操作而返回至半密度操作日夺,於奇數列的 ::二:係可能為不再需要。該資料係當半密度操作為再 了而刪除’因為寫人程序係、致動偶數字組線,藉著 ==大器而感測該資料(其為正確的原始資料),且接著 為互補於偶數字組線之奇數字組線。當該感測放大 :”動、且重新寫入其為存在於奇數列單元的無論任何 二元日二此係儲存於偶數列單元的資料之反相者於奇數列 n t!全密度至半密度之轉變中,於偶數列之資料係 益入:但是於奇數列之資料係拋棄。於-個實施例中,並 第1=為作成以保留於奇數列之資料。舉例而t,運用於 與2圖所示之配置,當切換自半密度至全密度操作時, 〇,〇列係成為(M列。 χρ 广—個實施例中,作業系統或記憶體控制器係組織 ^ 呆在其為提供至記憶體之前而為寫入於適當的諸When two full-density operations are returned to the half-density operation, the ::2: in the odd-numbered column may be no longer needed. The data is deleted when the half-density operation is repeated. 'Because the writer program is used to activate the even-numbered line, the data is sensed by the == device (which is the correct source), and then complemented. Odd number group line of even digital group lines. When the sense is amplified: "moving, and rewriting it as any binary day existing in the odd column unit, the inversion of the data stored in the even column unit is in the odd column nt! full density to half density In the conversion, the data in the even series is included: but the data in the odd series is discarded. In one embodiment, and the first = is made to retain the data in the odd column. For example, t, applied to In the configuration shown in Fig. 2, when switching from semi-density to full-density operation, 〇, 〇 系 becomes (M column. χρ 广 - In one embodiment, the operating system or memory controller system ^ stays in it Provided to the memory before being written to the appropriate

夕U 0 卷士77、A 田換自全密度模式至半密度模式時,於一個實施例 一 呆留來自奇數内部列之一些資料,資料係儲存於 一緩衝器,# ^ 接者在一刷去更新操作之前而寫入至一偶數 夕丨J。於另— ^ 策係余個實施例中,對於保持來自奇數列的資料之決 汽订於逐列(row by row)或甚至是逐個區塊(block by ίο !289306 block)之基礎。 •十對方、半抬度插作而寫入至記憶體而t,作業 記憶體控制器係被使用於置放資料於相符於操作模式之1 位置,即:於互補列之一者而非 換為僅於盆必須且右爭士h 有精乂允4该切 曰作係開始於半③、度模式,奇數/偶數列的成對者之僅 〇 tttf ^t〇^^(full)Bf , 如為邏輯可能去夕n 士 ' 耳:此者之滿日…該元件為仍需要更大的記憶體 么-’-可數列係寫入。一旦一奇數列係寫入,作業 或記憶體控制器、或其監視資料於記憶體的寫入位置之一 偵、測器係起始全密度操作。並無資料係喪失於自半密度而 =換至王松度’因為全部所為者係其建立於半密度操作的 冗餘性(redundancy)之消除。 於某點,該元件亦可具有一降低的密度需求。在當所 需的密度為下降至低於對於半密度操作的一臨限之時,2 憶體係切換回到半密度操作,以節省電力消耗。若核心記 十思:貝料係初始寫入至下層位址列(半密度列卜接著當該 e己係切換回到半密度操作’所喪失的資料係僅為於系 統之:密度操作期間所加入者之資料。於一個實施例中, 炙半山度紅阼之切換係不發生,直到並無資料為寫入於任 何的奇數内部列為止。 口 农方塊3 1 8所不之刷去更新係包含當轉換自全密度 I作回到半始度操作時而保留資訊於偶數内部列,且更為 詳細顯示於第4圖之流程圖。於一個實施例中,偶數字組 ⑧ 11 1289306 線係致動於方塊400,針對於彼等偶數字組線之資料係以 感測放大器而感測於方塊4〇2,且在感測放大器為穩定之 後,奇it字組線係致動於方& 404。&資料係於偶數=部 列所儲存之原始資料。當該感測放大器係起動於半密度操 作,於偶數内部列之資料的反相者係儲存於其原為奇= 部列而現為針對於各個偶數内部列的互補列者,如為最佳 顯示於第2圖。該二字組線係預先充電於方塊梅,:: 始資料係儲存於主要的單元而其互補者係錯存於互補的單 凡’如同於正常的半密度操作。於一個實施例中,刷去更 新係-獨特的命令。於另一個實施例中,刷去更新係於其 為來自一個稍早的操作之半密度模式的操作期間之任何於 作所運用的相同命令。 本 於另-個實施例中,記憶體之使用率(卿)係被於 =,且當使用率係下降至其充分為低於半使用率之一階: 日守’:憶體係接著切換回到半密度操作。於此實施例中: 一些貧料係可存在於奇數, ^ 1貝枓係必須在該切 …、 密度操作之前而為重新寫入於偶數内部列。When U 0 rolls 77 and A field are changed from full density mode to half density mode, some data from odd internal columns are left in one embodiment. The data is stored in a buffer, #^接接在一刷Write to an even number of 丨J before going to the update operation. In the other embodiments, the decision to keep the data from the odd columns is based on row by row or even block by block (289306 block). • Ten opponents, half-lifted and written to the memory and t, the job memory controller is used to place the data in the position corresponding to the operation mode, that is, one of the complementary columns instead of the replacement For the basin only, and the right squad, there is a fine 乂4, the cutting system starts in the half 3, degree mode, and the pair of odd/even columns is only 〇tttf ^t〇^^(full)Bf , If it is logical, it may go to the evening of the ear. Ear: The full day of this person... Does the component still need more memory?---Coherable column write. Once an odd-numbered column is written, the job or memory controller, or its monitoring data, is one of the write locations of the memory. There is no data loss from semi-density and = change to Wang Song degree' because all of them are based on the elimination of redundancy created by semi-density operations. At some point, the component can also have a reduced density requirement. When the required density drops below a threshold for half density operation, the 2 memory system switches back to half density operation to save power consumption. If the core remembers: the data that is initially written to the lower address column (the half density column and then the switch back to the half density operation) is only for the system: during the density operation The data of the entrant. In one embodiment, the switching of the 炙 山 阼 不 不 不 不 , , , , , , , , , , , , , , , , 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口Contains a flow chart that retains information in the even internal column when converted from full density I back to half-initial operation, and is shown in more detail in Figure 4. In one embodiment, the even-numbered group 8 11 1289306 is a line system. Actuated at block 400, the data for their even digital set lines is sensed by the sense amplifier at block 4〇2, and after the sense amplifier is stabilized, the oddit word line is actuated to the square &; 404. & data is the original data stored in the even = part of the column. When the sense amplifier is activated in semi-density operation, the inversion of the data in the even internal column is stored in its original odd = part of the column And now it is for each even internal column. The list is best shown in Figure 2. The two-character line is pre-charged in the block,:: The beginning data is stored in the main unit and the complement is stored in the complementary single-like 'as in Normal half-density operation. In one embodiment, the refresh-system unique command is swiped. In another embodiment, the brush-out update is any during the operation from a half-density mode of an earlier operation. The same command used in the work. In another embodiment, the memory usage rate is =, and when the usage rate drops to a level that is sufficiently lower than the half-use rate:守': Recall that the system then switches back to the half-density operation. In this embodiment: some lean systems can exist in odd numbers, ^ 1 shellfish must be rewritten in even internals before the cut..., density operation Column.

=此實,例中,作業系統係監視資料之置放,且當操作為 右人自全岔度而改變至半贫产 . A 資料係讀出於—緩衝=二其為待刪去的諸列之 , 友衝☆或類似者,且接著寫入於其資粗蔣 在當操作為切換自全穷^: ' ,八本H ± 山度至+捃度而作保留之諸列。該種 知查及言買出/寫入操作亦 -個實施例。 、们[塊之基礎而貫行於另 於操作時,本發明之—種記憶體係作用如後。該記憶 12 1289306 =一預設的操作係於啟動而起始。於一個實施例中,預 ,又的啟動杈式之操作係半密度操作。於啟動時,,士 ^體g作於半密度操作。於此實施例中,僅有偶數列係 馬入於讀、體功能,該陣列之奇數列係使用為針對於 於此技藝所習知者。寫入至DRAM係作成於偶數 ^ ’針對於密度之需求為超過記憶體的半密度操作之 時。用於記憶體之控制程式係監視資料為寫入至^之位 址旦一奇數列位址係碰到,記憶體控制器係切換該記 憶體之操作至一全密度操作,而加倍該記憶體之密度。當 僅需要半密度時,該記憶體之電力消耗係低於一全密度操 作之包力消耗。然而,當對於記憶體之需求係超過一半密 度刼作之需求時,全密度操作係被使用,且增加的容量係 可利用。記憶體控制器亦監視該記憶體之密度與使用部 刀一 °亥5己憶體為已經切換至一全密度記憶體。由於較 >的貝料為寫入或儲存於記憶體,當半密度操作對於記憶 ••為再人充刀之_時間係將會來到。於此時,該記憶體控 制裔係決定該最後的奇數列資料位址為不再需要,或是決 疋針對方;"己憶體的目前狀態所需要之記憶體密度為低於一 °° 一旦此決定為已經作成,記憶體控制器係切 換操作回到半密度。 如上所述’當切換於全密度操作與半密度操作之間, 怙存於可數列之資料係將喪失。因此,作業系統或記憶體 #工制為係監視其待寫入至記憶體之資料的位址,使得當該 。己L'版為彳呆作於半密度操作時,僅有半密度操作係被使 13 1289306 用。 如已為論述,並未具有於典型的全密度與半密度實體 佈局之間的結構差異。於全密度與半密度模式之差異係於 記憶體之邏輯與控制。本發明之實施例係運用邏輯移位, 以當較低的電力與較少的記憶體密度為所期望或需要而允 許半密度操作,且當較高密度之儲存為需要而允許全密度 操作。 於另一個實施例中,一模式暫存器係運用以驅使記憶 籲體至一正常或一半密度操作而非為預設開啟電源於一半密 度操作模式。舉例而言,若一 〇係寫入至模式暫存器,操 作係強制至全密度。若一 1係寫入至模式暫存器,操作係 強制至半密度。設定該模式暫存器係可“動態(〇n-the-fly)” 達成於操作期間、或是於開啟電源或類似者。再者,一特 定的“重設(reset)”命令係可由使用者所發動以強制操作 至全或半密度模式之操作。若半密度操作為不可行,用於 記憶體控制器或作業系統之一監視器係不允許操作於半密 籲度而直到待儲存的資料量係將適合於記憶體之一半密度配 置為止。於種種的實施例中,設定全密度操作係藉著以一 模式暫存器設定命令、一專用輸入接腳、或類似者而設定 該模式暫存器所達成。 於另一個實施例中,操作係於啟動時而預設至半密度 操作,且儘可能長時間為繼續於半密度,當一奇數列為存 取時而切換至全密度。 偶數與奇數列之規定係運用於本文之說明。應為瞭解 14 1289306 的是:針對於該❹率之其他的術語 — 與奇數係分別意謂著於 且猎者偶數 •^之僅有的諸列為 全密度可利用的諸列為奇數列。可 J為偶數列而於 為舉例而非為限制)係包括.斜' 〃他的術语(僅 列、,,子於偶數列之下層(lower) 一針對灰可數列之上層(upper)列。 一記憶體控制器或其他的作 會竑办I ·、,w w #茶糸統核組係使用於一個 為一機二記憶體之操作。該控制器或作業系統係可 :=Γ媒體,其係執行指令於-處理器'或類似者 達成本文所述的方法。 ^考第5圖,本發明的—個實施例之具有⑽趟如 二,^ 500之簡化方塊圖係被描述。該記憶體元件係可為 4理益51〇,以供雙向資料通訊。該種記憶體係 匕括一§己憶體單元陣列512。控制電路524係提供以響應 方、來自该處理器之控制訊號540而管理資料健存以及操取 自《該陣列。位址電路526、χ解碼器528、與γ解碼器530 係分析位址訊冑542與該陣列之儲存存取位置。感測電路 532係運用以讀取來自該陣列之資料且純輸出資料至U0 電路534。該1/0電路係操作於雙向的方式,以接收來自 處理器510之資料且通過此資料至陣列512。注意:該感 測私路係可為未使周於某些實施例以儲存輸入資料。 動態記憶體係眾所週知,且熟悉此技藝人士係將理解 的疋·上述的dram為已經簡化以提供DRAM技術之_ 基本瞭解且為無意以描述一 DRAM之所有的特徵。 儘管關於半密度操作寫入資料僅為至偶數列之資料寫 15 1289306 入係已經描述於本文,應為瞭解的是: 而宜、 对氧於+密度操作 W馬入資料至僅有奇數列亦為可利用。 僅A啻 用再者,只要資料係 些偶 牛在度刼作係可運用一 :之^ —些奇數列^分的是:可利用的記憶體單 低數者為運用而使得於半密度操作之電力消耗為降 :低電力節省,其 只現。再者,全密 該記憶體係可返回 下層半部所儲存的= In this case, in the example, the operating system is the placement of the monitoring data, and when the operation is changed from the full man to the semi-period. The A data is read in - buffer = two is the one to be deleted. Listed, You Chong ☆ or similar, and then written in its ruling Jiang in the operation to switch from the whole poor ^: ', eight H ± mountain to + 而 degrees for reservations. This kind of knowledge and speaking buy/write operation is also an embodiment. When the [blocks are based on other operations, the memory system of the present invention functions as follows. The memory 12 1289306 = a preset operation starts at startup. In one embodiment, the pre-open operation is a half density operation. At startup, the g body is operated at half density. In this embodiment, only the even columns are in the read and body functions, and the odd columns of the array are used as is known to those skilled in the art. Writing to the DRAM is done at an even number ^' when the density is required to exceed the half density of the memory. The control program for the memory is monitored by the address written to the address of the odd-numbered address, and the memory controller switches the operation of the memory to a full-density operation, and doubles the memory. The density. When only half density is required, the power consumption of the memory is lower than the package power consumption of a full density operation. However, when the demand for memory is more than half the density, a full density operation is used and the increased capacity is available. The memory controller also monitors the density of the memory and uses the knives to switch to a full-density memory. Since the > beaker is written or stored in the memory, when the half-density operation is for the memory, the time will come. At this time, the memory control system determines that the last odd-numbered data address is no longer needed, or is determined to be targeted; "the memory state density of the current state of the memory is less than one° ° Once this decision is made, the memory controller switches back to half density. As described above, when switching between full density operation and half density operation, the data stored in the countable column will be lost. Therefore, the operating system or the memory system is to monitor the address of the data to be written to the memory so that it is. When the L' version is used for half-density operation, only the half-density operation system is used for 13 1289306. As discussed, there is no structural difference between a typical full density and a half density physical layout. The difference between full density and half density modes is based on the logic and control of the memory. Embodiments of the present invention utilize logical shifting to allow for half density operation when lower power and less memory density are desired or needed, and allow full density operation when higher density storage is needed as needed. In another embodiment, a mode register is utilized to drive the memory to a normal or half density operation rather than turning the power on in a half density mode of operation. For example, if a system is written to the mode register, the operation is forced to full density. If a 1 is written to the mode register, the operating system is forced to half density. Setting this mode register can be "dynamically (〇n-the-fly)" achieved during operation, or when power is turned on or the like. Moreover, a particular "reset" command can be initiated by the user to force operation to full or half density mode. If half-density operation is not feasible, the monitor used in the memory controller or operating system is not allowed to operate at half-compact until the amount of data to be stored is suitable for one-half density configuration of the memory. In various embodiments, setting the full density operation is accomplished by setting the mode register with a mode register setting command, a dedicated input pin, or the like. In another embodiment, the operation is preset to a half density operation at startup and continues to a half density for as long as possible, and switches to full density when an odd column is accessed. The provisions for even and odd columns are used in the description of this document. It should be understood that 14 1289306 is: the other terminology for the rate - the only columns with odd-numbered systems and the even number of hunters are ^. The columns that are available for full density are odd columns. J can be an even-numbered column and is by way of example and not limitation.) The term includes: oblique ' 仅 his term (column only, sub-lower sub-column (lower) one for gray-corable upper-level (upper) column A memory controller or other device will be used for the operation of one computer and two memory devices. The controller or operating system can: = media, It is the implementation of the instructions in the processor - or the like to achieve the method described herein. ^ Figure 5, a simplified block diagram of (10), such as two, ^ 500, of the embodiment of the present invention is described. The memory component can be a two-way data communication. The memory system includes a memory cell array 512. The control circuit 524 provides a response signal from the processor 540. The management data is stored and manipulated from the array. The address circuit 526, the χ decoder 528, and the γ decoder 530 analyze the address 542 and the storage access location of the array. The sensing circuit 532 is used. To read the data from the array and the pure output data to U0 circuit 534. This 1/ The 0 circuit operates in a bidirectional manner to receive data from the processor 510 and to pass the data to the array 512. Note that the sensing private path may not be used to store input data in some embodiments. The system is well known and will be understood by those skilled in the art. The above-mentioned dram is a basic understanding that has been simplified to provide DRAM technology and is not intended to describe all the features of a DRAM. The data to the even series is written in 15 1289306. The system has been described in this paper. It should be understood that it is appropriate to operate the data in the + density to the odd-numbered column. Only A is used. As long as the data is used by some of the cows in the system, one can use one of them: some odd-numbered columns are: the available memory low-numbered ones are used to make the power consumption of the half-density operation lower: low Power saving, it only appears. Moreover, the full-density memory system can return to the lower half of the memory

本發明之種種實施例的優點係包括 係§ 一減少量的記憶體為運用時而自動 度知作之裨益係當需要而提供。甚者, 至半雄、度操作而未喪失於記憶體陣列之 屬料。 不發明之種種實 具有可利用之一有限量的電力之裝用於 1, ^ 且洧如•類似於手 二::或個人數位助理之可攜式褒置。於一個實施例, 7係可為儲存於下層記憶體陣列且該記憶體 置為於備用模式或啟動模式而操作於半密度操 : 曰“广資料係可於操作期間而儲存於全陣列。此資料儀 拋茱且該記憶體為返回至針對 ^ ^ J粒式叙置的備用或睡£ 糗式之共下層電力狀態,而未喪失任何的應用資料。 本發明之實施例係包括—可配置的記憶體(於 例··一 DRAM),1自動切施*入企一 Ά力 〃自動切換方;“、度的低功率操作 多 知作之間’針對於由系統所需之增大的密度。亦為揭: 者係返回記憶體至半密度操作之-種方法,針對於自我; 16 1289306 新電力節省而未喪失所錢 記憶體係以其最低的自我子、]資料。於開啟電源之期間, 所有操作係於偶數内部列而:電力而預設至半密度操作。 止。該記憶體係維持於卜到所有的偶數内部列為滿為 存取為止,於其點,^己二度操作而直到一奇數内部列為 記憶體操作。是以,自我自動轉換至正常的全密度 大的電力而調整。 4盼序係隨著全密度操作之增 一重設序列係當或若 該記憶體回到半密度操作定::、:為期望時而加入以轉換 維持其為初始運用於半密:更新刷去操作係加入以 料。本發明之_刷去 X本之於偶數列所儲存的資 知月之刷去更新的實施例 組線·,感測於-感測放大器之資I ^ 〇力-偶數字 在感測放大器為敎後而致動正確的原始資料” 相資料於單元預1#〜 數子、、且線(因此自動健存反 料於主要的…、亥二字組線;及’儲存原始的資 卄方、主要的早兀且儲存互補 … 於半密度操作所需者。 、d 也早如為針對 藝人施例係已經圖示且說明於本文,熟悉此技 可為替代^ 是:估計以達成相同目的之任何配置係 發明之任二、:的特定實施例。此申請案係意圖以涵蓋本 月 < 任何的修改 係僅為受限於申請專利範圍與其均等 ^ 【圖式簡單說明】 士:圖係-種全密度記憶體元件之部分電路圖; 乐圖係-種半密度記憶體元件之部分電路圖; 17 1289306 第3圖係根據本發明之一個實施例的一種方法之流程 圖; 第4圖係根據本發明之另一個實施例的一種更新刷去 操作之流程圖;及 第5圖係本發明可為實行於其的一種系統之方塊圖。 【主要元件符號說明】 100 :全密度記憶體 102 :記憶體單元 104 :歹丨J 106 :行 200 ··半密度記憶體 202 :記憶體單元Advantages of various embodiments of the present invention include the fact that a reduced amount of memory is automatically provided for use when needed. Moreover, to the semi-male, the operation is not lost to the memory array. The inventions that are not invented have a limited amount of power available for use in 1, ^ and such as • portable 2:: or personal digital assistants. In one embodiment, the 7 series can be stored in the lower memory array and the memory is placed in the standby mode or the startup mode to operate in the half density operation: 曰 "The wide data system can be stored in the full array during operation. The data device is thrown and the memory is returned to the standby or sleepy common underlying power state for the ^J J granular presentation without losing any application data. Embodiments of the present invention include - configurable The memory (in the case of a DRAM), 1 automatic cut * into the enterprise, the power of the automatic switching party; ", the degree of low-power operation between the knowledge of the 'for the increase required by the system density. Also for the disclosure: the method of returning from memory to semi-density operation, for self; 16 1289306 new power savings without losing money The memory system with its lowest self,] data. During the power-on period, all operations are in an even internal column: power is preset to half-density operation. stop. The memory system maintains until all even internal columns are fully accessed, at which point the operation is performed until an odd internal column is a memory operation. Therefore, the self-automatic conversion to normal full-density power is adjusted. The sequence of the sequence is reset with the full density operation when the sequence is reset or if the memory is returned to the half density operation: :, : added as desired and converted to maintain it as the initial application for semi-dense: update brush The operating system is added to the material. According to the present invention, the brush of the X-think is stored in the even-numbered column, and the updated embodiment of the brush line is sensed. The sense of the sense amplifier is I ^ 〇 - the even number is in the sense amplifier. Afterwards, the correct original data is actuated. The data is in the unit pre-1#~number, and the line (so the automatic health is reflected in the main..., the two-character line; and the 'original asset' , the main early and storage complementary ... for the half-density operation required., d as early as for the artist's example has been illustrated and described in this article, familiar with this technique can be an alternative ^ is: estimate to achieve the same purpose Any configuration is a specific embodiment of the invention: this application is intended to cover this month <any modification is limited only by the scope of the patent application and its equality ^ [simple description of the schema] A partial circuit diagram of a full-density memory component; a partial circuit diagram of a half-density memory component; 17 1289306 Figure 3 is a flow diagram of a method in accordance with one embodiment of the present invention; Another implementation in accordance with the present invention A flowchart of an update brushing operation; and Fig. 5 is a block diagram of a system implemented therein. [Main component symbol description] 100: Full density memory 102: Memory unit 104: 歹丨J 106 : Line 200 ··Half Density Memory 202: Memory Unit

204 :歹丨J 2 0 6 :行 500 :系統204 :歹丨J 2 0 6 : Line 500 : System

502 ·· DRAM 5 1 0 :處理器 5 1 2 :記憶體單元陣列 524 :控制電路 526 :位址電路 528 : X解碼器 530 : Y解碼器 5 3 2 ·•感測電路 534 : I/O 電路 ⑧ 1289306 5 4 0 :控制訊號 542 :位址訊號502 ·· DRAM 5 1 0 : processor 5 1 2 : memory cell array 524 : control circuit 526 : address circuit 528 : X decoder 530 : Y decoder 5 3 2 ·• sense circuit 534 : I/O Circuit 8 1289306 5 4 0 : control signal 542: address signal

1919

Claims (1)

1289306 4 ...........I _IM|, .......................... 月和修(更) 十、申請專利範園 1. 一種操作記憶體元件之方法,包含: 以半密度模式僅將資料寫入偶數 等偶數内部列為滿為止; 數内M,直到所有該 當一奇數内部列為首先存取時,切換至全密度模式; 以全密度模式寫入至任一列; 中 當並無奇數列為仍需要時,切換回到半密度模式,其 切換回到半密度模式係包含: 該記憶體元件内剩餘的原始資料,以將所有剩餘 的貝料寫入至該記憶體之偶數列;及 更新刷去。 2. 如申請專利_ i項之方法,其中,更新 包含: 致動含有半密度資料之一偶數字組線; 藉著一感測放大器而感測該資料;1289306 4 ...........I _IM|, ......................... Month and repair (more) 1. A method for operating a memory component, comprising: in a half density mode, only writing data to an even number of internal even columns is full; within a number M, until all of the odd internal columns are first accessed Switch to full density mode; write to any column in full density mode; switch to back to half density mode when there is no odd number listed as needed, switch back to half density mode: The remaining raw data is written to write all remaining beakers to the even columns of the memory; and the update is swiped. 2. The method of claim 1, wherein the updating comprises: actuating an even digital group line containing half density data; sensing the data by a sense amplifier; 致動一奇數字組線; 預先充電該二個字組線;及 儲存組織過的原始的資料於該偶數字組線且儲存互補 的資料於該奇數字組線。 其中,組織資料係 3·如申請專利範圍第1項之方法 包含: 決定自奇數列而來的什麼資料將被儲存; 儲存自奇數列而來將被儲存的資料於一個緩衝器之 内;及 σ 1289306 在個更新刷去之前,將自該緩衝ϋ而來之自奇數列 而來將被儲存的資料寫入至一個偶數列。 4_如申請專利範圍第μ之方法,其中,衫自奇數 列而來的什麼資料將被儲存係以—個逐列㈣吻叫之基 礎被實施。 5·如申請專利範圍第w之方法,其中,決定自奇數 歹J而來的什麼貝料將被儲存係以_個逐個區塊 block)之基礎被實施。 /·如申請專利範圍第μ之方法,其中,切換至半密 又Γ、式更^ 3針對於半推度操作而改變該記憶體之自我 更新時序。 申月專利範圍第1項之方法,切換回到半密度模 式更包含: 監視該記憶體元件之使用率;及 當該記憶體内所有將被儲存之資料係能夠儲存於該記 隐體7G件之—個半密度組態時’起動切換回到半密度模 式。 8·一種記憶體,包含·· 一陣列之記憶體單元,其可為由位址電路所定址; 輸入/輸出電路’其係接收外部資料且傳送該 該 陣列,·及 ::憶體控制器’其係用於操作該記憶體於一全密度 操作成::镇式之操作的一者’其令,該記憶體控制器係 、乍成貧轭一種方法,該方法包含·· 〆、^ ·.· ι- ^ .··*' 21 1289306 * ^ 當半密度操作為不具有足夠密度以容納待寫入至該記 It體的所有資料時,自該半密度模式之操作切換至全密度 杈式之操作,且當並無奇數列為仍需要時,切換回到半密 度模式,其中,切換回到半密度模式係包含: ^組織記憶體元件内剩餘的原始資料,以將所有剩餘的 資料寫入至該記憶體之偶數列;及 更新刷去。 _ 9·如申請專利範圍第8項之記憶體,其中,該記憶體 元件係為一個處理系統之一部分,該處理系統係包含: 一處理器其係連接至該記憶體,以儲存由該處理器所 提供的資料且提供資料至該處理器。 10·如申請專利範圍第8項之記憶體,其中,更新刷 去係包含: 致動一條含有半密度資料之偶數字組線; 藉著一感測放大器而感測該資料; _ 致動一奇數字組線; 預先充電該二個字組線;及 儲存組織過的原始的資料於該偶數字組線且儲存互 的資料於該奇數字組線。 11 ·如申請專利範圍第8項之記憶體,其係進一步包 含: 一個緩衝器;且 其中,於該方法内組織資料係包含·· 決定自奇數列而來的什麼資料將被儲存; 22 1289306 ^ f 儲存自奇數列而來將被儲存的資料於該緩衝器之内; 及 在一個更新刷去之前,將自該緩衝器而來之自奇數列 而來將被儲存的資料寫入至一個偶數列。 12·如申請專利範圍第丨丨項之記憶體,其中,決定自 奇數列而來的什麼資料將被儲存係以一個逐列(r〇w by r〇w) 之基礎被實施。 13·如申請專利範圍第丨丨項之記憶體,其中,決定自 I奇數列而來的什麼資料將被儲存係以一個逐個區塊…比仏 by block)之基礎被實施。 14·如申請專利範圍第8項之記憶體,其中,切換至 半密度模式更包含:針對於半密度操作而改變該記憶體之 自我更新時序。 如申請專利範圍第8項之記憶體,其中,切換回 到半密度模式更包含: N _ 監視該記憶體元件之使用率;及 當該記憶體内所有將被儲存之資料係能夠儲存於該記 憶體元件之一個半密度組態時,起動切換回到半密度模 式。 十一、圈式: 如次頁 23Actuating an odd digital group line; precharging the two word lines; and storing the original data that has been organized on the even number line and storing the complementary data on the odd number line. Among them, the organization data system 3 · The method of claim 1 of the patent scope includes: determining what data from the odd number column will be stored; storing the data stored from the odd number column in a buffer; and σ 1289306 Before the update is swiped, the stored data is written from the buffer to the even column. 4_ As for the method of applying for the patent range, the information from the odd number of shirts will be stored in a column-by-column (four) kiss basis. 5. The method of claiming the patent range, wherein it is determined that the material from the odd number 歹J will be stored on a basis of _ block by block. / · For example, the method of applying the patent range No. μ, wherein switching to semi-closed, 更, and ^ 3 changes the self-renewal timing of the memory for the half-push operation. The method of the first aspect of the patent scope of the patent, switching back to the semi-density mode further comprises: monitoring the usage rate of the memory component; and storing all the data to be stored in the memory in the 7G piece of the hidden body In the case of a half-density configuration, the start switches back to the half-density mode. 8. A memory comprising: an array of memory cells, which may be addressed by an address circuit; an input/output circuit 'which receives external data and transmits the array, and:: a memory controller 'It is used to operate the memory at a full density operation: one of the operations of the town type', the memory controller is a method of yoke deficiency, the method includes ·· 〆, ^ ··· ι- ^ .··*' 21 1289306 * ^ Switching from the operation of the half density mode to full density when the half density operation is not sufficient to accommodate all the data to be written to the It body The operation of the 杈 type, and when there is no odd number listed as still needed, switch back to the half density mode, wherein switching back to the half density mode includes: ^ The original data remaining in the organization memory component to all remaining The data is written to the even columns of the memory; and the update is swiped. _9. The memory of claim 8 wherein the memory component is part of a processing system, the processing system comprising: a processor coupled to the memory for storage by the processing Information provided by the device and provided to the processor. 10. The memory of claim 8 wherein the updating brush comprises: actuating an even digital group line containing half density data; sensing the data by a sense amplifier; _ actuating a An odd number group line; pre-charging the two word line lines; and storing the organized original data on the even number group line and storing the mutual data on the odd number group line. 11) The memory of claim 8 of the patent scope further comprising: a buffer; and wherein the organization of the data in the method comprises: determining what data from the odd number column will be stored; 22 1289306 ^ f stores the stored data from the odd-numbered column in the buffer; and writes the stored data from the buffer to the odd-numbered column before an update is swiped Even columns. 12. In the case of the memory of the scope of the patent application, in which the data from the odd-numbered series is determined to be stored on a column by column basis (r〇w by r〇w). 13. If the memory of the third paragraph of the patent application is applied, the information determined from the odd-numbered columns will be stored in a block-by-block basis. 14. The memory of claim 8 wherein switching to the semi-density mode further comprises: changing the self-renewal timing of the memory for half density operation. For example, the memory of claim 8 wherein switching back to the half density mode further comprises: N _ monitoring the usage rate of the memory component; and storing all data to be stored in the memory in the memory When a half density configuration of the memory component is configured, the startup switches back to the half density mode. Eleven, circle: as the next page 23
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EP1761932B1 (en) 2008-05-28

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