TWI288328B - Non-volatile memory and method with non-sequential update block management - Google Patents

Abstract

In a nonvolatile memory with block management system that supports update blocks with non-sequential logical units, an index of the logical units in a non-sequential update block is buffered in RAM and stored periodically into the non-volatile memory. In one embodiment, the index is stored in a block dedicated for storing indices. In another embodiment, the index is stored in the update block itself. In yet another embodiment, the index is stored in the header of each logical unit. In another aspect, the logical units written after the last index update but before the next have their indexing information stored in the header of each logical unit. In this way, after a power outage, the location of recently written logical units can be determined without having to perform a scanning during initialization. In yet another aspect, a block is managed as partially sequential and partially non-sequential, directed to more than one logical subgroup.

Description

1288328 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to non-volatile semiconductor memory, and more particularly to non-volatile semiconductor memory having various memory management systems. [Prior Art] Solid-state memory capable of non-volatile storage of electric charge, especially in the form of EEPROM and flash EEPROM packaged into a small memory card, has recently become a storage device for various mobile and handheld devices, especially information. Electricity and consumer electronics. Unlike RAM, which is also a solid-state memory (random access memory), the flash memory system is non-volatile, retaining its stored data even after the power is turned off. Also, unlike R〇M (read-only memory) flash memory and disk storage devices are rewritable. Despite the high cost, the use of flash memory is increasing in mass storage applications. Conventional mass storage devices based on rotating magnetic media, such as hard disk drives and floppy disks, are not suitable for mobile and handheld environments. This is because the disk drive tends to be bulky, easily mechanically faulty, and has high latency and high power requirements. These unwanted attributes make disk-based storage devices inaccessible to most subscription and portable applications. On the other hand, the Xenon flash memory, which is both in the form of a spoofed and removable memory card, is ideally suited for mobile and handheld environments because of its small size, low power consumption, high speed and high reliability. characteristic. Flash EEPROM and EEpR〇M (electronically erasable and programmable read-only memory) are similar in that they can be erased and can write or privately write new data to their memory cells. Non-volatile memory. Both 98704.doc 1288328 utilize floating (unconnected) conduction (4) above the channel region in the semiconductor substrate and between the source and the polar regions in the field effect transistor structure. A control gate is then provided over the floating gate. The amount of charge retained by the floating closed-pole controls the limiting voltage characteristics of the transistor. That is to say, in terms of the charge on the floating gate, the corresponding voltage (limit) must be applied to the control gate before the transistor is "on" to allow the source and the gate region to be Conductive between. In particular, flash memory such as flash EEPROM allows the entire block of memory cells to be erased simultaneously. The floating gate can maintain a certain charge range and, therefore, can be programmed to any defined voltage level within the threshold voltage window. The size of the threshold voltage window is limited to the minimum and maximum limits of the device, and the minimum and maximum limits of the device correspond to the range of charge that can be programmed onto the floating gate. The limit window is generally based on the characteristics of the memory device, operating conditions, and recording. In principle, the different and analyzable limits of the limits in the 'window' can be used to specify the explicit memory state of the unit. A transistor that is a memory cell is usually turned into a private state by one of two mechanisms. In "hot electron injection", the return voltage applied to the drain accelerates electrons across the channel region of the substrate. At the same time, the high voltage applied to the control gate attracts hot electrons through the thin gate dielectric to the oceanic gate. In the "wearing the person" towel, the control gate is applied with respect to the applied-high voltage. In this way, the substrate can be attracted to the intermediate floating gate. Although it is customary to use the "stylization" to describe the initial erasing charge storage unit that injects electrons into the memory unit to write to the memory to change the memory state, now and more common terms, 98704.doc 1288328 eg " Write or "record" exchange use. The following devices can be used to erase the memory device. For the EEPROM 3, by applying a high (four) to the control gate relative to the control gate, the electrons can be induced in the floating gate to pass through a thin oxide into the substrate channel region (ie, , F〇wl〇N〇rdheim tunneling effect) can be used to erase a memory unit. In general, EEpR〇M can be erased on a byte by byte basis. For flash EEPROM, each time: erase all memory or erase more than one minimum erasable area each time. The smallest erasable block of ghosts may be more than one segment. And the parent area can store more than 5 12 bytes of data. The memory device includes a memory chip that can be mounted on a memory card. Each memory chip includes a memory cell array supported by peripheral circuits such as decoders and circuits such as erase, write, and read. The more sophisticated Z L body is also equipped with a controller that performs intelligent and higher-order memory operations and interface connections. There are many commercially available non-volatile solid state memory devices available today. These memory devices may be flash EEPR0M or other types of non-volatile memory cells may be used. Examples of flash memory and systems and methods of fabricating the same are disclosed in U.S. Patent No. 5, (7), No. 5, No. 5, 315, 541, No. 5, 343, 063, No. 5, 661, No. 53, No. 5, 313, (3) and 6,222,762. Specifically, a flash memory device having a NAND string structure is described in U.S. Patent No. 1, No. 35. Alternatively, a memory unit for storing the charge interface layer can be used to make a non-volatile memory 98704.doc 1288328 body device. It replaces the previously described conductive floating gate 7C with a dielectric layer. Such memory devices utilizing dielectric storage elements have been described by Eitan et al. in IEEE Electr〇n Device [Deduction (10), Vol. 21, No. 11, pp. 543_545, NR, January 2000). 〇M: AN〇vel

Localized Trapping, 2-Bit Nonvolatile Memory Cell. A dielectric layer extends across the channel between the source and drain diffusion regions. The charge of one of the data bits is localized in the dielectric layer near the drain, and the charge of the other data bit is localized in the dielectric layer near the source. For example, U.S. Patent Nos. 5,768,192 and 6,011,725 disclose a non-volatile memory cell in which a trapping dielectric is sandwiched between two layers of germanium dioxide. Multiple state data storage can be achieved by separately reading the binary state of the charge storage region separated by the space within the dielectric. To improve read and program performance, multiple charge storage elements or memory transistors in the array are read or programmed in parallel. Therefore, it will read or program the memory element phase "page". In the prior art, the -column usually contains a number of interleaved pages or a list of all memory elements that can constitute a page of pages that are read or stylized together. In flash memory systems, erase operations may require orders of magnitude greater than read and program operations. Therefore, it is desirable to have a large-sized erase block. In this way, the erase time on the purely large unit can be reduced. Depending on the nature of the flash memory, the data must be written to the erased memory location. If you want to update the data of a specific logical address of the host, one way 98704.doc 1288328 is to write the updated data to the same physical memory location. That is, the logic does not change the physical address mapping. However, this means that the entire erase block containing the physical location must be erased before being written with the updated data. This update method is inefficient because it needs to erase and rewrite the entire erase block' especially when the data to be updated occupies only a small portion of the erase block. In addition, it will result in the eradication of memory blocks that are relatively frequent, which is not ideal for the limited durability of this type of memory device. Another problem with managing flash memory systems is that they must handle system control and directory data. This data is generated and accessed during the course of various memory operations. Therefore, its effective processing and rapid access will directly affect performance. Since flash memory is used for storage and is non-volatile, it is desirable to be able to maintain this type of data in the f-flash. However, because there is an intermediate file management system between the controller and the flash memory, the data cannot be accessed directly. Also, 'system control and catalog data tend to be active and fragmented' and this is not helpful for storage in systems with large block erases. As is customary, this type of material is set in the controller RAM, thereby allowing direct access by the controller. After powering up the memory device, the initialization program scans the flash memory to compile the necessary system control and directory information to be placed in the controller RAM. This procedure is both time consuming and requires controller RAM capacity, especially for ever-increasing flash memory capacity. US 6,567,307 discloses a method of processing a sector update in a large erasure block, which includes recording 98704.doc -10· 1288328 new data in a plurality of erase blocks that are available as available memory areas, and finally in various The valid sections are summarized in the block, and then the valid sections are rearranged in logical sequential order before being written. In this way, it is not necessary to erase and rewrite blocks at each of the tiniest updates. Both W0 03/027828 and W0 00/49488 disclose an updated memory system for processing large erase blocks, including dividing logical sector addresses in units of regions. The logical address range of a small area is reserved for active system control data that is separate from another area for user data. In this way, system control data manipulation in its own area does not interact with user data associated with another area. The update belongs to the logical segment level, and the write metric points to the corresponding physical segment in the block to be written. The mapping information is buffered in RAM' and finally stored in the section configuration table of the main memory. The latest version of the logical section will eliminate all previous versions in the existing block, which will therefore become partially eliminated. Performing a collection of abandoned items can maintain a partially eliminated block as an acceptable quantity. Prior art systems tend to distribute updated data across many blocks or to update data to partially eliminate many existing blocks. The result is usually a large collection of obsolete items required for partially eliminated blocks, which is inefficient and leads to premature aging of the memory. Also, there is a lack of a systematic and efficient way to handle sequential updates compared to non-sequential updates. Therefore, high-capacity and high-performance non-volatile memory is generally required. In particular, there is a greater need for high-capacity non-volatile memory that is capable of performing memory operations in large blocks without the above problems. SUMMARY OF THE INVENTION Entity of physical memory location A non-volatile memory system is organized according to the group 98704.doc 1288328. Each entity group (relay block) is an erasable emerald and can be used to store data of a logical group. The memory management system allows to update a logical group by means of a relay zone dedicated to the update data of the configuration log logical group (4). The Q update (four) block records the updated poor material according to the received order' and the record is original. There is no limit to the correct logical order of storage (10) or not (chaos). Finally, the update relay block is closed for additional recording. A number of procedures will occur - 'but will eventually end up with a relay block that replaces the original relay block that is completely filled in the correct order. In the case of confusion, the directory data is maintained in non-volatile memory in a way that facilitates frequent updates. The system supports multiple logical groups that are updated simultaneously. One feature of the present invention allows data to be updated in a logical group by group manner. Therefore, when updating a logical group, the distribution of logical units (and the distribution of memory cells that have been eliminated) is limited. This is especially true when the logical group is usually contained within a physical block. During the update of a logical group, one or two blocks that buffer the updated logical unit must typically be assigned. Therefore, it is only necessary to perform obsolete project collection on a relatively small number of blocks. The collection of obsolete items in the chaotic block can be performed by summarizing or compressing. (4) In the case of sequential blocks, the economic efficiency of the update process will become more apparent in the process of updating the blocks, so there is no need to update the *blocks for the chaotic (non-sequential). All update blocks are configured to be sequential 2 new blocks and any update block can be changed to a confusing update W. More specifically, the -update block can be arbitrarily changed from sequential to chaotic. 98704.doc -12- 1288328 Effective use of system resources allows multiple logical groups to be updated simultaneously. This can further increase efficiency and reduce excessive consumption. k Memory alignment dispersed over a plurality of recording planes according to another aspect of the invention, organized into a plurality of erasable blocks and composed of a plurality of memory planes (and thus can be read in parallel) a plurality of logical units or a memory array in which a plurality of logical units are parallelized into the plurality of planes, when the original logical unit stored in the first block in the specific memory plane is to be updated, The supply is required to keep the updated logical unit in the same plane as the original. This can be done by recording the updated logical unit to the next available location of the second block that is still in the same plane. Preferably, the logic cells are stored in a plane in the same displacement position as the other versions, such that all versions of a given logic unit are served by the same set of sensing circuits. Accordingly, in a preferred embodiment, any intermediate gap between the last stylized memory unit and the next available planar aligned memory unit is filled with the current version of the logical unit. The current version of the logical units logically located after the last programmed logical unit and the current logical unit located in front of the logical units stored in the next available planar aligned memory unit The filling can be completed by filling in the gap. In this way, all versions of the logical unit can be maintained in the same plane with the same displacement as the original, so that in the waste project collection operation, it is not necessary to extract the latest version of the logical unit from different planes to avoid performance degradation. In a preferred embodiment, the latest version can be used to update 98704.doc -13 - 1288328 or to fill the I-seven & parent a-remember cell on the plane. Thus, the logical units can be read out in parallel from each plane, which will have a logical sequence without further rearrangement. This scenario is based on allowing the new version of the logical unit of the logical group to be rearranged on the plane' without having to collect the latest version of the different memory planes, and shrinking the time of the total chaotic block. This report has the advantage, in which the effect of the host interface; ^ can be used to complete the maximum waiting time for the segment write operation by the Z memory system. Staged Program Error Handling According to another aspect of the present invention, in a memory having a block management system, during a time-critical memory operation, a program failure in the block can be continued by interrupting the block (breakout blGek) The stylized operation of t to deal with. After the manuscript, in less urgent times, the data recorded in the failed block before the interruption can be transferred to other blocks that may also be interrupted blocks. The failed block can then be discarded. In this way, when a defective block is encountered, it will not be processed because the data stored in the defective block must be transferred immediately and the specified time limit is exceeded. This mishandling is especially important for the collection of waste projects. Therefore, it is not necessary to repeat the entire operation for a new block during an emergency time. At the appropriate time, the defective block can be saved by reconfiguring to other blocks. data of. Program failure handling is especially important during rollup operations. A normal summary operation summarizes the current versions of all logical units resident in the original block and the updated block to the summary block. During the rollup operation, if a program failure occurs in the summary block, then another block that is used as the interrupt 98704.doc -14- 1288328 summary block is provided to receive the summary of the remaining logical units. In this way, = logical unit must be copied more than one time, and the exception processing can still be completed within the normal = operation specified by =. At the appropriate time, all the unprocessed logical units of the group are summarized into the interrupt block to complete the capsule operation. A suitable time would be one in addition to the current host write operation = a period of time during which the capsule is total. One such suitable time = the essence of another host write in which there is an update but no associated capsule operation, the summary of program failure handling can be considered as multi-stage 杳^ in the first stage, in the occurrence After the material fails, cut the logic single ^ ~ to more than one block 'to avoid summarizing each logical unit - more than one time. (4) The appropriate time will be completed in the final stage, where the logical group will be merged to better collect all logical units in a financial order.

Interrupt summary block. Another aspect of the invention of the fI non-sequential update block index is that in the non-volatile memory supporting the non-sequential logic Cuiyuan update block management system, the index of the non-sequenced logic element is buffered. In the ram, and the regular index is stored in the special, in the specific embodiment, the 隹 is dedicated to the block in which the index is stored. In another example, the cable is stored in the update block itself. In another case, ^: Example: The index is stored in the header of each logical unit. In another aspect, after the last index update but in the next "丄4 side logical unit is prepared, the n iu home update is written to 曰,, and the index information is stored in the header of each logical unit. in. 98704.doc -15- 1288328 In this way, after a power interruption, it is not necessary to perform a scan during initialization to determine the location of the most recently written logical unit. In yet another aspect, the block is managed in a partial sequence and a portion of the non-sequentially directed to more than one logical subgroup. Controlling Data Integrity and Management In accordance with another aspect of the present invention, additional levels of reliability are guaranteed if critical lean materials, such as some or all of the control material, are maintained in the replicated item. The execution of the copy is any stylization in the second encoding process for a multi-state memory system that uses a two-pass encoding process (tw〇_pasy stylization technique to continuously program multiple bits of the same set of memory cells). Errors can't damage the data created by the first encoding process. Copying can also help detect write aborts, detect false positives (ie, two replicas have good Ecc but different data), and can add additional levels of reliability. Tenth. If + material copying techniques have been considered. In a specific embodiment, after stylizing two copies of a given data in a slightly stylized encoding process, the subsequent stylized encoding process can avoid stylization. And storing at least one of the two copies of the two copies. In this manner, at least one of the two copies is not suspended until the subsequent stylized encoding process terminates and destroys the data of the earlier encoding process. In another embodiment, two copies of a given data are stored in two different blocks, and at most only two of the two copies One of the memory units will be stylized in a subsequent stylized encoding process. 98704.doc -16- 1288328 In another embodiment, after two copies of a given material, the memory of the notebook The unit group implements the final stylized encoding process of any incoming unit group to achieve this purpose. The private encoding process stores a program that is no longer used to store the two further steps. The two copies of the two copies are programmed in another way, and the two copies of a given data can be programmed into a multi-state memory in a stylized pattern.

In the body, the shirt will perform any further stylization of the stylized memory unit. In the case of another-item, it uses two: the under-programming (four) program-based technology to continuously program the multi-state memory system of the same group of memory elements, 'will use the fault-tolerant code to encode more The memory state' makes the data created by the early stylized encoding process unaffected by errors in the subsequent stylized encoding process. According to another aspect of the invention, non-volatile in a block management system

In the memory, you can implement the “Control Waste Project Collection” or the preemptive reconfiguration of the memory block to avoid a large number of update blocks happening on the same day: but to reconfigure. This can happen, for example, when updating control data that is used to control the operation of the block. The hierarchy of control data types can coexist with varying degrees of update times, resulting in their associated update blocks and the collection or reconfiguration of obsolete items at different rates. There will be more than one specific number of simultaneous acquisitions of the obsolete items that control the data type. In extreme cases, the reconfiguration phase of all update blocks of the control data type is reorganized, causing all update blocks to be reconfigured at the same time as 98704.doc -17-1288328. Other features and advantages of the present invention will become apparent from the following description of the preferred embodiments of the invention. [Embodiment] The figure shows a main hardware component of a memory system suitable for implementing the present invention in a schematic view. The memory system 20 typically operates as a host through the host interface. Memory (4) is usually in the form of a job card or an embedded memory system. The memory system 20 includes a memory 2 that is controlled by the controller i 〇〇. The memory 200 includes zero or a plurality of arrays of non-volatile memory cells distributed over one or more integrated circuit wafers. The controller 1 includes: an interface 11 〇, a processor 120, an optional sub processor 丨 2 卜 R 〇 M 〗 2 2 (read only memory RAM 130 (random access memory), and optional program Non-volatile memory 124. Interface 11() has a component that connects the controller to the host and another component that is connected to the memory 200. Stored in a non-volatile ruler River 122 and/or selected for non-volatile s The firmware in the memory 124 can provide the processor 12 code to implement the functions of the controller 100. The processor 12 or the optional secondary processor ΐ2 can process the error correction code. The controller 1 can be implemented by a state machine (not shown). In yet another specific embodiment, the controller 100 can be implemented within the host. Logical and physical block structure FIG. 2 is in accordance with the present invention. A memory of a preferred embodiment is organized into a plurality of physical segment groups (or relay blocks) and managed by a controller of the controller. Organized into a number of relay blocks, each of which is a group of relay blocks The physical segment erased together is 98704.doc -18- 1288328 S〇···, Sn-i. The host 10 can access the 5 memory 20 执行 when executing the application under the file system or the operating system. The host will determine the data in units of logical segments, such as Gans, ,, 八, for example, each segment can contain 512 bytes of data. Also, the host through $ will also be in logical clusters. Read or write to the memory system, each logical cluster consists of one or more logical segments. In some host systems, there may be a selective host-side memory manager to execute the lower-order memory of the host In most of the examples, during a read or write operation, the host 10 essentially issues an instruction to the memory system 20 to fetch or write a data logical segment containing a string of consecutive addresses. The program: the memory-side memory manager is implemented in the memory system 2, and the storage and operation host is managed in a plurality of relay blocks of the flash memory 200. Data of the logical section. In this preferred implementation In the example, the memory manager includes a plurality of software modules for managing erase jobs, read jobs, and write jobs of the relay blocks. The memory manager also plays the flash memory. The system control and directory information related to the maintenance and operation of the body 2 (8) and the controller read 130. A schematic diagram of a mapping between a logical group and a relay block in a preferred embodiment. The μ(four)t^block has a physical segment 'used for storage—the logical group data of the logical group. Figure 3Α(1) shows the data from the logical group LGI, wherein the logical segments present a continuous logical sequence The 资料, 卜..., - shows are stored in the same logical order in the 98704.doc -19· 1288328. The same data in the block is the so-called "sequential". "Non-sequential" or Γ of data stored in different orders. When stored in this manner, the relay block is generally such that the relay block may have, in this case, the relay block is so confusing. There will be a displacement between the L-group, the lower address, and the lowest address of the mapped relay block. At this point, the logical sector address will wrap around to the top of the bottom of the logical group in the relay block. For example, in Figure 3 (4), the relay block will be in its first data from the logical segment ^

Store in one location. When the last logical segment Ν·1 is reached, the relay block wraps around to the segment 〇, and finally stores the data associated with the logical segment ^ in its last physical segment. In a preferred embodiment, the page mark is used to know, the displacement 'example &', to identify the starting logical sector address of the data stored in the first physical segment of the relay block. #两块块 differs only one solid page is dry. In the meantime, the two blocks are considered to store their logical segments in the same order.

Figure 3Β is a schematic diagram of the mapping between a plurality of logical groups and a plurality of relay blocks. Each logical group is mapped to a _-only relay ghost. Except for a few logical groups where the data is being updated. After a group of k, and after being updated, it may be mapped to a different relay zone. The ghost can maintain the mapping in a set of logical pair entities, which will be described in detail later. Other types of logical group to relay block mapping relationships are also considered. For example, the United States patent application filed by Alan Sinclair on the same day as the present invention, entitled "Adaptive Metabl〇cks" 98704.doc -20- 1288328, is not variable. The size of the relay block. The entire disclosure of this co-pending application is incorporated herein by reference. One feature of the present invention is that the system operates in a single logical split, and the logical segment groups in the entire logical address range of the memory system are processed in the same manner. For example, a section containing system data and a section containing user data can be distributed anywhere in the logical address space. Unlike prior art systems, there is no special segmentation or partitioning of system sections (ie, sections of file configuration table directories or subdirectories) to localize logic that may contain updated data for high and small sizes. In the address space section. Rather, the scheme for updating the logical group of segments is effectively handled as a typical access mode typical of the system segment and typical for archival material. Figure 4 shows the alignment of the structure in the relay block and the physical memory. Flash memory contains blocks of memory cells that can be erased together as a single unit. This erase block is the smallest erase unit of the flash memory or the smallest erasable unit (MEU) of the memory. The minimum erase unit is the hardware design parameter of the memory. However, in some memory systems that support multiple MEU erases, a "super MEU" containing more than one MEU can be set. For flash EEPROM, a MEU can contain one segment, but preferably includes multiple segments. In the example shown, it has one section. In a preferred embodiment, each segment may store 5 12-bit data and have a user data portion and a header portion for storing system or additional item data. If the relay block is composed of one MEU and each MEU contains one segment, each relay block will have N = Ρ * 区段 segments. At the system level, the relay block represents a group of memory locations, for example, 98704.doc -21 - 1288328 (erased area slave. Flash memory entity address a group of relay blocks, of which Following e θ θ # Β « is processed into π... "small erase unit. In this copy, relay block" and "block" are synonymous with words, used to manage media at the system level. Minimize the unit, and: "bit" or "delete" is used to indicate the minimum number of minimum flashes of the flash memory to minimize the stylized speed and erase. Speed, as far as possible, use the parallel method 'by configuring multiple page information to be parallelized (located in multiple MEUs)' and configuring multiple defects to be erased in parallel. In flash memory, a page is a group of memory cells that can be programmed together in a single operation... a page can contain - or multiple segments. Also, the memory array can be divided into more than one plane, where only one MEU in a plane can be programmed or erased at a time. Finally, the planes can be distributed in one or more memory chips. In flash memory, a MEU can contain one or more pages. Several MEUs within a flash memory wafer can be organized in a plane. Since one MEU of each plane can be programmed or erased at the same time, it is advantageous to select one MEU from each plane to form a plurality of MEU relay blocks (see Figure 5B below). Figure 5A shows a relay block formed by a minimum erasing unit that connects different planes. Each of the relay blocks (e.g., MB0, MB 1, ...) is constructed of a plurality of MEUs in different planes of the memory system, wherein different planes may be distributed in one or more of the wafers. The relay block link manager 170 shown in Fig. 2 can manage the link of the MEUs of the respective relay blocks. If one of the MEUs does not fail, each relay block is set during the initial 98704.doc -22- 1288328 formatter and retains its constituent JVIEU throughout the life of the system. Figure 5B shows a specific embodiment of selecting a minimum erase unit (meu) from each plane to join into a relay block. Figure 5C shows another embodiment in which more than one MEu is selected from each plane to join into a relay block. In another embodiment, more than one MEU can be selected from each plane to form a super. For example, a super MEU might be composed of two MEUs, for example. At this point, the above encoding process is taken once for a read or write operation. _ A co-pending and co-owned US patent application filed by Carlos Gonzales et al. on the same day as the present invention, entitled "

Deterministic Grouping 〇f Blocks into Multi-Block

Structures also reveals that multiple MEUs are linked and reconnected into relay blocks. The entire disclosure of this co-pending application is incorporated herein by reference. Trunk Block Management Figure 6 shows the Unintentional Blocks® of the Relay Block Management System implemented in the controller and flash memory. The middle block management system includes various functional modules implemented in the controller (10), and is transferred to various control data (including ^) in the form and the list of the flash memory 20 and the controller RAM 130. Directory information). The functional modules implemented in the controller (10) include an interface module, a logical entity address translation module 140, an update block manager module 150, and an erase block manager module 16 The relay block link manager 170. . 98704.doc • 23- 1288328 w-plane 110 allows the relay block management system to interface with the host system. The logical-to-real address translation module 14 maps the logical address of the host to the physical memory location. The update block manager module 150 manages the feed update operation for a given data logical group in the memory. The erased block manager (10) manages the erase operation of the relay block and its configuration for storing new information. The relay block link manager 170 manages the links of the sub-groups of the smallest erasable block of the segment to form a relay block for the cell. These modules will be explained in detail in their individual paragraphs. During the operation, the relay block management system generates and works with control data such as address, control and status information. Since many control materials tend to be small materials that are frequently changed, it is not possible to store and maintain flash memory towels having a large block structure at any time. In order to compare static control data in non-volatile flash memory, and to find a small number of relatively variable control data in the controller RAM for more efficient update and access, hierarchical and Decentralized solution. In the event of a power outage or failure, this scheme allows scanning of a small group of control data in non-volatile memory to quickly rebuild control data in the volatile controller RAM. This is possible because the present invention limits the number of blocks associated with a given logical group, and the > In this way, scanning can be limited. In addition, some of the control data that needs to be persistent is stored in the non-volatile relay block updated by the section, where each update will replace the new section of the previous section. The control data uses the segment indexing scheme to record updates by segment in the relay block. The non-volatile flash memory 200 stores a large amount of relatively static control data. This includes: Group Address Table (GAT) 210, chaotic block Suobeibei 98704.doc • 24· 1288328 (CBI) 220, erased block list (EBL) 23〇 and mAP 24〇. Gat 210 can record the mapping between logical groups of segments and their corresponding relay blocks. These mappings will not change unless updated. The CBI 220 can record the mapping of logically non-sequential segments during the update. EBl 230 can record the pool of relay blocks that have been erased. MAp 24〇 is a bit map showing the erase status of all the relay blocks in the flash memory. The volatile controller RAM 130 stores a small portion of the control data that is frequently changed and accessed. This includes a configuration block list (A]BL) 134 and a clear block list (CBL) 136. The ABL 134 can record the configuration of the relay block for recording updated data' while the CBL 136 can record the deconfigured and erased relay blocks. In the preferred embodiment, RAM 130 can be used as a cache memory for control data stored in flash memory 200. Update Block Manager The Update Block Manager 150 (shown in Figure 2) handles the updating of logical groups. In accordance with an aspect of the invention, each logical group of segments for updating is configured to record a dedicated update relay block for updating data. In a preferred embodiment, any block of one or more of the logical groups will be recorded in the update block. Update blocks can be managed to receive updated data in sequential or non-sequential (also known as "chaotic") order. The chaotic update block allows the section data to be updated in any order within the logical group, and individual sections can be arbitrarily repeated. In particular, it is not necessary to reconfigure any of the data sections, and the sequential update block can become a chaotic update block. Chaotic data updates do not require any predetermined block configuration; unscheduled writes of any logical address can be automatically incorporated. Therefore, unlike prior art systems, which differ from prior art systems, it is not necessary for 98704.doc -25 - 1288328 to specifically address whether each update block of the logical group is logically sequential or non-sequential. The general update block is only used to record various blocks in the order requested by the host. For example, even if the host, system data, or system control data tends to be updated in a chaotic manner, it is not necessary to process the logical address space corresponding to the host system data in a different manner than the host user data. Preferably, the data of the complete logical group of the segments is stored in a single relay block in a logical sequential order. In this way, the index of the stored logical section can be predefined. When a relay block stores all segments of a given logical group in a predetermined order, it can be said to be complete. As for the update block, when it finally fills the update data in a logically sequential order, the update block becomes an updated full relay block that can replace the original relay block at any time. On the other hand, 'If the update block fills up the update data in a different order from the logical and complete blocks', the update block is a non-sequential or chaotic update block, then the sequenced blocks must be further processed so that the sum can be finally pressed. The entire block is in the same order to store the updated data of the logical group. In the preferred embodiment, it is in a logically sequential order in a single relay block. Further processing involves summarizing the updated segments in the update block and the unchanged regions in the original block to yet another update relay block. The summarized update blocks will then be in a logically sequential order and can be used to replace the original block. Under some predetermined conditions, there will be one or more compression procedures before the summary program. The compression program simply re-records the segments of the chaotic update block into alternate flush update blocks, while removing any duplicate logical segments that have been eliminated by subsequent updates of the same logical segment. The update scheme allows multiple executions of up to a predetermined maximum value to be executed simultaneously. 98704.doc -26- !288328 Thread. Each thread is a logical group that is updated with its dedicated update relay block. Update of the order data When the data belonging to the logical group is updated first, the relay block and the update block of the update data which is dedicated to the logical group are configured. When an instruction to write a block of one or more segments of a logical group is received from the host (the existing relay block has stored all the full extents), the update block is configured. For the first host write operation, the data of the first block is recorded on the update block. Since each host write is a block with one or more consecutive logical addresses, the first update is followed by the feature for the first update. In subsequent host writes, the update blocks in the same logical group are recorded in the update block in the order received from the host. A block continues to be managed as a sequential update block, while the segments updated by the host within the associated logical group remain logically sequential. All segments updated in this logical group are written to this sequential update block until the block is closed or converted to a fuzzy update block. Figure 7A shows an example of a segment written in a logical group of sequential update blocks in sequential order due to the host write operation of the two branches, and the original block of the logical group & The corresponding section in the middle becomes obsolete. In the host write operation:], the logical segment LS5_LS_ is updated. The data updated to (3) will be recorded in the newly configured dedicated update block. For convenience, the logical update group will be updated in the private update block of the first-physical segment location. : The first logical section recorded in the new is not necessarily the group and the 5 'to be more, the science - section. Therefore, 98704.doc -27- 1288328 is between the starting point of the logical group and the starting point of the updated block. There will be displacement. This bit shift is referred to as a "page mark" as previously described in connection with Figure 3A. Subsequent segments will be updated in a logically sequential order. When the last segment of the logical group is written, the group address wraps around and the write sequence continues from the first segment of the group. In master write operation #2, the program segment of the data in logical segment LS9_LS12 is updated. The data updated to LS9, -LS12, will be recorded in the dedicated update block directly in the position after the end of the last write. The figure shows that two hosts are written as follows: The update data in the update block, ie LS5'_LS 12, is recorded in a logically sequential order. The update block can be thought of as a sequential update block because it has been filled in a logically sequential order. The updated data recorded in the update block can be used to eliminate the corresponding data in the original block. Chaotic Data Update When any of the sections updated by the host within the associated logical group are logically non-sequential, the chaotic update block management can be initiated for the existing sequential update block. This random update block is in the form of a data update block in which logical segments within the associated logical group can be updated in any order and can be repeated any number of times. It can be established by converting the sequential update block to the previously written segment within the updated logical group when the segment written by the host is logically out of order. All subsequent segments updated in this logical group are written to the next available segment location in the chaotic update block, regardless of its logical segment address within the cluster. Figure 7B shows an example of a section of a logical group that writes a chaotic update block in a chaotic order due to five separate host write operations, while the logical group 98704.doc -28- 1288328 is replaced in the original block. The segments that are copied and the segments that are copied in the chaotic update block become obsolete. In host write operation #1, the logical segments LS10-LS11 of the given logical group stored in the original relay block are updated. Updated Logs: Segments LS10, -LS11 are stored in the newly configured update block. At this point, the update block is a sequential update block. In the host write operation #2, the logical extents LS5-LS6 are updated to LS5'-LS6' and recorded in the update block immediately after the last write. This converts sequential update blocks into confusing update blocks. At the host write operation #3, the logical section LS10 is updated again and recorded in the next position of the update block to become LSI0". At this time, the LSI0" in the update block can replace the LSI0' in the previous record, and the LSI0' can replace the LS10 in the original block. In the host write operation #4, the data of the logical segment LS10 is updated again. Record it in the next location of the update block to become LSI 0'''. Therefore, LS10," is now the last and only valid material of logical segment LS10. It will be updated in host write operation #5. The data of the logical segment LS30 and its record in the update block become LS 3 01. Therefore, this example shows that a plurality of logical segments in a logical group can be written into a chaos in any order and any repetition. Update block. Forced sequential update Figure 8 shows an example of writing a segment of a sequential update block in a logical group in sequential order due to two separate host write operations with interrupts at the logical address. In #1, the update data of the logical segment LS5-LS8 is recorded in the dedicated update block to become LS5'-LS8'. In the host write #2, the update data of the logical segment LS14-LS16 is recorded. Recorded after the last write 98 The update block of 704.doc -29- 1288328 becomes LS14, -LS16, however, there is an address jump between LS8 and LS14, and the host write #2 usually makes the update block non-sequential. The address jump is not reported. One option is to copy the data of the middle section of the original block to the update block before executing the host write #2 to perform the padding operation (#2A). In this way, it can be saved. Update the sequential nature of the block.Figure 9 shows a flow diagram of a program for updating the information of a logical group by the update block manager in accordance with a general embodiment of the present invention. The update process comprises the following steps: Step 260: The memory is organized a plurality of blocks, each block being divided into a plurality of memory cells that can be erased together, each memory cell being used to store data of a logical unit. Step 262: The data is organized into a plurality of blocks Logical group, each logical group is divided into a plurality of logical units. Step 264: In the standard example, according to the first specified order, preferably

Logically (4), all the logical units of the logical group (4) are stored in the memory unit of the original block. In this way, the index of the individual logical units in the access block can be known. Step 270: For the data of a given logical group (eg, LGx), please # logical unit within the new LGX. (The logical unit update is an example. In one case, the update will be grouped by LGx- or multiple consecutive logical units.) 'Step 272: The requested update logic unit will be stored in dedicated to record LGX Updated in the second block. The order of recording is based on the second order, usually 98704.doc -30- 1288328 is the order of the update request. One feature of the present invention allows for the initial setting of data to be recorded in a logically sequential or chaotic sequence as a general update block. Therefore, according to the second order, the second block may be a sequential update block or a chaotic update block. Step 274: When the program loop returns to step 27, the second block continues to record the requested logical unit. The second block will be closed when the closed predetermined condition is formed to receive further updates. At this point, the process proceeds to step 276. Step 276: Determine whether the closed second block records its update logical unit in the same order as the original block. When the two block record logical units differ by only one page mark, the two blocks are considered to have the same order' as described in connection with Figure 3A. If the two blocks have the same order, the program proceeds to step 2 80, otherwise, the obsolete item collection must be performed in step 2900. Step 280. Since the second block has the same order as the first block, it can be used to replace the original first block. The update process then ends at step 299. Step 290: Collect the latest version of each logical unit of the logical group from the second block (update block) and the first block (original block). The summarized logical units of a given logical group are then written to the third block in the same order as the first block. Step 292: Since the third block (summary block) has the same order as the first block, it can be used to replace the original first block. The update process then ends at step 299. 98704.doc -31 - 1288328 Step 299: When the end program establishes a complete update block, the block becomes a new standard block for a given logical group. The update thread for this logical group will be terminated. Figure 10 is a flow diagram showing the flow of updating the data of a logical group by the update block manager in accordance with a preferred embodiment of the present invention. The update procedure includes the following steps: Step 310: For a given logical group (e.g., 'LGx) profile, a request is made to update the logical segment within the LGX. (The zone update is an example. In general, the update will be a program segment consisting of LGX- or multiple consecutive logical segments.) Step 312: If the LGx-specific update block does not yet exist, proceed Go to step 41 to start a new update thread for the logical group. This can be done by configuring an update block dedicated to the update data of the record logical group. If there is already an updated update block, proceed to step 3-14 to begin recording the update segment onto the update block. Step 314·· If the current update block is already confusing (ie, non-sequential), proceed directly to (4) 51G, and X records the more (4) segment of the request to the chaos. If the current update block is sequential, proceed to the step. 316, to process the blocks in order. Step (10) The feature of the present invention is that the material is initially set to be arranged in a logically sequential or chaotic sequence to record the sequential storage: the sequence of the updated block will be logically sequenced. Therefore, I will teach you to follow the order as much as possible. In addition, when the block is closed-updated to 98704.doc -32 - 1288328 for further updates, less processing will be required as there is no need to collect waste items. Therefore, it is judged that the requested salary b π * follows the current sequential order of the update block. If the update is followed by #, proceed to step 5U) to perform the sequential update, and the update block will maintain the order. On the other hand, if the update is not followed (chaotic update), it will convert the sequential update block into a chaotic update block when no action is taken.

The block becomes a chaotic update block. Optional Forced Sequencing Procedure In a specific embodiment, no action is taken to save the situation' then the procedure proceeds directly to step 37G, where the update is allowed to be updated in another embodiment, which is selectively performed The force sequencer step 320' saves the sequential update blocks as much as possible due to the chaotic update of the suspension. There are two cases in which both cases need to copy the missing segments of the original block to maintain the sequential order of the logical segments recorded on the updated block. The first case is where the update can establish a short address jump. The second case is to end the update block early to keep it in order. The forced sequencer step 320 includes the following sub-steps: Step 330: If the update established logical address hop is not greater than the predetermined number CB, the program proceeds to the forced sequence update procedure of step 350, otherwise the program proceeds to step 340 to Consider whether it is suitable for forced completion. Step 340: If the number of unfilled physical segments exceeds a predetermined design parameter Cc (the representative value is half of the updated block size), the update block is phase 98704.doc -33- 1288328 pairs are not used, so no Will close early. The process proceeds to step 370' and the update block becomes confusing. On the other hand, if the update block has been substantially filled, it is considered to have been fully utilized, so the process proceeds to step 36 to end the forced sequence. Step 350: Force the sequential update to allow the current sequential update block to maintain the sequence as long as the address jump does not exceed the predetermined number Cb. Essentially, the section of the associated original block of the update block is copied to fill the gap spanned by the address jump. Therefore, before proceeding to step 5 10, the block is updated sequentially with the information of the intermediate address to sequentially record the current update. Step 360: If the current sequential update block has been substantially filled, rather than being converted to a chaotic update block by the suspended mess update, then the forced sequence end allows the current sequential update block to be closed. A chaotic or non-sequential update definition is an update with the following items: no forward address transitions, reverse address transitions, or address repetitions covered by the above address hop exceptions. In order to prevent the sequential update block from being converted for a chaotic update, the unwritten segment position of the update block is filled by copying the sector of the original partial demise block of the associated block. Then completely eliminate and erase the original block. Now, the current update block has a complete set of logical segments and then ends up as a complete relay block that replaces the original relay block. The program then proceeds to step 430 to configure the update block at its location to accept the record of the pending segment update requested in step 31. Convert to chaotic update block

Step 370: When the suspended update is not in the sequential order and may or may not be available, if the forced sequence condition cannot be met, then the program is continued to the step 5 1 Q 98704.doc -34 - 1288328 by allowing the update A suspended update section with a non-sequential address is recorded on the block to allow the sequential update block to be converted into a chaotic update block. If the maximum number of chaotic update blocks are present, the chaotic update block that has not been accessed for the longest time must be closed before allowing the conversion to proceed; thus, the maximum number of chaotic blocks will not be exceeded. The identification of the oldest unaccessed chaotic update block is the same as the general example described in step 420, but is limited to the chaotic update block. At this point, closing the chaotic update block can be achieved by summarizing as described in step 550. Configuring a New Update Block Restricted by the System Step 410: The procedure for configuring the erase relay block to update the block begins with determining whether the predetermined system limit is exceeded. Due to limited resources, the memory management system typically allows a predetermined maximum number cA of update blocks that can exist simultaneously. This limit is the total number of sequential update blocks and chaotic update blocks, and is also a design parameter. In a preferred embodiment, this limit is, for example, a maximum of 8 update blocks. Also, due to the high demand for system resources, there is a corresponding predetermined limit (e.g., 4) on the maximum number of hybrid update blocks that can be simultaneously turned on. Therefore, when the CA update blocks have been configured, the next configuration request can be satisfied only after one of the existing configuration requests is closed. The process continues to step 420. When the number of update blocks opened is less than Ca, the program proceeds directly to step 430. Step 420: When the maximum number Ca of update blocks is exceeded, the update block that has not been accessed for the longest time is closed and the collection of the discarded items is performed. The oldest unaccessed update block is identified as the update block associated with the longest unaccessed logical block. In order to determine the block that has not been accessed for the longest time, access includes writes and selective reads of logical sections. The 98704.doc -35- 1288328 list of update blocks is maintained in the order of access; no initialization sequence is assumed during initialization. When the update block is sequential, the same procedure as described in connection with step 36 and step 53 will be followed. When the update block is garbled, the same private sequence as described in conjunction with step 54 will be used. This close removes the space to configure a new update block in step 43. Step 43 0. Configuring a new relay block as the update block dedicated to the given logical group lgx can satisfy the configuration requirement. The program then proceeds to step 510. Recording the update data on the update block Step 510: Record the requested update zone on the next available physical location of the update block. The program then proceeds to step 52 and determines if the update block is ready to end. Update Block End Step 520: If the update block still has space to accept additional updates, then proceed to step 522. Otherwise proceed to step 57 to end the update block. When a write request of a destination request is written to a logical section that is more than all of the space of the block, there are two possible embodiments for filling up the update block. In the first embodiment, the write request is divided into two parts, wherein the first part can be written up to the last physical section of the block. The block is then closed and the second portion of the write is processed as the next requested write. In another embodiment, the requested write is retained while the block fills the remaining segments and then closed. The requested write is processed as a write to the next request. Step 522 · If the update block is sequential, proceed to step 53 〇 to perform a sequential shutdown. If the update block is confusing, proceed to step 98704.doc -36 - 1288328 step 540 for a messy shutdown. Sequential Update Block End Step 530·· Since the update block is sequential and completely filled, the logical group stored therein is complete. The relay block is complete and can replace the original relay block. At this point, the original block will be completely eliminated and erased. The program then proceeds to step 570 where the update thread for the given logical group ends. Chaotic Update Block End Step 540 • Since the update block is non-sequentially populated, it may contain multiple updates of some logical segments, so a waste project collection is performed to save valid data. The chaotic update block can be compressed or summarized. At step 542, the program to be executed will be determined. Step 542: The compression or aggregation to be performed will depend on the degradation of the update block. If a logical segment has been updated multiple times, its logical address will be highly degraded. Multiple versions of the same logical section will be recorded on the update block, and the last 5 recorded version will be a valid version of the logical section. In an update block with multiple versions of logical segments, the number of distinct logical segments will be much less than for logical groups. In a preferred embodiment, when the number of distinct logical segments in the update block exceeds a predetermined design parameter CD (which represents a half of the logical group size), the end program performs a summary at step 550. Otherwise the program will proceed to the compression of step 560. Step 550: If the chaotic update block is to be summarized, the original block and the updated block will be replaced by a new standard relay block containing the total packet data. After & 98704.doc -37- 1288328, the update thread will end at step 570. Step 560: If the chaotic update block is to be compressed, it will be replaced with a new update block containing the compressed data. After compression, the processing of the compressed update block will end at step 507. Alternatively, compression may be delayed until the update block is written again' thus eliminating the possibility of a summary without intermediate updates after compression. Then 'when the next request in step 502 occurs to update in lGx', a new update block is used in the further update of the given logical block. Step 570: When the end program establishes a complete update block, the block becomes a new standard block for a given logical group. The update thread for this logical group will be terminated. When the end of the program builds a new update block that replaces the existing update block, the new update block is used to record the next update requested for the given logical group. When the update block has not ended, processing will continue when the next request in the LGX is updated in step 31. As can be seen from the above procedure, when the chaotic update block is closed, the updated data recorded thereon is further processed. In particular, the collection of obsolete items of valid data is performed by the following procedure: a program compressed to another chaotic block, or a summary of the original blocks associated with it to form a new standard sequential block. Fig. 11A is a detailed view showing the summary of the private sequence of the chaotic update block shown in Fig. 1A. '/Centre update area soil bundle summary {executed when the I update block (such as § update block has filled the last physical segment location of its write): a possible program -. The number of logical segments that are distinguished by the number of people written in the block will be summarized when the pre-existing 5 juice parameter CD is exceeded. The summary private sequence step 5 5 图 shown in Figure i 〇 contains the following sub-steps: v Step 5 5 1 · When this random update block is closed, a new relay zone with 98704.doc -38 - 1288328 may be configured instead Piece. Step 552: Collect the latest version of each logical segment and ignore all the eliminated segments in the chaotic update block and the associated original block. Step 554 · Record the collected valid segments in a logical sequential order on the new relay block to form a complete block, that is, blocks of all logical segments of the logical group recorded in sequential order . Step 5 5 6 : Replace the original block with a new complete block. Step 558: Erasing the updated block and the original block. Figure 11B is a flow chart showing in detail the compression procedure for closing the chaotic update block shown in Figure 1A. Compression is selected when the number of logical segments that are written in the block is lower than the predetermined design parameter CD. The compression program step 560 shown in Figure 1A includes the following sub-steps: Step 561: When the chaotic update block is compressed, a new relay block is replaced. Step 562 · Collect the latest version of each logical section in the existing chaotic update block to be compressed. Step 564: Record the collected segments on the new update block to form a new update block with the compressed segments. Step 566 - Replace the existing update block with a new update block with a compressed section. Step 568: Erasing the updated block that has ended. Logic and Relay Block Status Figure 12A shows all possible states of a logical group and their possible transitions under various operations. 98704.doc 1288328 Figure 12B is a table listing the possible states of a logical group. The logical group status is defined as follows: 1 · A # : All logical segments in the logical group have been written into a single relay block in a logical sequential order, which may utilize page mark winding mode. 2. Table Respect 8: No logical segments have been written in the logical group. The logical group is marked in the group address table as a successor block that is not written and has no configuration. Returns a predetermined data pattern in response to a host read for each segment in this group. 3.·豸豸舞: Some sections in the logical group have been written into the relay block in a logically sequential order, possibly using page markers, so it can replace the corresponding logic of any previous complete state in the group. Section. 4. Must dance: Some sections in the logical group have been written in the human relay block in a logically non-sequential order, possibly using page markers, so it can replace the corresponding complete state of the group towel. Logical section. The sections in the group address can be written more than once - and the latest version will replace all previous versions too. Figure 13A shows all possible states of a relay block, and the possible transitions between them. Figure 13B below shows all possible states of the relay block, and the possible transitions between them: Stay L (10) Xu: All the segments in the relay block have been erased. = Sequence (9): The relay block has been partially written, and its segments are in a logical sequence, possibly using page markers. All sections belong to the same 98704.doc 1288328 logical group. 3. Mannong ^ Ben · The relay block has been partially or completely written, and its segments are in a logical non-sequential order. Any section can be written more than once. All sections belong to the same logical group. 4. End #: The relay block has been completely written in the logical sequential order, possibly using page markup. The original known block was previously complete but at least one segment has been phased out due to host material updates. Figure 14(A)_14(J) is a state diagram showing the various operational effects on the logical group status and on the physical relay block. Figure H(A) shows a state diagram corresponding to the logical grouping of the first write operation and the transition of the relay block. The host writes one or more segments of the previously unwritten patch group to the newly configured erased block in a logically sequential order. The logical group and the relay block enter the sequential update state. The graph μ(β) does not correspond to the logical group of the first complete operation and the ghost map of the relay zone. The sequential update logical group that was not previously written becomes complete due to the host = sequential write to all sections. If the memory card fills the remaining unwritten segments with a predetermined data pattern to fill the group, the transition will also occur. The relay block becomes complete. Fig. 14(c) shows that the logical group of the first chaotic operation and the relay area ▲ turn 4 are sad. A previously updated sequence of sequential update logic becomes confusing when the host writes at least one segment out of sequence. Figure 14 (D) shows a state diagram corresponding to the logical grouping of the first compression operation and the transition of the relay block. Copy the previously unwritten chaotic update logic 987〇4.d (all active sections in the -41 - 1288328 group to the new chaotic relay block' from the old block and then erase it. Figure 14 (E) displaying a logical group corresponding to the first summary operation and a state diagram of the middle 'block transition. Moving all valid segments in the previously unwritten chaotic update logical group from the old chaotic block to press The newly configured erased block is logically filled sequentially. The sectors that are not written by the host are filled in a predetermined data pattern. Then the old chaotic block is erased. Figure 14(F) shows the corresponding write State diagram of the logical grouping of operations and the transition of the relay block. The host writes one or more segments of the complete logical group to the newly configured erased relay block in a logical sequential order. Logical group and The relay block becomes a sequential update state. The previous complete relay block becomes the original relay block. Figure 14(G) shows the state diagram corresponding to the logical group and relay block transition of the sequential padding operation. Logical group when the host writes all its segments sequentially It becomes complete. This can also occur when the sequential update logical group is filled with the valid section of the original block to make it complete during the collection of discarded items, after which the original block is erased. Figure 14(H) shows the corresponding State diagram of logical group and relay block transitions for non-sequential write operations. The sequential update logical group becomes confusing when the host writes at least one segment non-sequentially. Unsequential segment writes may result in updated blocks or The valid segment corresponding to the original block becomes obsolete. Figure 14(1) shows the state diagram corresponding to the logical group and relay block transition of the compression operation. From the old block, all the validities in the chaotic update logical group are valid. The segment is copied to the new chaotic relay block and then erased. The original block 98704.doc -42- 1288328 will not be affected. Figure 14(J) shows the logical group and medium corresponding to the summary operation. Following the state diagram of the block transition. Copy all the valid segments in the chaotic update logical group from the old chaotic block to fill the newly configured erased blocks in a logically sequential order. Then erase the old chaotic area. Block and original block. Update Block Tracking and Management Figure 15 shows a preferred embodiment of the structure of an Configuration Block List (ABL) for tracking open and closed update blocks and erased blocks for configuration. Block list (ABL) 6 10 will be stored in controller RAM 130 to allow management of erased block configurations, configured update blocks, associated blocks, and control structures to enable proper logical pair entities. Address translation. In a preferred embodiment, the ABL includes: a list of erased blocks, an open update block list 614, and a closed update block list 616. The open update block list 614 is in the ABL. A block project group having the attribute of opening the update block. The opened update block list has one item of each data update block currently open. Each item retains the following information. LG is the logical group address dedicated to updating the relay block. Sequential/chaotic is the state in which the update block is populated with sequential or mixed IL update data. MB is the relay block address of the update block. The page mark is the starting logical section of the record at the first physical location of the update block. The segment number written represents the segment number currently written on the update block. MB 〇 is the relay block address of the associated original block. Page TagG is the page mark of the original block associated with it. The closed update block list 616 is a subset of the configuration block list (Abl). 98704.doc -43- 1288328 This is the block project group in abl with the properties of the closed update block. The closed update block list has an item for each data update block that has been closed, but its items are not updated in the logical pair main entity directory. Each item retains the following information. LG is the logical group address dedicated to the current update block. Mb is the relay block address of the update block. The page mark is the starting logical section of the first-physical location record in the update block. MB. Is the relay block address of the original block associated with it. Chaotic Block Index The Sequential Update Block has data stored in a logically sequential order, so it is easy to find any logical section in the block. A chaotic update block has logical segments that are not stored in order and can store multiple update generations of one logical segment. Additional information must be maintained to record where each valid logical segment is placed in the chaotic update block. In a preferred embodiment, the chaotic block index data structure allows for tracking and fast access to all active segments in the chaotic block. The chaotic block index is independent of the logical address space of the small area and can effectively handle the hotspots of system data and user data. The index data structure essentially allows index information with infrequent update requirements to be maintained in the flash memory to avoid significant impact on performance. On the other hand, the list of recently written segments in the chaotic block is retained in the chaotic section list of controller Ram. Also, the cache memory of the index information of the flash memory is retained in the controller RAM to reduce the number of flash sector accesses for address translation. The index of each chaotic block is stored in the chaotic block index (CBI) section of the flash memory. Figure 16A shows the data field of the chaotic block index ((:] 31) section. The chaotic area 98704.doc -44 - 1288328 The block index section (CBI section) contains the sections in the logical group mapped to the mix索引 Updating the index of the block, the position of each segment of the logical group in the chaotic update block or its associated original block may be defined. The CBI segment includes a chaotic block index of the effective segment in the recorded chaotic block. Blocking, recording the chaotic block information field of the chaotic block address parameter, and recording the segment index field of the valid CBI section in the relay block (CBI block) storing the CBI section. Figure 16B shows the record An example of a chaotic block index (CBI) section in a dedicated relay block. A dedicated relay block may be referred to as a CBI block 620. When the CBI section is updated, it is written to the CBI block 620. The next available physical segment location. Therefore, multiple copies of the CBI segment can exist in the CBI block, with only the last written copy being valid. For example, the logical group LGi has been utilized with the latest version of the valid version. The CBI section is updated three times. The last written CBI section in the block The group index can identify the location of each valid segment in the CBI block. In this example, the last written CBI segment in the block is the CBI segment of LG^6, and its index group is substituted for all previous index groups. A valid index group. When the CBI block finally becomes fully populated with a CBI segment, 'all valid segments are rewritten to the new block location to compress the block during the control write operation. Then the entire region is erased The chaotic block index field in the CBI section contains an index item of each logical section within the logical group or a subgroup mapped to the chaotic update block. Each index item represents the valid data of the corresponding logical section. Chaos updates the displacement within the block. The reserved index value represents the valid data in the chaotic update block without the logical segment 'and the corresponding segment in the original block representing the association is valid. Some chaotic block index blocking items The cache memory is retained in the controller RAM of 98704.doc 1288328. The chaotic block information block in the CBI section contains an item about each chaotic update block present in the system to record the block. Address parameter information. The information in this field is only valid in the last written segment of the CBI block. This information will also appear in the data structure of the RAM. The items of each chaotic update block include three address parameters. The first parameter is the logical address of the logical group (or logical group number) associated with the chaotic update block. The second parameter is the relay block address of the mixed IL update block. The third parameter Is the physical address offset of the last segment written in the chaotic update block. The displacement information sets the scan start point of the chaotic update block during initialization to reconstruct the data structure in the RAM. The segment index field contains information about each of the CBI blocks. A project of a valid CBI section that defines the displacement of the most recently written CBI section within the CBI block for each of the licensed chaotic update blocks. The reserved value of the displacement in the index represents that the licensed chaotic update block does not exist. Figure 16C is a flow diagram showing the access to data for a logical segment of a given logical group that is undergoing a chaotic update. During the update process, the update data is recorded in the chaotic update block, while the unaltered data is left in the original relay block associated with the logical group. The procedure for accessing the logical section of a logical group under a chaotic update is as follows: Step 650: Start looking for a given logical section of a given logical group. Step 652: Find the last written CBI section in the CBI block. Step 654: Look for the chaotic update block or the original area 98704.doc -46 - 1288328 block associated with the given logical group by querying the chaotic block information block of the last written cbi section. This step can be performed any time before step 662. Step 658: If the last written CBI segment is directed to a given logical group, the CBI segment can be sought. Proceed to step 662. Otherwise, proceed to step 660. Step 660: Find the CBI section of the given logical group by querying the sector index field of the last written CBI section. Step 662: Find a chaotic block or a given logical segment in the original block by querying the chaotic block index field of the CBI section found. Figure 16D shows a flow diagram of accessing data for a logical segment of a given logical group that is undergoing a chaotic update, based on an alternative embodiment in which a logical group has been partitioned into subgroups. The limited capacity of the CBI segment can only record a predetermined maximum number of logical segments. When a logical group has more logical segments than a single CBI segment can handle, the logical group is split into a plurality of subgroups having CBI segments assigned to each subgroup. In one example, each CBI section has a capacity sufficient to track a logical group of up to 256 segments and up to 8 chaotic update blocks. If the logical group has a size greater than 256 segments, there are separate CBI segments for each 256 segment subgroup within the logical group. The CBI section can exist for up to 8 subgroups within a logical group to support logical groups up to 2048 segments. In a preferred embodiment, an indirect indexing scheme is employed to facilitate index management. Each item of the section index has direct and indirect blocking. The direct segment index defines the displacement within the CBI block for all possible C BI segments of a particular chaotic update block. The information in this shelving is only valid in the CBI section that was written last about the particular chaotic update block. In the index 98704.doc -47- 1288328 The reserved value of the displacement means that the CBI section does not exist because the corresponding logical subgroup of the chaotic update block does not exist or is not updated due to the configured update block. . The indirect section index may define the displacement within the CBI block in which the most recently written CBI section of each chaotic update block of the license is located. The reserved value of the displacement in the index represents that the licensed chaotic update block does not exist. Figure 16D shows the procedure for accessing the logical section of a logical group under a chaotic update, the steps of which are as follows: Step 670: Split each logical group into a plurality of subgroups and assign a cbi section to each subgroup. Step 6 8 0: Start looking for a given logical segment of a given subgroup of a given logical group. Step 682: Find the last written CBI section in the CBI block. Step 684: Find the chaotic update block or the original block associated with the given sub-group by querying the chaotic block information field of the last written CBI section. This step can be performed any time before step 6.9. Step 686: Proceed to step 691 if the last written CBI section is directed to a given logical group. Otherwise, proceed to step 690. Step 690: Indirect segment indexing by querying the last written CBI segment

A field that looks for the last written CBI section in multiple CBI sections of a given logical group. Step 69 1 : At least one CBI section associated with one of the subgroups of the given logical group has been found. carry on. Step 692: If the found CBI section points to a given subgroup, then 98704.doc 1288328 may look for a CBI section of the given subgroup. Proceed to step 696. Otherwise, proceed to step 694. Step 694: Find the CBI section of the given subgroup by querying the direct section index field of the CBI section currently being sought. Step 696: Find a chaotic block or a given logical segment in the original block by querying the chaotic block index field of the CBI section of the given subgroup. Figure 16E shows an example of a Chaotic Block Index (CBI) section and its functions in a specific embodiment in which each logical group is partitioned into a plurality of subgroups. The logical group 700 originally stores its complete data in the original relay block 7〇2. The logical group is then updated with the configuration-specific chaotic update block 704. In this example, logical grouping 700 is partitioned into subgroups, each of which has 256 segments. In order to find the i-th segment in subgroup B, the last written CBI segment in CBI block 620 is first looked for. The chaotic block information field of the last written CBI section can provide the address of the chaotic update block 704 looking for a given logical group. At the same time, it can also provide the location of the last segment written in the chaotic block. This information is useful when scanning and rebuilding indexes. If the last written CBI section result is one of the four CBI sections of a given logical group, it is further determined whether it is the CBI section of the given subgroup B containing the third logical section. If so, the chaotic block index of the cbi section will point to the location of the relay block storing the data of the next logical section. The segment location will be in the chaotic update block 704 or in the original block 702. If the last written CBI segment result is one of the four 98704.doc 1288328 CBI segments of the given logical group but not belong to Subgroup b will query its direct section index 'to find the CBI section of subgroup B. After looking for this exact CBI section *, the chaotic block index is queried to find the i-th logical section in the chaotic update block 704 and the original block 702. If the last written CBI section result is not one of the four CBI sections of a given logical group, the indirect section index is queried for one of the four sections. In the example shown in Figure 16E, the CBI section of subgroup c is looked for. This CBI section of subgroup C then queries its direct section index, _, to find the exact CBI section of subgroup B. This example shows that when querying a chaotic block index, it will find that the i th logical segment is unchanged and will find its valid data in the original block. The same considerations are also made when looking for the jth logical segment in a subgroup C of a given logical group. This example shows that the last written CBI section result is not any of the four CBI sections of a given logical group. Its indirect section index points to one of the four CBI sections of a given group. The last written result of the four pointed to is also the CBI section of subgroup C. When querying its chaotic block, it will find that the jth logical sector is found at the specified location in the chaotic update block 7〇4. There is a list of chaotic sections of the chaotic update blocks in the system in the controller RAM. Each list contains a record of the segments that were written into the chaotic update block from the beginning of the last updated CBI segment in the flash memory to the current segment. The number of logical sector addresses (which may remain in the chaotic section list) for a particular chaotic update block is a design parameter for a representative value of 8 to 16. The optimal size of the list determines the trade-off between the effect of the 98704.doc -50-1288328 degrees of consumption and the zone scan time during initialization. During system initialization, in order to identify the valid segments written since the previous update of one of its associated CBI segments, each chaotic update block must be scanned. In the controller RAM, a list of chaotic sections of each chaotic update block is formed. It is only necessary to scan each block in the CBI section that was last written, starting from the last sector address of the chaotic block in the chaotic block of each block. When a chaotic update block is configured, the CBI section is written to correspond to all of the update logical subgroups. The logical and physical addresses of the chaotic update block are written to the chaotic block information fields available in the segment, where the null value entries are in the chaotic block index block. A list of chaotic sections will be opened in the controller RAM. When the chaotic update block is closed, the CBI section is written with the block logic and physical address removed from the chaotic block information field in the section. The list of corresponding chaotic sections in RAM becomes unused. The list of chaotic sections corresponding to the controller RAM can be modified to include a record of the section written to the chaotic update block. When the chaotic section in the controller RAM does not write any free space recorded by other sections of the chaotic update block early, the updated CBI section is written for the logical subgroup of the section in the list, and then Clear the list. When CBI block 620 becomes full, the valid CBI section is copied into the configured erased block and the previous CBI block is erased. Address Table The logical-to-physical address translation module 140 shown in Figure 2 is responsible for associating the logical address of the host in the flash memory with the corresponding physical address. The mapping between logical groups and entity groups (relay blocks) is stored in non-volatile flash memory 98704.doc -51 - 1288328 200 and the more volatile RAM 13 0 (see Figure 1). A set of tables and lists that are distributed. The address list is maintained in flash memory containing the address of the relay block for each logical group in the memory system. In addition, the logical-to-physical address record of the most recently written section is temporarily retained in RAM. These volatile records can be reconstructed from the block list and the data section headers in the flash memory when the system is initialized after startup. Therefore, the address table in the flash memory only needs to be updated occasionally to reduce the percentage of over-utilization of the control data. The hierarchy of the address records of the logical group includes: a list of updated blocks opened in the RAM, a list of closed update blocks, and a group address table (GAT) maintained in the flash memory. The list of updated update blocks is a list of data update blocks currently open in the controller RAM for writing updated host segment data. The block's items are moved to the closed update block list when the block is closed. The closed update block list is a list of the data update blocks that have been closed in the controller RAM. The subset of the list (4) is moved to the section in the group address table while controlling the write operation period. The Group Address Table (GAT) is a list of the relay block addresses of all logical groups of host data in the memory system. The GAT contains - items for each logical group that are sequentially ordered according to logical addresses. The _th item in the GAT contains the relay block address of the logical group with the address η. In a preferred embodiment, the GAT is a representation in the flash memory - a component comprising a set of items having a relay block address defining each logical group in the memory system. (called the GAT section). In flash memory, the gat section is looked up in one or more 98704.doc -52 - 1288328 dedicated control blocks (called gat blocks). Figure 17A shows the data field of the Group Address Table (GAT) section. The GAT segment can have a capacity of a GAT project that is large enough to contain a set of 128 consecutive logical groups. Each G AT segment consists of two components, namely a set of GAT entries for the relay block addresses of each logical group in the range, and a GAT segment index. The first component contains information for finding a relay block associated with a logical address. The second component contains information for finding all valid GAT segments within the GAT block. Each GAT project has three fields, namely a relay block number, a page mark as previously described in connection with Figure 3 A(iii), and a flag indicating whether the relay block has been reconnected. The GAT section index lists the parts of the valid GAT section in the GAT block. This index will be replaced in each GAT segment but will be replaced by the version of the next GAT segment written in the GAT block. Therefore only the version in the last written GAT section is valid. Figure 17B shows an example of recording a group address table (GAT) section in one or more GAT blocks. The GAT block is a relay block dedicated to recording the GAT section. When the GAT segment is updated, it is written to the next available physical segment location in the GAT block 720. Thus, multiple copies of the GAT segment can exist in the GAT block, with only the last written copy being valid. For example, the gat section 25 5 (the metric containing the logical group LG3968 _ LG4 〇 98) has been updated at least twice with the latest version of the valid version. A set of indices of the last written gap segment in the block identifies the location of each valid segment in the GAT block. In this example, the last written GAT segment in the block is the GAT segment 236, and its index group is a valid index group that replaces all previous index groups. When the gat block finally becomes completely filled with the G AT segment, all valid segments are again written to 98704.doc -53 - 1288328 to the new block location to compress the block during the control write operation. Then erase the entire block. As described above, the G AT block contains items of a group of logically consecutive groups in the area of the logical address space. The GAT segments within the GAT block each contain 128 logically logical group mapping information for consecutive logical groups. Within the address range spanned by the G AT block, the number of GAT segments required to store all logical group items occupies only a small portion of the total segment location within the block. Therefore, the G AT segment can be written to the next available segment location in the block to update it. The index of all valid GAT segments and their locations in the GAT block is maintained in the index field in the most recently written G AT segment. A small portion of the total segment occupied by the active GAT segment in the G AT block is the system design parameter, which is typically 25%. However, there are up to 64 valid GAT segments in each GAT block. In systems with large logical capacity, it may be necessary to store G AT segments in more than one GAT block. At this time, each G AT block is associated with a fixed range logical group. The GAT update execution can be part of the control write operation, which is triggered when the ABL runs out of configured blocks (see Figure 18). Its execution is performed simultaneously with the abl fill and CBL clear operations. During the GAT update operation, a GAT zone has items that are updated with the corresponding items in the closed update block list. When the GAT project is updated, any corresponding items are removed from the closed update block list (cubl). For example, the GAT segment to be updated is selected based on the - item in the list of closed update blocks. The update section can be written to the next available section location in the G AT block. When no segment location is available for an updated GAT segment, 98704.doc • 54-1288328 gat rewrite operation occurs during control write operations. The new GAT block will be configured and the valid G AT segments defined by the GAT index will be copied sequentially from the complete GAT block. Then erase the entire GAT block. The GAT cache memory is a copy of the sub-divided items of the 128 items of the GAT segment in the controller ram 130. The number of GAT cache memory items is a system design parameter with a value of 32. Each time an item is read from the GAT section, the gat cache memory of the relevant section sub-segmentation can be established. Multiple GAT caches will be maintained. The number is a design parameter with a value of 4. GAT cache memory is overwritten based on items that have not been subdivided by different sections for the longest time. Erased Relay Block Management The erase block manager ι6〇 shown in Figure 2 can manage erased blocks using a list of maintained directory and system control information. These lists are distributed among the controller RAM 130 and the flash memory 200. When the erased relay block must be configured to store the user profile or the storage system control profile, the next available relay block number in the configuration block list (ABL) retained in the controller RAM is selected. (See Figure 15). Similarly, when the trunk block is removed and erased, its number is added to the clear block list (CBL) that also remains in the controller rAM. Relatively static catalog and system control data is stored in flash memory. These include a list of erased blocks and a bit map (MAP) that lists the erased states of all of the relay blocks in the flash memory. The erased block list and MAp are stored in individual segments and are recorded in a dedicated relay block called "MAP Block". These lists, which are distributed in the controller RAM and flash memory, provide the level of the erased blocks 98704.doc 1288328 to effectively manage the use of erased blocks. Figure 18 is a schematic block diagram showing the distribution and flow of control and directory information for the use and recycling of erased blocks. The control and directory data is maintained in a list that is retained in the controller ram 130 resident in the flash memory or in the MAP block 750. In the preferred embodiment, controller RAM 130 retains configuration block list (ABL) 610 and clear block list (Cbl) 740. The 'Configuration Block List (ABL) as previously described in connection with Figure 15 can record which relay block has been recently configured to store user data or storage system control data structures. When a new erased trunk block must be configured, the next available trunk block number is selected in the configuration block list (ABL). Similarly, the Clear Block List (CBL) is used to record the updated relay blocks that have been unconfigured and erased. ABL and CBL are reserved in controller RAM 13 0 (see Figure 1) for quick access and easy manipulation when updating blocks in tracking relative effects. The configuration block list (ABL) records the configuration of the pooled and erased trunk blocks of the erased trunk block that will become the update block. Thus, each of these relay blocks can be illustrated by an attribute specifying whether it is an erased block, an open update block, or a closed update block in an ABL suspended configuration. Figure 18 shows that the ABL contains: an erased ABL list 612, an open update block list 614, and a closed update block list 616. In addition, associated with the opened update block list 614 is the associated original block list 615. Similarly, associated with the closed list of updated blocks is the associated erased original block list 617. As shown previously in Figure 15, the list of these associations is a subset of the open update block list 614 and the closed update block list 616, respectively. 98704.doc -56- 1288328 The erased ABL block list 612, the opened update block list 614, and the closed update block list 616 are all subsets of the configuration block list (ABL) 610, in each list. The items have corresponding attributes. The MAP block 750 is a relay block dedicated to the erase management record in the flash memory 200. The MAP block stores a time series of MAP block segments, wherein each MAP segment is not an erase block management (EBM) segment 760, or a MAP segment 780. When the erased block is recirculated when the configuration is exhausted and the relay block is retracted, the associated control and directory data is preferably included in the logical section that can be updated in the MAP block, where the updated data will be updated. Each item is recorded in a new block section. Multiple copies of EBM section 760 and MAP section 780 may be present in MAP block 750, with only the latest version being active. The index of the location of the valid MAP section is contained in the block of the EMB block. A valid EMB segment is always written to the MAP block during the control write operation. When MAP block 750 is full, all valid sectors are rewritten to the new block location and compressed during the control write operation. Then erase the entire block. Each EBM section 760 contains an erased block list (EBL) 770, which is a list of subset addresses of the erased block population. The erased block list (EBL) 770 can be used as a buffer containing the erased block number, from which the relay block number is periodically taken to refill the ABL and periodically The block number is added to this buffer to re-empt the CBL. The EBL 770 can be considered as a buffer for the following: an available block buffer (ABB) 772, an erased block buffer (EBB) 774, and a cleared block buffer (CBB) 776. 98704.doc -57- 1288328 The available block buffer (ABB) 772 contains a copy of the ABL 610 project immediately following the previous ABL fill operation. It is actually a backup copy of the ABL after the ABL fill operation. The erased block buffer (EBB) 774 contains the erased block addresses previously transmitted from the MAP section 780 or the CBB list 776 (described below), and the addresses can be transmitted during the ABL fill operation. To ABL 610. The cleared block buffer (CBB) 776 contains the address of the erased block that has been transferred from the CBL 740 during the CBL clear operation and then transferred to the MAP segment 780 and the EBB list 774. Each MAP section 780 contains a bit mapping structure called "MAP". The MAP uses a bit of each of the relay blocks in the flash memory to indicate the erase status of each block. Bits corresponding to the block addresses listed in the ABL, CBL, or erased block list in the EBM section are not set to the erase state in the MAP. The block configuration algorithm will never be used in MAP, erased block list, ABL or CBL, any block that does not contain a valid data structure and is not designated as an erased block, so this cannot be accessed. Class blocks are used to store hosts or control data structures. This provides a simple mechanism to exclude blocks with defective locations from the accessible flash memory address space. The hierarchy shown in Figure 18 effectively manages erased block records and provides complete security for the list of block addresses stored in the controller's RAM. The erased block items can be exchanged between the list of block addresses and one or more MAP segments 780 in an infrequent manner. The information in the erased block list and the address translation table stored in the plurality of sectors 98704.doc -58 - 1288328 may be stored in the flash memory during system initialization after the power is turned off, and limited A small number of referenced data blocks in the flash memory are scanned to reconstruct the lists. The methods used to update the hierarchy of erased block records may be configured in the following order using the erased block: the block from the MAp block 750 is in the address sequence The block address plexes from the CBL 740 are interleaved, reflecting the order in which the system blocks are updated by the host. For most of the trunk block size and system memory capacity, a single MAP segment provides a one-dimensional mapping for all of the relay blocks in the system. In this case, the erased blocks must be configured for use in the same address order as recorded in this MAP segment. Erasing Block Management Operations As mentioned above, ABL 610 is a list of the following address items: • Erasable block that can be configured for use, and a block that has recently been configured as a data update block. The actual number of ABL·middle block addresses is between the maximum and minimum limits of the system design variables. During manufacture, the number of formatted AbL items is a function of the type and capacity of the memory card. In addition, since the number of available erased blocks is reduced due to block failures during the lifetime, the number of items in the ABL is also reduced to approach the end of the system life. For example, after a fill operation, items in the ABL can specify blocks that can be used for the following purposes. Each block has a part of a project that is written to the data update block and does not exceed the system's limit on the maximum update block that is simultaneously open. Used between one to twenty items configured as erase blocks for data update blocks. Four items that are configured to control the erased block of the block. 98704.doc -59- 1288328 ABL Fill Operation Since the ABL 610 becomes exhausted due to configuration, it needs to be refilled. The operation of padding the ABL occurs during the control of the write operation. This is triggered when the block is configured, but the ABL contains an erased block item that is not sufficient for configuration as a data update block or some other control data update block. During control writes, the ABL fill operating system and the GAT update operation are performed simultaneously. The following actions occur during the ABL fill operation. 1. Retain the ABL project with the attributes of the current data update block. 2. Retain the ABL item whose properties of the data update block have been closed, unless an item of the block is being written in the simultaneous GAT update job, in which case the ABL will be removed from the ABL project. 3. Reserve the ABL project for the unconfigured erase block. 4_ Compress the ABL to remove the gap created by the removal of the item to maintain the order of the items. 5. Completely populate the ABL by appending the next available item from the EBB list. 6. Overwrite the ABB list with the current projects in the ABL. CBL Clear Operation CBL is a list of erased block addresses in the controller RAM. The limit on the number of erased block items is the same as ABL. The operation of clearing the CBL occurs during the control of the write operation. Therefore, it is performed simultaneously with the ABL padding/GAT update operation or the CBI block write operation. In the CBL flush operation, items are removed from the CBL 740 and written to the CBB list 776. 98704.doc -60- 1288328 MAP Exchange Operation When the EBB list 774 has been emptied, the MAP swap operation between the erase block information and the EBM section 760 in the MAP section 78 can occur periodically during the control write operation. . If all erased relay blocks in the system are recorded in the EBM section 760, no MAP section 780 will exist and no MAP exchange will be performed. During the MAP exchange operation, the MAP section for feeding the erased block to EBB 774 is considered to be the source MAP section 782. The MAP segment used to receive the erased block from CBB 776 is considered to be the destination MAP segment 784. If there is only one MAP section, it can be regarded as the source and destination MAP section, which is defined as follows. The following actions are performed during the MAP exchange. 1 · Select a source map segment based on the incremental indicator. 2. Select a destination map segment based on the block address in the first CBB project that is not in the source MAP segment. 3_ Update the target MAp section in the manner defined by the relevant project in the CBB and remove the items from the CBB. 4. Write the updated destination MAP segment into the MAP block unless there is no separate source MAP segment present. 5. Update the source MAp section as defined by the relevant project in the CBB and remove the items from the CBB. 6. Add the remaining items in the CBB to the ebb. 7. Fill the EBB as much as possible with the erased sector address defined by the source MAP section. 8. Write the updated source MAP section to the MAP block. 98704.doc -61 - 1288328 9. Write an updated EBM section to the MAp block. List Management Figure 1 shows the distribution and flow of control and catalog information between various lists. For convenience, the operation of moving items or changing item attributes between list elements is identified as [A] to [〇] in Fig. 18, as explained below. [A] When the erase block is configured as an update block of the master data, its project attributes in the ABL are changed from the erased ABL block to the open update block. [B] When an erased block is configured as a control block, its items in the ABL are removed. [C] When an ABL project with open update block attributes is created, the associated original block block is added to the project to record the original relay block address of the updated logical group. This information is available from GAT. [D] When the update block is closed, its project properties in the ABL are changed from the open update block to the closed update block. [E] When the update block is closed, its associated original block is erased, and the attribute of the associated original block field of the item in the ABL is changed to the erased original block. [F] During an ABL fill operation, any closed update block whose address is updated in GAT during the same control write operation will remove its entry from ab]l. [G] During the ABL fill operation, when an item that has closed the update block is removed from the ABL, its associated item that erased the original block is moved to the CBL. 98704.doc -62- 1288328 [Η] When the control block is erased, the item used is added to the CBL. [I] During the ABL fill operation, the erased block item is moved from the EBB list to the ABL and assigned the attributes of the erased ABL block. [J] After modifying all relevant ABL items during the ABL fill operation, the block address in the ABL will replace the block address of the ABB list. [K] is performed simultaneously with the ABL fill operation during the control write, moving the items of the erased block in the CBL to the CBB list. [L] Move all related items from the CBB list to the MAP destination section during the MAP exchange operation. [M] Move all related items from the CBB list to the MAP source section during the MAP exchange operation. [N] After [L] and [M] during the MAP exchange operation, move all remaining items from the CBB list to the EBB list. [O] After [N] during the MAP exchange operation, if possible, move items other than the items moved in [Μ] from the MAP source section to populate the EBB list. Logical to Physical Address Translation To find the physical location of a logical segment in flash memory, the logical-to-physical address translation module 140 shown in Figure 2 can perform a logical-to-physical address translation. In addition to the recently updated logical group, most of the translations can be performed using the Group Address Table (GAT) resident in the flash memory 200 or the GAT cache memory in the controller RAM 130. The address translation of the recently updated logical group will require a list of addresses of the updated blocks that are primarily resident in controller RAM 130. Therefore, the logic of the logical sector address depends on the type of block associated with the logical group in which the physical address translation 98704.doc -63 - 1288328 is associated with the logical group in which the segment is located. The types of blocks are as follows: complete block, sequential data update block, mixed data update block, and closed data update block. Figure 19 is a flow chart showing a logical versus physical address translation procedure. Essentially, the logical block address is used to query various update directories (for example, the updated update block list and the closed update block list) to find the corresponding relay block and entity segment. If the associated relay block does not belong to the update program, the directory information is provided by the G AT. Logical to physical address translation involves the following steps: Step 8 0 〇 : Given a logical sector address. Step 810: Query the given logical address of the updated block list 614 opened in the controller RAM (see Figures 15 and 18). If the query fails, proceed to step 820, otherwise proceed to step 83. Step 820 - Query the given logical address in the closed update block list 616. If the query fails, the given logical address does not belong to any part of the update procedure; proceed to step 87〇 for GAT address translation. Otherwise, proceed to step 860 to perform a closed update block address translation. Step 830: If the update block containing the given logical address is sequential, the process proceeds to step 84A to perform sequential update block address translation. Otherwise, the process proceeds to step 850 for chaotic update block address translation. Step 840: Use the sequential update block address translation to obtain the relay block address. Proceed to step 880. Step 850··Use chaotic update block address translation to get the relay block bit 98704.doc 1288328 address. Proceed to step 880. Step 860: Use the closed update block address translation to obtain the relay block address. Proceed to step 88. Step 870: Use the group address table (GAT) translation to obtain the relay block address. Proceed to step 88. Step 880: Convert the relay block address to a physical address. The translation method depends on whether the relay block has been reconnected. Step 890: The physical sector address has been obtained. The various address translation processes are described in more detail below: Sequential Update Block Address Translation (Step 84〇) The information from the Open Update Block List 614 (Figures 15 and 18) can be directly converted and updated sequentially. The address translation of the target logical sector address in the logical group associated with the block is described below. 1. From the list (5) "Page Mark" and "Writed Section Number Mom", the position can be determined whether the target logical section has been configured in the update block or its associated original block. 2. From the clear, the relay can read the relay block address suitable for the target logical segment. 3. The appropriate "page mark" block determines the sector address within the relay block. The chaotic update block address translation (step 85〇) and the address translation sequence of the target logical sector address in the logical group associated with the chaotic update block are as follows. . = If the chaotic section list in 攸rAM determines that the section is the most recently written section, the address translation can be done directly from its position in this list. 98704.doc 1288328 2. The most recently written section in the CBI block contains the entity address of the chaotic update block associated with the target logical sector address in its chaotic block data block. It also contains the displacement within the CBI block of the CBI section last written to this chaotic update block in the indirect section index field (see Figures 16A-16E). 3. The information in the blocks is cached and stored in the ram without the need to read the segment during subsequent address translation. 4. Reading Step 3 The CBI segment identified by the indirect segment index is blocked. 5. The direct segment index field cache of the recently accessed chaotic update subgroup is stored in RAM without the need to perform the read at step 4 to repeatedly access the same chaotic update block. 6. The direct sector index intercept read in step 4 or step 5 can then identify the CBI section containing the logical subgroup containing the target logical sector address. 7. Read the hash block index entry of the target logical sector address from the CBI section identified in step 6. 8. The most recently scrambled block index bucket can be cached in the controller RAM without the need to perform the read at steps 4 and 7 to repeatedly access the same logical subgroup. 9. The Chaos Block Index item defines the location of the target logical section in the chaotic update block or associated original block. If the valid copy of the target logical segment is in the original block, it can be found using the original relay block and page tag information. Closed Update Block Address Translation (Step 860) The address translation of the target logical sector address in the logical group associated with the updated block can be directly completed and closed from the information of the updated updated block list. 98704.doc - 66 - 1288328 (see Figure 18), explained below. 1. The relay block address assigned to the target logical group can be read from the order. 2. From the “Page Mark” field in the list, you can determine the segment address in the relay block. GAT Address Translation (Step 87) If a logical group is not referenced by a block update list that is turned on or off, its entry in the G AT is valid. The address translation sequence of the target logical sector address in the logical group referenced by the GAT is as follows. 1. Evaluate the range of available GAT cache memory in RAM to determine if the target logical group's items are included in the GAT cache. 2 • If the target logical group is found in step 1, the gat cache memory contains complete group address information, including the relay block address and page mark, thus allowing translation of the target logical sector address. 3. If the target address is not in the G AT cache memory, the GAT index of the target GAT block must be read to identify the location of the G AT segment with respect to the target logical group address. 4. The GAT index of the last accessed GAT block will remain in the controller ram and can be accessed without reading the segment from the flash memory. 5 • A list of the relay block addresses of each G AT block and the number of segments written into each GAT block is stored in the controller ram. If the necessary GAT index cannot be obtained at step 4, it can be read from the flash memory immediately. 6. Read the gat section about the target logical group address from the extent location in the GA butyl area 98704.doc -67 - 1288328 block defined by the GAT index obtained at step 4 or step 6. The gat cache memory is updated with a subdivision of the section containing the target item. 7. Get the target segment address from the relay block address and the "page mark" block in the target GAT project. Relay block-to-physical address translation (step 880) If the flag associated with the relay block address represents that the relay block has been re-linked, the associated LT segment is read from the BLM block to Determine the erase block address of the target sector address. Otherwise, the block address will be erased from the relay block address. Control Data Management Figure 20 shows the operational hierarchy of the control data structure during the memory management operation. The data update management operation can work on various lists resident in the ^^". The control write operation can affect various control negative and special blocks in the flash memory, and can also be exchanged with the list in the memory. The data update management operation is implemented in RAM for ABL, CBL, and the list of chaotic sections. When the erased block is configured as an update zone ghost or control block, or is closed - update zone When the block is updated, the ABL is updated. When a control area is erased, or an item of a closed update block is written into the GAT, the cbl is updated. : When the write-chaotic update block is in the middle, the update chaotic section list is updated. ..., the operation knows that the information from the control data structure in the ram 98704.doc 68 - 1288328 is written to the flash memory In the control data structure, if necessary, the flash memory and other supported control data structures in the RAM are updated. When the ABL does not contain any other blocks of the erased block to be configured as update blocks. When project, or write to the CBI again In the case of a block, a control write operation is triggered. In a preferred embodiment, an ABL fill operation, a CBL clear operation, and an EBM segment update operation are performed during each control write operation. When an EBM segment is included When the MAP block is full, the valid EBM and MAP segments are copied to the configured erased block, and then the previous MAP block is erased. During each control write operation, a GAT region is written. The segment will also be updated with the list of updated blocks that are closed. When the GAT block is full, the GAT rewrite operation will be performed. As described above, after several times of chaotic segment write jobs, one will be written. CBI section. When the CBI block becomes full, the valid CBI section is copied into the configured erase block, and then the previous CBI block is erased. As mentioned above, the MAP exchange operation is performed in the EBM zone. When there are no other erased block items in the EBB list of the segment, each time the MAP block is rewritten, the MAP address for recording the current address of the MAP block is written in the dedicated MAPA block. (MAPA) section. When the MAPA block is full, a valid MAPA section will be copied. The configured erased block is then erased from the previous MAPA block. Each time the MAPA block is rewritten, the boot sector is written to the current boot block. When the boot block is full, The valid boot section of the current version of the boot block will be copied to the backup version, which will then become the current 98704.doc -69- 1288328 version. The previous current version will be erased and become a backup version and will The active boot sector is written back therein. The alignment of the memory spread across multiple memory planes. As previously described in connection with Figures 4 and 5A-5C, multiple memory planes are operated in parallel for added efficiency. Basically, each plane has its own sense amplifier, and as part of the item fetch program circuit, parallel services span the corresponding pages of the memory cells of the plane. When combined with multiple planes, multiple pages can be operated in parallel, which improves performance.

According to another aspect of the present invention, it is organized into a plurality of erasable blocks and is composed of a plurality of memory planes (so that a plurality of logical units can be read in parallel or a plurality of logical units can be paralleled A memory array that is stylized into the plurality of planes, when the original logical unit stored in the first block of the particular memory plane is to be updated, supplies the required logic to keep the updated logical soap elements In the same plane as the original. This can be done by recording the updated logical unit to the next available location of the second block that is still in the same plane. Preferably, the logic cells are stored in a plane in the same displacement position as the other versions, such that all versions of a given logic unit are served by the same set of sensing circuits. Accordingly, in the preferred embodiment of the present invention, any intermediate gap between the previous <&& γ i of the last stylized memory unit and the next aligned memory unit is originally filled in the logical unit. The current version of the logic that is logically located after the stylized logical unit - and _ 卞 is logically located in a usable plane row element that is stored in the raft In front of the logical unit -, "the body, this current logic is filled in the current version of 98704.doc -70- 1288328 to complete the filling operation. In this way, all versions of the logical unit can be maintained. In the same plane with the same displacement as the original, it is not necessary to extract the latest version of the logic unit from different planes in the waste project collection operation, so as not to reduce the performance. In a preferred embodiment, the latest is available. The version updates or fills each memory cell on the plane. Thus, a logical unit can be read out in parallel from each plane, which will have a logical order without further rearrangement. Rearranging the new version of the logical unit of the logical group on the plane, and eliminating the need to collect the latest version of the different memory planes, and shortening the time to summarize the chaotic blocks. There is a benefit in that the performance specification of the host interface can be defined as the maximum waiting time of the memory system and the segmentation of the memory segment. Figure 21 shows a memory array composed of multiple memory planes. The memory plane can come from The same memory chip or a plurality of memory chips. Each plane 910 has its own read and program circuit to parallel the pages of the memory memory unit without loss of generality, in the example shown,

The memory array has four planes that operate in parallel.訾 In general, a logical unit is the smallest unit accessed by the host system. A logical unit is a section of size 512 bytes. The page is a flat unit in the plane. Usually, a logical page contains one or one album I. Therefore, when a plurality of planes are combined, the maximum total number S of parallel read stylizations can be regarded as a relay page of the memory unit, and the relay page system is composed of multiple The pages of each plane in the plane are composed. For example, 98704.doc -71- 1288328 The relay page of MP〇 has four pages, that is, pages from each plane, μ, Μ, and Ρ3, in which logical pages are stored in parallel. The reading and intrusion efficiency of the memory is increased by four times compared to the operation of the heart (3), and therefore only in the _ planes. The memory array is further organized into a plurality of relay blocks, such as two, ..., and all of the memory cells in each of the relay blocks can be erased together by ', ', and - units. Such as MB. The relay block is constructed by a plurality of memory stands to store a logical page 914 of data, such as Lp "LPw. The logical pages in the relay block are distributed in four planes according to the order in which they are filled in the relay block. (9) ^^(4) For example, when the logical page is filled in the logical order, the - A cyclical sequence of the first page in the plane, the second page in the second plane, etc., visits the plane. After reaching the final plane, the fill returns in a round-robin fashion to restart from the first plane of the next relay page. In this way, successive logical pages can be accessed in parallel when all planes are in parallel operation. Generally speaking, if there are W plane parallel operations and the relay blocks are filled in a logical sequential order, the kth logical page of the sequence block will be resident in plane X, where x = k plane W. For example, if there are four planes, W = 4', when the blocks are filled in logical sequential order, the fifth logical page will be resident in the plane given by 5M〇D4, that is, the plane is as shown in _. The memory operation in each memory plane is performed by a set of read, write circuits 912. The data entering and leaving each read/write circuit is transmitted through the data bus 93 () under the control of the controller 920. The buffer 922 in the controller_ can assist in the transfer of buffered data via the data bus 93. In particular, 98704.doc -72- 1288328 When the operation of the first plane requires access to the data of the tenth side of the first π, the two-step procedure will be required. The controller will read the Shan Chu _ red column as the data of the second plane without the Jingya, and then transmit it to the first plane via the data bus and buffer. In fact, in most memory architectures, data transfer between two different bit lines also requires data exchange via data bus 920. At least 'this involves transferring from a set of read/write circuits in a plane and then entering another set of read/write circuits in another plane. In the case where the planar system is from a different wafer, germanium needs to be transferred between the wafers. The present invention provides a structure and scheme for memory block management to prevent a plane from accessing data from another plane to maximize performance. As shown in Fig. 21, a relay page is composed of multiple logical pages (each located in one of the planes). Each logical page may consist of more than _ logical units. When the data is to be recorded in a logical unit by block in a block spanning the planes, each logical unit will be in one of the four memory planes. Planar alignment issues occur when updating logical units. In the current example, for ease of explanation, the logical unit is treated as a logical section of 512-bit tuples, and a logical page is also a logical unit wide. Since the flash memory does not allow a portion of the block to be written without first erasing the entire block, the update of the logical page is not written to the existing location, but is recorded in the unused block. In the location. The previous version of the logical unit is then considered to be obsolete. After some updates, the block may contain some logical units that have become obsolete due to the update. Then this block can be said to be "not clean", and the abandoned project collection operation will ignore the dirty logic unit and collect the latest version of each 98704.doc • 73· 1288328 4 series 7L and re-sequence it in a logically sequential order. Recorded in a new block or a new block. Then erase and recycle the dirty blocks. When the Tianhai updated logic unit is recorded in the next unused location in a block, it is usually not recorded in the same body plane as the previous version. When a waste collection operation is to be performed, such as summarization or compression, the latest version of a logical unit will be recorded in the same way as the original

Vp T" y I A' to maintain the original order. However, if you have to extract the latest version from another plane, performance will be reduced.

Thus, in accordance with another aspect of the invention, the original logical unit of the first block of the plane is given. This can be accomplished by recording the updated logical unit to the next available location of the second block that is still in the same plane, in the preferred embodiment, and in the original block. The current version of the logical unit of the same relative position of the logical unit is padded (ie, filled by copying) any intermediate gap between the previous stylized memory unit and the next used plane aligned memory unit.

Figure 22A shows a flow chart of a method with planar alignment updates in accordance with a general embodiment of the present invention. Step 950 · In a non-volatile memory that is organized into a plurality of blocks, = each block is divided into a plurality of memories that can be erased together ^ 疋 'mother memory unit is used The library stores information about a logical unit. Step 952: constituting the memory by a plurality of memory planes, each plane having a set of sensing circuits for aligning the page of the service memory, the memory page having one or more memory cells. Step 954: Store the first version of the logical unit in a first order according to the first sequence in a plurality of memory units of the first block of -98704.doc -74 - 1288328 - the aw aw parent and the other version of the logical unit are stored in One of the memory planes. Step 956: storing in a second block according to a second subsequent version different from the first order, and storing the subsequent versions in the early and last versions in the same memory port as the first version. One of the available memory is in the early stage, so that all the versions of a logical unit can be accessed from the same plane using the sensing circuit of the set of ^^^. /22Β shows a preferred embodiment of the step of updating the material in the flow chart shown in Fig. 22A. Step 956' includes steps 957, 958, and 959. Step 957: Divide each block into a relay page, and each relay page is constructed by a page of each plane. This step can be performed before any of the storage steps. Step 958: Store the subsequent version of the logical unit to the second block according to the second order different from the first order, and each subsequent version is stored in the next available memory with the same displacement of the first page and the first version. In the body unit. Step 959: Simultaneously with the subsequent version of the storage logic unit, the current version of the logical unit is copied according to the first-order, and any unused memory units preceding the next available memory unit are filled one by one. & Figure 23A shows an example of a logical unit that writes a person to a sequential update block in a sequential order regardless of plane alignment. This example shows that each logical page is a logical segment, such as LS0, LS丨.... In the four-plane example, each block (eg, MB0) can be considered to be split into multiple relay pages 98704.doc • 75- 1288328 ο, MPi, ..., where each relay page (eg, Mp〇) Each contains four segments (eg, LSO, LSI, LS2, and LS3), each segment from planes P0, P1, P2, and P3, respectively. Therefore, the block is filled into the logical units in the planes p〇, ρι, p2, and p3 in a cyclical order. In host write operation #1, the data in logical section LS5_LS8 is being updated. The data that is updated to LS5, -LS8, is recorded in the newly configured update block starting at the first available location. In the host write operation #2, the block of the data in the logical section LS9_LS12 is being updated. The data that is updated to become LS9, 彳S12, is recorded in the update block in the position immediately after the end of the fetch write. The figure shows that the way of two host writes is to record the update data in the update block in logical sequential mode, namely LS5'-LS 12,. The update block can be thought of as a sequential update block because it has been filled in a logically sequential order. The updated data recorded in the update block can be used to eliminate the corresponding data in the original block. However, the update logic segment is recorded in the update block based on the next available location but regardless of the planar alignment. For example, the segment LS5 is originally recorded in the plane P1, but the updated LS5 is now recorded in the other. Similarly, all other update sections are not aligned. Figure 23B shows an example of a logical unit that writes a chaotic update block in a non-sequential order regardless of plane alignment. In host write operation #1, the logical segment LS10_LS11 of the given logical group stored in the original relay block is updated. The updated logical section LS10'-LS11' will be stored in the newly configured update block. At this point, the update 98704.doc -76- 1288328 block is a sequential update block. In the host write operation #2, the logical extents LS5-LS6 are updated to LS5'-LS6' and recorded in the update block immediately after the upper_write. This converts sequential update blocks into confusing update blocks. At the host write operation #3, the logical section LS 1 is updated again (V and recorded in the next position of the update block becomes LSI0.) At this time, the LSI0 in the update block can be replaced in the previous record. LSI0', and LSI0' can replace LS10 in the original block. In host write operation #4, the data of logical section LS10 is updated again and recorded in the next position of the update block to become LSI0" Therefore, LSI0'" is now the last and only valid version of logical segment LS10. All previous versions of LS 10 are now obsolete. In host write operation #5, the data for logical segment LS30 is updated. And record it in the update block to become LS301. In this example, the logical units in the logical group can be written to the chaotic update block in any order and in any repetition. Similarly, the update logic segment is based on The next available position, but regardless of the plane alignment, is recorded in the update block. For example, the sector LS 10 is originally recorded in the plane P2 (ie, MP2, the third plane), but the LSI 0 is updated, but now recorded in P0. (ie 'MP〇' In the first plane). Similarly, in the host write #3, 'the logical section LS101 will be updated again to LS10" and placed in the next available position where the result is also in the first plane of the plane POCMPi') Thus, in general, it can be seen from the figure that recording the update section to the next available location of the block causes the update section to be stored in a different plane than its previous version. Planar Aligned Sequential Update Block 98704.doc -77 - 1288328 Figure 24A shows a sequential update example of Figure 23A with plane alignment and padding in accordance with a preferred embodiment of the present invention. The data that is updated to LS5, _LS8, is recorded in the newly configured update block starting from the first available plane alignment position. In this example, 'LS5 is originally in p1, and p1 is the first page of the relay page. The second plane. Therefore, the LS5'-LS7' will be programmed in the corresponding plane of the first available relay page MP〇 of the update block. At the same time, the logical segment LS4 before the LS5 will be relayed in the original block. Current version of the fill The gap of the first plane that is not used in Ι γ. The original LS 4 is then processed into the eliminated data. Then the remaining LS8' is recorded in the first plane of the next relay page ΜΡ, and is aligned in the plane. In operation #2, the data of the update to LS9, -LS 12, will be recorded in the update block of the next available plane alignment position. Therefore, LS9' will be recorded in the next available plane-aligned memory unit, ie The second plane. At this point, no gaps are created and no padding is required. The update block can be viewed as a sequential update block because it has been filled in a logically sequential order. In addition, it will be planarly aligned because each update logic unit is in the same plane as its original. Alignment chaotic update block with intermediate gaps Figure 24B shows a chaotic update example of Figure 23B with plane alignment and without any padding in accordance with a preferred embodiment of the present invention. In host write operation #1, the updated logical extents LS10'-LSll are stored in the newly configured update block. It is not stored in the next available memory unit, but is stored in the next available plane pair 98704.doc 1288328. Since the LS10' and LSI Γ were originally stored in planes Ρ2 and Ρ3 (the third and fourth planes of 原始2 of the original block), the next available plane-aligned memory unit will be in the updated block. In the third and fourth planes, at this time, the update block is non-sequential, and the pages of the relay page Mp〇 are filled in the order of "unfilled", "unfilled", LS10f, and LS11'. In host write operation #2, the logical segment LS5-LS6 is updated to LS5f-LS6' and recorded in the next available horizontally aligned update block. Therefore, the second (ρι) and third (p2) planes of the MP1 or the LS5' and LS6' of the § memory unit in the original block are programmed into the next available page MP! in the update block. In the corresponding plane. This leaves the first unused plane in front of mp i . At host write operation #3, the logical sector LSI is updated again, and it is recorded in the next plane alignment position of the update block to become LS10". Therefore, it will be written to the next available third plane, in MP2. This leaves a gap in the front in the rear plane of μρ〆 and the first two planes of ΜΡ/. This will eliminate the LS10 in MP〇'. In host write operation #4, the data in the logical sector LSI 〇" is updated again and recorded in the next available second plane of the relay page ΜΡ/ in the update block becomes LS10"f. LS10M1 is the last and only valid version of the logical section lsi〇. This leaves a gap consisting of the last plane of MP2, and the two planes of MP/. In host write operation #5, the logic is updated. The data of the segment LS30 and its record in the update block become LS30. Since the original LS30 is resident in the P2 or the third plane of the relay page, it will be written in the update block 98704.doc - 79- 1288328 available second planes. At this time, it will be the third plane of mi>4. The gap will be generated due to the last plane of MP3' and the first two planes of Μιγ. Since 2' this (four) display can The plane alignment method, in any order and any repetition, writes a plurality of logical segments in a logical group into a chaotic update block. In subsequent garbage collection operations, it will be conveniently by the same group. Sensing circuit to serve given logic All versions of the segment, especially the latest version. A chaotic update block with plane alignment to fill the filled intermediate gap. Figure 24C shows a preferred embodiment of the present invention having planar alignment and padding in accordance with Figure 23A. The chaotic update example. This operation is the same as shown in Figure 24, but the intermediate gap is filled with padding first. In host write operation #1, the current version of LS8 and LS9 resident in the original block will be used first. Filling the gap generated by the first and second unused planes of the relay page Mp. This will cause LS8 and lS9 in the original block to be eliminated. At this time, the update block is a sequential update block in which the relay is relayed. The padding order of the page MP〇' is LS8, LS9, LS10, and LS11. In the host write operation #2, a gap will be generated due to the first unused plane in the first, which will be first performed by LS4. This will cause the LS4 in the original block to be eliminated. As before, the second write can convert the sequential update block into a chaotic update block. In the host write operation #3, it will be due to Last used The plane and the first two planes of the MP/ create a gap. The last plane of the MP1 is filled with the LS7 after the last stylized LS6', and then the logical unit before the Lsi〇 (ie LS8&LS9) To fill the first two planes of the MIV. This will 98704.doc -80- 1288328 retire MP (in LSIO1 and LS7-LS9 in the original block. In host write operation #4, will be generated by the end of MP/ The gap between the plane and the first two planes of mp3. The last plane of MP2' can be filled by the LS11' in the relay page MP2' after the last written LSI 0" The first two planes of the MP/ can be padded by LS8 and LS9, respectively, as in the Logic 0, before, and in the relay page MP3'.

In the host write operation #5, the gap between the last two planes from MP3' to MP4 and the first two planes is also filled with LSI 1, LS28, and LS29, respectively. Thus, this example shows that a plurality of logical segments within a logical group can be written into a chaotic update block in any order and any repetition, in a planar alignment manner.

In a preferred embodiment, a relay page contains loop pages from individual flats. Since relay pages can be read or programmed in parallel, it is convenient to implement host updates at the granularity of the relay page. When there is any padding, it can be recorded along with the update logic unit of the relay page. In the particular embodiment shown in the example of Figures 24A and 24C, padding is performed between each of the main; write Js on the memory cells that are to be used to customize the updated planar aligned memory cells. In the next host write, don't delay any action on the memory unit after the last stylized memory unit. A 舯 ^ ^ ; ... 斯 奴 奴 s, will be at the border of each relay page 4 ^ to fill any unused memory in the front of the single it. In other words, if the gap in the front of the > spans over the two Uchida 1U T turtle pages, then according to each relay page, the appropriate logically sequential order is performed on each of the relays. , but 98704.doc -81 - 1288328 continuity across the border. When the block is summarized, the last written page of the person, such as a partial write, can be completely filled by padding. In another embodiment, any partially populated relay page can be fully populated before moving to the next relay page. Memory Cell Granularity Read or stylized cells can vary depending on the flexibility supported by the individual memory architecture. The individual features of the individual planes allow independent reading and programming of individual pages of individual planes in the relay page. The above example has the largest stylized unit for pages in each plane. Within the relay page, there can be partial relay page stylizations that are smaller than all pages. Example #, you can program the first three pages of the relay page and then program the fourth page. Also, at the plane level, a physical page can contain one or more memory cells. If each memory unit can store data for one segment, then: a physical page can store one or more segments. Some memory architectures can support partial page stylization'. By suppressing the stylization of selected memory cells within a page, the selected logical units can be programmed at different times in multiple stylized encoding processes. Logical unit alignment for chaotic updates of logical groups in the memory plane In the block memory system, logical groups of logical units are stored in the original block in a logically sequential order. When a logical group is updated, subsequent versions of the logical unit are stored in the update block. If the logical unit is stored confusingly (ie, non-sequentially) in the update block, the obsolete project collection is finally performed to collect the latest version of the original block and the logical unit in the update block to sequentially integrate it into the new original. Block. If all of the updated versions of the given logical list 98704.doc -82 - 1288328 兀* are stored in the update block aligned with the original version in its original block, so that the same set of sensing circuits can access all versions, then Obsolete project collection operations are more effective. According to another aspect of the present invention, in the above-described block memory management system, 'when a memory is organized into a series of memory pages (where each page of the memory unit is parallelized by a set of sensing circuits), If all versions of a given logical unit have the same displacement position in the stored page, all versions are aligned. Figure 25 shows an exemplary memory organization in which each page contains two memory cells for storing two logical units, such as two logical segments. In the original block, 'since the logical segments are stored in a logical sequential order, the logical segments LSO and LSI are stored in the page p〇, the logical segments LS2 and LS3 are stored in the page, and The logical sections [84 and LS5 are stored in the middle of page P3. It can be seen that in the pages of the two sections, the page displacement of the first section from the left is "〇", and the page displacement of the second section is "1". When the logical group of logical segments sequentially stored in the original block is updated, the updated logical segment is recorded in the update block. For example, the logical segment LS2 is resident in the page p〇 with the displacement r 〇" in the original block. If in the first write, if LS2 is updated to LS2, it will be stored in the first available location of the update block with the same page offset "〇". This will be in the first memory unit of page P0'. If LS5 is updated to LS5' in the second write, it will be stored in the first available location of the update block having the same page displacement "J". This will be in the second memory unit with the displacement "1" of page P1. However, before storing LS5, the latest version of the logical section that will maintain the logical sequential order at least in each page is copied at 98704.doc -83 - 1288328 to fill the displacement "1" in P0'. The memory unit and the displacement "〇" in P1' are not used. At this time, LS3 will be copied to p〇, the position of "1" will be shifted, and LS4 will be copied to P1, and the position of "〇" will be shifted. If 1^2 is updated to LS2" again in the third write, it will be stored in the displacement "〇" of P2'. If it is updated to LS22' and LS23' in the fourth write, it will be stored in the displacements "〇" and "i" of P3, respectively. However, before that, the unused memory cells with a bit shift of "1" in P2 are filled with LS3. The above update sequence assumes that individual sections can be programmed within the page. For memory architectures where partial page stylization is not supported, the sections within the page must be stylized together. At this time, in the first write, LS2, and LS3 will be programmed into Ρ0·. In the second write, it will be programmed together into pi'. In the third write, LS2" and lS3 are programmed together to P2f* and so on. Planar alignment within the relay page Alternatively, the stylized unit can have the granularity of the relay page. If the granularity of writing the chaotic update block becomes a relay page, the items in the CBI block described in connection with Figures 16A and 16B will be related to the relay page, not to the sector. Increased granularity reduces the number of items that must be recorded for the chaotic update block

The number and allows for direct elimination of the index and the use of a single cBI segment per relay block. The memory of Fig. 26A and Fig. 21 has the same structure except that each page contains two areas & Therefore, the relay page Mp can be seen from the figure. Now each has its own 98704.doc -84- 1288328 page that can store the data of two logical units. If each logical unit is a zone &, the logical sections are sequentially stored in the plane p〇 and in the MP0 of LS2 and LS3 in the plane P1. Fig. 26B shows a relay block shown in Fig. 26A having a memory unit arranged in a line graph manner. Compared with the single-segment page of Fig. 21, the logical area & is stored in a four-page four pages in each page.

In general, S, if there is a plane in which the hips operate in parallel and each page has a single 7G, and the relay blocks are filled in a logical sequential order, the kth logical page in the relay block will Resident in a planar species, where x = k, M0D

W, where k' = INT(k/K). For example, there are four planes, w = 4, 2 segments per 4 pages, κ = 2 ' for k = 5, which means the fifth logical region name LS5, which will reside in 2 M〇D 4 In a given plane, that is, plane 2, = 24A... In general, the same principle applies to the implementation of the above-described flat alignment. The above example is used for multiple 芈 and @蓉10-sided architecture in the alignment of planes and pages. In the case of a page with multiple sections, it is also advantageous to have #i && 乜 maintain the alignment of the sections within the page. In this way, using the sensing circuit of the "flying phase" group is beneficial for the same

Different versions of the logical section. There may be U%, such as the reconfiguration of the section and the "continuation-modify" write operation. In the adoption and alignment of the page and the plane, it can be filled with h. It can also be filled with any intermediate gap according to the specific embodiment. The logical unit plane alignment without filling is shown in Figure 27. For #柯f# 幻幻计划 as follows: do not need to fill the sneakers from one position to 98704.doc -85- 1288328 to another, you can get in the update area. You can go to the update area. The planes of the four planes of the plane pair and the update block are autonomously 趟+ τ. The knives are regarded as four collections, and the planes of the sighs are aligned with the moon and the new logic is early and slow. The next one of the devices is received from the host &, Luo M 0 — , P can be privately ported to the ear of the ear 7 ^. According to Zhao Zhao from the wide Μ Μ received from the host logic list, sequence There may be a different number in each plane. The coffee is early - is programmed to this updated area, an updated version of all logical units that can contain logical relay pages, such as for expansion. Can contain less than all logic of the relay page ~ as used for ΜΡ, in In the example of ..., the missing logical unit core can be obtained from the corresponding original block ΜΒ(). This alternative scheme is particularly effective when the memory architecture can support parallel reading of any logical page of each plane. In the single-parallel read operation, β can take all the logical pages of the relay page, even if the individual logical pages are not from the same column. Staged program error handling When there is a program failure in the block, it will usually be all The data stored in the block is moved to another block and the failed block is marked as bad. Depending on the timing specifications of the operation in which the failure occurred, there may not be enough time to move the stored data to another area. Block. The worst case scenario is a program failure during a normal abandoned project collection operation, where another identical waste project collection operation is required to reconfigure all data to another block. In this case, it may be reversed. The write latency limit specified by the host/memory device, which is typically designed to be accommodated once (and 98704.doc -86 - 1288328) Non-twice) Abandonment project collection operation. Figure 28 shows a scenario in which the defect block repeats the summary operation on another block when the program fails during the summary operation. In this example, block 1 is logically The original block of the complete logical unit of the logical group is sequentially stored. For ease of explanation, the original block contains segments a, b, c, and D, each storing a logical unit of a subgroup. When the host updates the group For a particular logical unit, a newer version of the logical unit is recorded in the update block, block 2. As previously described in connection with the update block, depending on the host, this update can be sequential or non-sequential (chaotic) The logical unit is recorded sequentially. Finally, the update block is closed to receive the progress update because the update block is full or for some other reason. When the update block (block 2) is closed, the current version of the logical unit resident on the update block or the original block (block 1) is summarized on the new block (block 3) to form The new original block of the logical group. This example shows that the update block contains a newer version of the logical unit in sections B and D. For convenience, the sections B and D are displayed in the block 2 not necessarily at the position where they are recorded, but are aligned with their original positions in the block 1. In the summary operation, the current version of all logical units originally resident in the logical group of block 1 is recorded in the summary block (block 3) in sequential order. Therefore, the logical unit of the sector A is copied from the block 1 to the block 3, and then the block B is copied from the block 2 to the block 3. In this example, when copying the logical unit of the sector C from the block 1 to the block 3, the defect of the block 3 will cause the program to fail. One way to resolve a program failure is to restart the summary program on a brand new block (block 4). Therefore, the segments A, B, C, D are copied on the block 98704.doc -87 - 1288328 4 and then the defective block 3 is discarded. The bran and ▲ 妯 妯 妯 从 从 从 从 从 从 , , , 从 从 从 , , , , , , , , , ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ ▲ The specific time tolerance of the owner. For example, when the host writes to the memory device, P, . r S in 4 expects the write operation to be at the specified time r, which is known as the "write wait time". When the card is busy writing the data of the host, it will send a message "B is like the ceremony to the host. If the "BUSY-like slave" is in the form of a product, the main character is "s" and the long-lasting error of the write waiting time continues. . After the ..., write access exception or =9 to the schematic shows the host write operation with the timing or write wait time that allows enough time to complete the write (update) operation. The master has a write timeout, which provides (4) the time to complete the update operation 972 of writing the sense and shell 4 to the update block (Fig. 10). As described in the block government system, the update block The host write can trigger the summary #. Therefore, the 'timing also allows the summary operation 974 outside the update operation (Fig. 29(B)). However, the summary operation must be restarted in response to the failed capsule operation. Too much time and exceed the specified writer waiting time. According to another aspect of the invention, in the memory with the block management system: 'In the time-critical memory operation, the program failure in the block can be improved by ^ The program in the breakout block is also operated to handle. Later, in less urgent time, the feed recorded in the failed block before the interruption can be transferred to other blocks that may also be interrupted blocks. In this way, the failed block can be discarded. In this way, when the defective block is encountered, the data will not be lost due to the need to immediately transfer the data stored in the defective block and the time specified by 98704.doc -88- 1288328 Limit, ie This error handling is especially important for the collection of abandoned items, so there is no need to repeat the entire operation for a new block during an emergency time. Thereafter, at the appropriate time, by reconfiguring to other blocks, The data of the defective block can be saved. Figure 3A shows a flow chart of the failure handling of the program according to the general scheme of the present invention. Step 1002 · Organize the non-volatile memory into blocks, and divide the blocks into pieces that can be wiped together. In addition to the memory unit, each memory unit can store data of a logical unit. Program failure handling (first stage) Step 1012 · Store a series of logical unit data in the first block. v1014· In response to storage Some of the logical units fail to be stored in the first block, and the subsequent logical units are stored in the second block as the interrupt block of the first block. Program failure handling (final stage), step 1020: in response to the predetermined The event transfers the logical unit stored in the first block to the third block 'where the third block and the second block may be the same or different. Step 1022 · Discarding the first block. Figure 31A shows a specific embodiment of the program failure handling, wherein the third (last reconfiguration) block is different from the second (interrupt) block. Recording a series of logical units on the first block. If the logical unit is from a host write, the first block can be regarded as an update block. If the logical unit is a summary from a compression operation, the first area can be The block is considered to be a new configuration block of 98704.doc -89 - 1288328. If the program fails in block 1 at some point, the port provides the second block as the interrupt block. In block 1 and subsequent Logical units that fail to log in the logical unit are recorded on the interrupt block. In this way, no additional time is required to replace the failed block 1 and the data resident on it in intermediate stage II, which is available in block 1 And all the recorded logical units in the sequence are obtained between blocks 2. In the final phase III, the logical unit is reconfigured to block 3, which can be considered as a reconfigured block, to replace the failed block 1 and the data resident on it. Therefore, the data in the failed block can be saved and the failed block discarded. The final phase is scheduled so that it does not conflict with the timing of any simultaneous memory operations. In this particular embodiment, reconfiguration block 3 and interrupt block 2 are differentiated. This is convenient when the interrupt block has been recorded with an additional logical unit during the intermediate phase. Therefore, the interrupt block has become an update block and may not be suitable for reconfiguring the logical unit of defective block 1 therein. Figure 31B shows another embodiment of a program failure handling in which the third (last reconfiguration) block is the same as the second (interrupt) block. Stages 1 and 11 are the same as the first embodiment shown in Fig. 31A. However, in stage m, the logical unit of defective block 1 is reconfigured to interrupt block 2. This is convenient when the interrupt block 2 is not recorded by an additional logical unit other than the original sequence of the previous write operation. In this way, the block required to store the logical unit in question is the smallest. Specific Examples of Program Failure Dispositions During Aggregation Program failure handling is especially important during summary operations. The normal summary operation 98704.doc -90· 1288328 summarizes the current versions of all logical units resident in the original block and the updated block to the summary block. During a total abandonment operation, if a program failure occurs in the summary block, another block that serves as an interrupt summary block is provided to receive a summary of the remaining logical units. In this way, it is not necessary to copy the logical unit more than one time, and the exception processing can still be completed within the period specified by the normal capsule total operation. At the appropriate time, all the unprocessed logical units of the group are summarized into the interrupt block to complete the total abandonment operation. The appropriate time will be during the period of some other time-synthesizing summaries other than the current host write operation. One such suitable time 疋1 another period during which the host writes the updated but unrelated summary operations. ‘Essential soil’ can be considered as a multi-stage summary of the failure of the program. In the first phase, after a program failure occurs, the logical unit is divided into two or more blocks to avoid summarizing the logical units more than once. The final phase is completed, where the logical groups are summarized into one and the second is best collected by the sequential order in which all logical units are collected into the total block. Ding τ 232A shows a flow chart that causes the initial update operation of the summary operation. Cut: Γ: The technical volatile memory is organized into blocks, and the data of each unit is divided into blocks. Early storage of a logic Step 1104 • Organize the data into a plurality of logics for groups that can be stored in the (four) towel dragon unit. |Logic Group / Step 1112. Receive host data encapsulated in the logical unit. 98704.doc -91 - 1288328 Step 1114:

Create the original block of the logical group. The first version of the logical unit, step 1116:

Record to a new block. Figure 32B shows a flow chart of a multi-stage summary operation in accordance with a preferred embodiment of the present invention. Summary Failure Handling (Phase I) Summary of Error Handling, Phase I Operation i i20 includes Step 22 and Step 1124 〇 Step 1122: Store the logical group in the third block in the same order as the first order The current version of the logical unit to create a summary block of logical groups. Step 1124: In response to the storage failure of the summary block, the logical units of the logical group not included in the third block are stored in the fourth block in the same order as the first sequence to provide an interrupt summary block. Since the data in block 1 and block 2 has been transferred to block 3 and block 4, block 1 and block 2 can be erased to free up space. In the preferred embodiment, blocks 2 through EBL (list of erased blocks, see Figure 18) can be immediately released for use. Block 1 can only be released under the following conditions: if it is a closed update block and there is another block pointed to by the corresponding GAT item 0 98704.doc -92- 1288328 In essence, block 3 becomes logical The original block of the group, and block 4 becomes the replacement of the block 3 with the sequential update block. After completing Phase I, the memory device sends a message to the host by releasing the BUS Y signal. Intermediate Operation (Phase II) Phase II, intermediate operation H30, may occur prior to Stage III summary operation 1140. As suggested by any of steps 1132, 1134, 1136, there may be several possible scenarios. Step 1132: Or in the write operation of the logical group, write the fourth block (interrupt summary block) as the update block. If the host writes the logical group in question, block 4, which is the interrupt summary block and which has now replaced the sequential update block, will be used as the normal update block. Depending on the host write, it can be maintained in a sequential or chaotic state. As an update block, it will trigger the closing of another chaotic block at some point, as described in the previous preferred embodiment. If the host writes to another logical group, it goes directly to the stage ΠΙ operation. Step 1134: In the read operation, the memory in which the third block is the logical group original block and the fourth block is the update block is read. At this point, the logical units of segments a and B are read from block 3 of the original block for the logical group, and the logic for reading segments c and D from block 4 for the updated block of the group. unit. Since only segments a and B can be read from block 3, pages that have failed to be stylized cannot be accessed, and portions that have not been written later cannot be accessed. Although the GAT directory in the flash memory has not been updated and it still points to block 1 of the original block 98704.doc -93 - 1288328, no data is read from it, and the block itself has been wiped out earlier. except. Another possibility is that the host reads the logical units in the logical group. At this time, the block 3 of the original block of the logical group reads the logical unit of the sections A and B and reads the sections C and D from the block 4 of the sequential block of the group. Logical unit. Step 1136: or in power-on initialization, by scanning the contents to re-identify any of the first to fourth blocks. Another possibility in the intermediate phase is to turn off the power to the memory device and then restart. As described above, during power-on initialization, the blocks in the configuration block list (the erase block blocks to be used, see Figures 15 and 18) are scanned to identify the original blocks that have become special states in the logical group ( Block 3) and associated defect update block (block 4) defect summary block. The flag in the first logical unit of the interrupt block (block 4) will indicate that the associated block is the original block that has encountered a program error (block 3). Block 3 can be found by looking up the block directory (GAT). In a specific embodiment, the flag is programmed to the first logical unit of the interrupt summary block (block 4). This can assist in indicating the special state of the logical group: that is, it has been aggregated into two blocks, namely, block 3 and block 4. An alternative to using flags to identify logical groups with defective blocks is to use features that are not as full as the original block (unless the error occurred on the last page, and the last page has no ECC error). The block is a defective block. Also, depending on the embodiment, there will be an information record about the failed group/block of the control data structure stored in the flash memory, and 98704.doc -94 - 1288328 is not just in the write interrupt summary area. The flag in the header area of the first segment of the block (block 4). Summary completion (stage III) v step 1142 · In response to the predetermined event, for the first case when the fourth block is not further recorded since the stage, the logic is stored therein in the same order as the first order The current version of all unprocessed logical orders = of the group; for the first case when the fourth block has been further recorded since the stage, the third and fourth blocks are summarized into the fifth block. Step 1144: After that, for the first case, when the memory is operated, the aggregated fourth block is used as the original block of the logical group; for the second case, when the memory is operated, the fifth block is used as the logic. The original block of the group. As long as there are any machines t that do not violate any of the specified time limits, the final summary in the phase out can be performed. A preferred case is when there is another update operation of the logical group without the summary operation, "attach (one (four)" on the next host write time slot. If another logical group host writes Triggering the collection of abandoned items will delay the aggregation of stage m. Figure 33 shows the sample sequence of the first and last stages of the multi-stage summary operation n ^1. The host writes the wait time and is right. , the width of each host that has a duration of 1 is written. The host write 1 is a simple 1 early update, and the current version of a logical unit in the logical group LGi will be recorded in the associated On the update block. When the host writes 2, it will be updated on the logical group group LGI, causing the more blocks to be closed (for example, full). Ready & 9 edge for the new update area Block to record the remaining updates. Provides a new update block from 3 triggers the collection of obsolete items, resulting in a summary operation of 98704.doc 95 1288328 on LG* to recycle the blocks to be reused. The current logical unit will be recorded in sequential order On the summary block, the summary operation can continue until the defect is encountered in the summary block. Then call the 13⁄4 segment Ϊ summary 'where the total dish operation continues on the interrupt summary block. At the same time, the final summary of LG4 (phase III) Will wait for the next opportunity. In the host write 3, the logical unit of the logical group LG2 will also be written to trigger the summary of LG2. This means that the time slot has been fully utilized. At the host write 4, the operation is just LG: Some of the logical units are logged to their update block. The remaining time in the time slot provides the opportunity to perform the final summation of !4. The specific embodiment of not converting the interrupt summary block to the update block is shown in Figures 34A and 34B, respectively. A first case of Phase I and Phase III operations of the multi-stage summary applicable to the examples of Figures 28 and 31 is shown. Figure 34A shows a summary in which the interrupt summary block is not used as an update block but is used as a summary of its summary operations. An example of a block. In particular, FIG. 34 refers to the host write #2 shown in FIG. 33, in which the host writes an update of the logical unit belonging to the logical group LGi, and during this time, the operation also touches A summary of the blocks associated with another logical group LG#. The original block (block 1) and the update block (block 2) are formed in the same manner as the example of Fig. 28. Similarly, during the summary operation, It is known that the summary block (block 3) is defective in summarizing the logical units of section C. However, unlike the re-aggregation scheme of the figure, this multi-stage scheme can be used as the interrupt summary area in the new provision. The summary operation continues on the block (block 4) of the block. Therefore, in the stage I summary operation, the logical units of the segment 98704.doc -96-1288328 have been summarized in the summary block (block 3). When a program failure occurs in a block, the remaining logical units in the areas 4 and C and D are sequentially copied to the interrupt summary block (block 4). If the host originally writes the update in the first logical group triggers the summary operation of the block associated with the second logical group, the update of the first logical group is recorded to the update of the logical group. Block (usually a new update block). At this point, the interrupt summary block (Block 4) will not be used to record any update data outside of the summary operation and will maintain the interrupt summary block that must be completed. Since the data in blocks 1 and 2 is now completely contained in another block (block 3 and block 4), it can be erased for recycling. The Address Table (GAT) is updated to point to Block 3 as the original block of the logical group. The directory information of the update block (in the ACL, see Figure 15 and Figure 18) will also be updated 'to point to the block 4 of the sequential update block that has become a logical group (eg, LG4), the result of the summary logic The group is not confined to one block, but is distributed over the defect summary block (block 3) and the interrupt summary block (block 4). An important feature of this scenario is that the logical units in the group will only be aggregated once during this phase, but the summary is spread over more than one block. In this way, the summary operation can be completed within the normally specified time. Figure 34B shows the third and final stages starting from the multi-stage summary of Figure 34A. As described in connection with Figure 33, the Phase III summary is performed at a suitable time after the first phase (e.g., during subsequent host writes that do not trigger the accompanying summary operation). In particular, Fig. 34B refers to a time slot in which the host write #4 shown in Fig. 33 occurs. During this period, the host write can update the logical unit belonging to logical group LG2 without triggering another additional summary operation. Therefore, there are 98704.doc -97-1288328 which facilitates the use of the remaining time in the time slot for the phase ΠΙ operation to complete the aggregation of the logical group lg4. This operation summarizes all unprocessed logical units of LG* that are not yet in the interrupt block into the interrupt block. In this example, this means that sections a and B are copied from block 3 in logically sequential order to the interrupt block (block 4). Due to the wraparound scheme of the logical units in the block and the use of page markers (see Figure 3A), even if the example is shown in block 4, segments a and b will be recorded after segments C and D, but will still be The sequence of records is considered to be equivalent to A, B,. , the sequential order of D. Depending on the embodiment, the current version of the unprocessed logical unit to be copied is preferably obtained from block 3, since it is already in a summarized form, but may also be from block i and block 2 that have not been erased. Collected in. After the final summary is completed on the interrupt block (block 4), it is designated as the original block of the logical group and is updated with the appropriate directory (eg, gat, see Figure 17A). Similarly, the failed physical block (block 3) is marked as bad and is excluded. Other blocks 'Block 1 and Block 2' will be erased and recycled. On the same day, the LG2 update will be recorded in the update block associated with LG2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INTERRUPTION ACCUMULATION BLOCKS FIG. 35A and FIG. 35B respectively show a second case of Phase I and Phase III operations of the multi-stage summary of the examples of FIGS. 28 and 33. Fig. 35A shows an example in which the interrupt summary block is maintained as a newer block written by the receiving host instead of the summary block. This applies to host writes such as updating the logical group LG^, and in this program, it also triggers the sum of the same logical group. As in the case of Figure 34A, the aggregation of block 1 and block 2 in block 3 will continue 98704.doc -98 - 1288328 until the program fails when processing segment c. The summary is then continued on the interrupt summary block (block 4). After summarizing the unprocessed logical units (eg, in section C&D) in the interrupt block (block 4), they do not wait for completion of the logical group summary in phase III, but maintain the interrupt block. To update the block. This case is especially suitable for situations where a host writes an updatable logical group and triggers a summary of the same logical group. In this example, this records the record of the host update of the logical group LG* in the interrupt summary block (block 4) instead of the new update block. This update block (previously the interrupt summary block (block 4)) can be sequenced or confusing based on the host data recorded therein. In the example shown, block 4 has become confusing because the subsequent newer version of the logical unit in segment C causes the previous version in block 4 to be phased out. During the intermediate phase, block 3 will be considered the original block of LG4, and block 4 will be the associated update block. Figure 35B shows the third and final stages starting from the multi-stage summary of Figure 35 in the second example. As described in connection with Figure 33, phase III is performed at the appropriate time after the first phase, as during subsequent host writes that do not trigger the accompanying summary operation. During this period, the host writes can update the logical units belonging to the logical group without triggering another additional summary operation. Therefore, it is advantageous to use the time remaining in the time slot for the phase ΠΙ operation to complete the aggregation of the logical group LG4. The obsolete items of logical group LG4 are then collected from block 3 and block 4 to the new summary block (block 5). Block 3 is then marked as bad, block 4 is recycled, and the new summary block (block 5) becomes the original block of the new 98704.doc -99-1288328 of logical group LG4. Other blocks, Block 1 and Block 2, will also be erased and re-circulated. Other Specific Embodiments of Phased Program Failure Handling The examples described in Figures 31A, 31B, 34A, 34B, 35A, and 35B are applicable to a preferred block management system in which each physical block (relay block) is only stored. Logical units belonging to the same logical group. The invention is equally applicable to other block management systems in which no logical group is aligned to a physical block, such as the block management system disclosed in WO 03/027828 and WO 00/49488. Some examples of implementing a staged program failure handling method in these other systems are shown in Figures 36A, 36B and 36C. Figure 36A shows a phased program error handling method for the case where the host write triggers the shutdown of the update block and the update block is sequential. The closing in this example is accomplished by copying the remaining valid data (B and C) of the original block 2 to the sequential update block 3. In the example where the program in the data part c stylized starting point fails, part C is programmed to the reserved block 4. The new host data can then be written to the new update block 5 (not shown). Phases II and III of this method are the same as in the case of a closed block. Figure 3 6B shows a phased program error handling method applied to the (local block system) in the updated example of the update block. In this example, the logical group is stored in the original block i and other update blocks. The summary operation includes copying the data of the original block 1 and other update blocks 2 to one of the update blocks (selected according to some rules, block 3 in the figure). The main difference from the already explained case is that block 3 has been partially written. Figure 36C shows a staged program error handling the discarded item collection operation, or 98704.doc 1288328 does not support clearing in the memory block management system mapped to the logical group of the relay block. Such a memory block management (cyclic storage) system is described in WO 03/027828 A1. An obvious feature of the circular storage system is that no blocks are configured for a single logical group. It supports multiple logical groups of control data in the relay block. The collection of abandoned projects involves the partial elimination of blocks, and the valid data segments that may not have any relationship (random logical block address) are taken to the reconfigured blocks where there may already be some data. If the reconfigured block becomes full during operation, another block will be opened. Non-Sequential Update Block Index In the above paragraph on chaotic block indexing and in conjunction with Figures 6A-16E, the CBI section can be used to store an index that can record logical sector locations that are randomly stored in chaotic or non-sequential update blocks. . According to another aspect of the present invention, in a non-volatile memory having a block management system supporting an update block having a non-sequential logic unit, an index of a logical unit buffering a non-sequential update block stored in the RAM is Stored regularly in non-volatile memory. In a specific embodiment, the index is stored in a block dedicated to storing the index. In another embodiment, the index is stored in the update block. In yet another specific embodiment, the index is stored in the header of each logical unit. In another aspect, the logical unit written after the last index update but before the next index update stores its index information in the header of each logical unit. According to this, after the power supply is interrupted, it is not necessary to perform scanning during the initialization, and it is determined that the position of the logical unit to be written is taken. On the other hand, _, the block officially points to part of the sequence and part of the non-sequential point to more than one logical subgroup. 98704.doc 1288328 Index metrics for CBI segments stored in CBI blocks after a predetermined trigger event. According to the scheme described in connection with Figures 16A-16E, the list of recently written segments in the chaotic block is retained in the controller RAM. in. The CBI section containing the latest index information is written to the flash memory (CBI block 620) only after a predetermined number of writes to the logical group associated with the given chaotic block. In this way, the number of CBI block updates can be reduced. The list of recently written segments in the logical group is retained in the controller RAM before the next update of the CBI segment in the logical group. This list will be lost when the memory device encounters a power down, but can be rebuilt by scanning the update block during initialization after power is turned on. Figure 37 shows a scheduling example of writing a CBI section to an associated chaotic index section block after writing the same logical group every N sectors. This example shows two logical groups LG3 and LGn that are updated simultaneously. Initially, the logical segments of LG3 are stored in the original block in sequential order. Updates to logical segments in the group are recorded on the associated update block in the order specified by the host. This example shows a chaotic update sequence. At the same time, the logical group LGU is also updated in the same way as its update block. After each logical segment is written, its location in the update block is retained in the controller RAM. After each predetermined trigger event, the current index of the logical segment in the update block is written to the non-volatile hash index segment block in the form of a chaotic index segment. For example, a predetermined triggering event can occur after every N writes, where N is three. Although the examples provided are related to the logical unit of data as a section, those skilled in the art will appreciate that the logical unit can also be some other aggregate, such as a page containing a section or a group of sections. Also, the page 98704.doc -102-1288328 in the sequential block is not necessarily a logical page because the page mark that is wrapped around may be the first page. Index metrics for CBI segments stored in chaotic update blocks after a predetermined trigger event. In another embodiment, the index metrics are stored in the chaotic update block itself after every N writes. In the CBI section. This scheme is the same as the specific embodiment in which the index is also stored in the CBI section. The difference is that in the above specific embodiment, the CBJ sector is recorded in the CBI sector block, not in the update block itself. This method is based on keeping all chaotic block index information in the chaotic update block itself. 38A, 38B and 38C respectively show the state in which the updated blocks of the CBI section are also stored in three different stages. Fig. 38A shows an update block until a section is recorded therein after a predetermined number of writes. In this example, after the host has sequentially written to logical section 0-3, another version of the logic segment will be issued again, thus destroying the sequential sequence of data writes. The chaotic block index carried in the cBI section is then implemented to convert the updated block into a chaotic update block. As mentioned above, CBI is an index of the index of all logical sections containing chaotic blocks. For example, the second item represents the displacement of the update block of the third logical segment, and likewise, the nth item represents the displacement of the nth logical segment. The CBI section can be written to the next available location in the update block. In order to avoid frequent Shaanxi flash memory access, the cBI sector is written after every N data sectors are written. In this example, N is 4. If power is lost at this time, the last written segment becomes a CBI segment and this block is treated as a chaotic update block. 98704.doc 1288328 Figure 38B shows the update block in Figure 38 further recorded in logical segments 1, 2 and 4 after the index segment. Newer versions of logical sections and 2 replace the old versions previously recorded in the update block. In the case of a power cycle at this time, the last written segment must be found first, and then up to N segments must be scanned to find the last written index segment and the most recently written data segment. Figure 38C shows the update block of Figure 38B with another write to trigger the logical segment of the next record of the index segment. The same update block after the other N (N=4) sectors are written may record another current version of the CBI section. The advantage of this scheme is that there is no need for separate CBI blocks. At the same time, there is no need to worry about whether the additional data area of the physical flash zone is large enough to accommodate the number of items required for the index of the valid section in the chaotic update block. Then, the chaotic update block contains all the information, and the address translation does not require external data. This makes the algorithm simpler, which reduces the number of control updates for c B! block compression and also makes the serial control update shorter. (See above for [Μ Block Management"). "The information stored in the most recently written section of the data section header in the 9 random update block is in accordance with the invention. On the other hand, it will be recorded in the area ▲ after the mother N is written. The index of the early memory is stored in the non-volatile memory, and the current information about the intermediate write of the first and last 7L is stored in the additional item written in each logical unit.

,Knife. In this way, after the power is restarted, it is not necessary to scan the block; ^ p A _ _ ^ & the last part of the ghost that is written to the logical unit is fast

Get the information of the logical unit that has Μ δ U—the index is written after the update. Figure 3 9 Α display; at 1 1 /, stored in the chaotic update block in the header of each data section 98704.doc 1288328 intermediate index written. Figure 3 9B shows an example of storing an intermediate index of intermediate writes in each of the written & In this case, 丨φ, A are both x. After writing four segments LS〇-LS3 in the dry U, the (10) index is written as the τ_ segments in the block. Thereafter, the logical segments LS, LS'2, and LS4 are written to the block. Each time, the header stores the intermediate index of the logical unit of the person written since the last cm index. Therefore, the header in ls, 2 will have an index that provides the previous CBI index and its displacement (ie, position). Similarly, the header in LS4 will have the previous CBI index and 1^1 and 1^'2. The index of the displacement (ie, position). The last written data section will always contain information about up to N last written pages (ie, the CBI section up to the last write). As long as the power is restarted, the previous CBI index can provide the index of the uranium write of the logical unit in the CBI* lead section. § Hole, and the index information of the logical unit of the post-write can be written in the last written data area. Found in the header of the segment. This has the advantage that it is not necessary to scan the block for its subsequent writes at initialization to determine its position. The scheme of storing intermediate index information in the header of the data section is equally applicable regardless of whether the CBI index section is stored in the update block itself or in a separate CBI section block, as previously described. Index Indicators for Data Section Headers Stored in Chaotic Update Blocks In another embodiment, the entire CBI index is stored in the add-on portion of each data section in the chaotic update block. Figure 40 shows the information in the scrambled index block stored in the header of each data section of the chaotic update block. The section header has a limited amount of information, so the index range provided by any single section 98704.doc -105 - 1288328 can be designed as part of the hierarchical indexing scheme. For example, a section within a particular plane of memory can provide an index to a section that is only within that plane. There is also the ability to divide the range of logical addresses into sub-ranges to allow for an indirect indexing scheme. For example, if a segment with 64 logical addresses can be stored in a plane, each segment can have 3 blocks for the segment shift value, and each block can store 4 displacement values. The first stop can define the physical displacement of the last written segment within the logical displacement range 〇-15, 15-31, 32-47, and 48-63. The field column defines the entity displacement values for the four sub-ranges of each of the four segments within its associated range. The third blocker defines the entity displacement values for the four segments within its associated sub-range. Therefore, by reading the indirect displacement values of up to 3 segments, the physical displacement of the logical segments within the chaotic update block can be determined. The advantage of this scheme is that there is no need for separate CBI blocks or CBI sections. However, this only applies when the additional item data area of the physical flash segment is large enough to accommodate the number of items required for a valid segment index in a chaotic update block. Limited logical range within a logical group of chaotic update blocks Within a logical group, the logical range of segments that can be written out of order can be reduced. The main advantages of this technique are as follows: Since only one multi-session page needs to be read (in the multi-wafer example, 'the pages can be read in parallel'), all the destination pages can be obtained (assuming the source and destination) Aligned, if it is not aligned, then another read is required, so that the copy of the sequential write data can be completed more quickly, so the extents outside the range remain in the original block and the writes are discarded. The operation can be completed in a shorter time, using the complex terabar on the wafer & this feature, you can copy the sequential data from the source to the destination, instead of telling the story | crying day + 隹 control stolen Transfer data back and forth. If the source 98704.doc 1288328 枓 has been decentralized, as occurs in a chaotic block, then each segment needs to read up to one page to collect all the segments to be written to the destination. In the specific embodiment, the logical range is not actually limited to a certain amount of segments, but is completed by limiting the number of CBIs (only limiting the confusion of large groups/relay blocks is reasonable, Because it requires multiple chaotic block indexes to cover the entire logical group range). For example, if a relay block/group has 2048 segments, it will need up to M0CBI segments, each covering a contiguous logical range of 256 segments of a subgroup. If the number of cBIs is limited to 4, the chaotic block can be used to write up to 4 subgroups of any of the segments (any one of them). Therefore, the logical group is allowed to have up to 4 partial or complete chaotic subgroups, and at least 4 subgroups will remain fully sequential. If a chaotic block has 4 valid CBI segments associated with it, and the host writes segments outside of these CBI segments (chaotic subgroups), the chaotic logical groups should be summarized and closed. But this is highly unlikely, because in real applications, the host does not need more than 4 256 segments of chaos (subgroups) in the 2048 segment range (logical group). As a result, under normal circumstances, the collection of obsolete items will not be affected, but the precautions of the restriction rules form an extreme example of the waste collection being too long (which will trigger the host's timeout). Partially sequential chaotic update block index When a sequential update block is partially written before converting the block to the chaotic management mode, all or part of the sequential update segment of the logical group may continue to be processed to have been sequentially updated, And chaotic update management can only be applied to a subset of the address range of the logical group. Controlling Data Integrity and Management 98704.doc -107- 1288328 Data stored in a memory device may become corrupted due to a power interruption or a specific memory location becoming defective. If a memory block defect is encountered, the data is reconfigured to a different block and the defective block is discarded. If the error does not increase, the error can be corrected during execution by the error correction code (ECC) stored with the data. However, there will still be times when Ecc cannot be right to destroy the data. For example, when the number of error bits exceeds the valley. This is unacceptable for key information such as control information associated with the memory block management system. An example of controlling batting is catalog information and block configuration information associated with the memory block management system, as described in connection with Figure 2〇. As mentioned above, control data can be maintained in high speed RAM and slower non-volatile memory blocks. Any <RTI ID=0.0>>>><>>> In this way, the control data can be stored in a non-volatile, non-volatile version of the flash memory. As shown in Figure 2〇, (10), ΜΑ?, A control batting structure level will be maintained in the flash memory 匕 control write operation caused by the control of the data structure in the RAM can be updated in the flash, in the body The same control data structure. Key Data Backup In accordance with the $_th aspect of the present invention, if the key to some or all of the control data is maintained in the copy, the reliability of the material level is guaranteed. The technique uses the two-pass stylization technique to program the multi-state d-systems of the multi-bits of the ^^, , and In fact, 筮-4 for a long time, any stylized errors in the flat code process are 98704.doc 1288328 can not damage the data created by the first encoding process. Replication also helps detect write aborts, detect false positives (ie, two replicas have good ECC but different data) and can add additional levels of reliability. Several techniques for data replication have been considered. In a specific embodiment, after stylizing two copies of the shell material in the early stylized encoding process, the subsequent stylized encoding process can avoid stylizing the memory for storing at least one of the two copies. Body unit. In this manner, at least one of the two copies will not be affected when the subsequent stylized encoding process terminates and destroys the data of the earlier encoding process before completion. In another embodiment, two copies of a given material are stored in two different blocks, and at most only one of the two copies of the two copies will be It is stylized in the later stylized encoding process. In another embodiment, after storing two copies of a given data in a stylized encoding process, no further stylized cell groups are implemented to facilitate the storage of the memory cells of the two copies. This can be achieved by stylizing this in the final stylized coding process. . In the other embodiment, the two copies of the memory are programmed to program the two copies of a given material into the memory of the _multi-state in a binary stylized mode. This will not further stylize these programmed memory units. In yet another embodiment, the method uses a two-step stone program 98704.doc • 109-1288328 technique to continuously program a multi-bit memory system of the same group of memory cells. The fault-tolerant code is used to encode multiple memory states' so that the data created by the earlier stylized encoding process is not affected by errors in the subsequent stylized encoding process. The complexity of data copying can be caused in multiple state memories in which each memory unit can store more than one bit of data. For example, a 4-state memory can be represented by two bits 70. One prior art technique is to program this memory using a two-pass encoding process. The first bit (lower page bit) can be programmed by the first encoding process. Thereafter, the same unit can be programmed in the second encoding process to represent the desired second bit (upper page bit). In order not to k the value of the first bit in the second encoding process, the memory state representation of the first bit depends on the value of the second bit. Due to inflammation, during the stylization of the second bit, if it occurs due to power interruption or other reasons. Mistakes and *correct memory state, it will also destroy the value of the first bit. Figure 41 shows when each memory When the volume unit stores two bits of data, the threshold voltage distribution of the state memory array. These four distributions represent the total of four recorded figures 1-11, "again", "¥" and "2". Before stylizing memory 11 saponins, it will be erased to its "U" 3 Ge "unwritten" state. When the t-memory unit is gradually programmed, it will progressively reach the memory state "X" "Y" and "z". Park 4 1B shows the existing make

WWay code) 2 times Lin code recombination scheme. The four states can be represented by two bits, that is, the lower azimuth element and the upper page bit, such as (the upper page H, the lower page bit; for the parallelized stylized unit, actually There are two logics 98704.doc -110 - 1288328. The logical lower page and the logical upper page. The first - stylized encoding process: will program the logic below the page. With the appropriate encoding, there is no need to reset the logic below the page φ 'unit Subsequent second stylized encoding on the same page = will program the top page of the logic. The general code is Gray code, and only one of the bits will change when transitioning to the adjacent state. Therefore, this code The advantages are as follows: there are fewer requirements for error correction, since only one bit is involved. - The general scheme of using Gray code is to assume that "L stands for "unprogrammed" condition. Therefore, the erased memory state "u" Can be expressed as: (above page: 兀 'below page bit) = (1, 1}. In the first encoding process of the page below the stylized logic, any unit storing the "〇" will have its The logical state transition of (X,1) to (X,〇), where "X" represents the "don't care" value of the upper azimuth. However, since the upper azimuth element has not been %-formed, Consistently, "χ" can be marked as "]". (U) The logic can be represented by the stylized unit as the memory state "χ". That is to say, 'before the second program encoding process, the lower position The value "〇" can be expressed as the memory state "X". The second encoding process can be programmed to store the position of the page above the logic/, and the unit that needs the upper page bit value "〇". Will be programmed in the first person encoding process, the unit in the page in the logic state (1,1) or (,) in order to save the value of the lower page in the second encoding process, must be the area under the knife 7 ° value " 〇" or "i". For the transition from (1,0) to (0, 0), the 'single' unit is programmed into the memory state "Y". For (i, ) to (〇) The turn of '1) will be stylized into the memory state 98704.doc -111 - 1288328 state "z". In this way, during the reading process, the lower page bit and the upper page bit can be decoded by determining the memory state programmed in the cell. However, the 2 encoding process of the Gray code is programmed in the second pass. Stylized errors can become a problem. For example, if the lower position is 程式, the upper page bit is stylized as "G", which will cause (1, υ to (q 1), · This requires the memory unit to be progressively "U" is stylized through "χ" and "γ". To "Ζ". If a power interruption occurs before the stylization is completed, the memory unit will end in one of the transition memory states, such as "χ". When the memory unit is read, "X" is decoded into a logic state (1, 〇). This causes an incorrect result for the upper and lower orientation elements, since it should be (^). Similarly, if the stylization is interrupted when it reaches "Υ", it will correspond to (0, 〇). Although the upper position is correct now, the lower position is still wrong. Therefore, it can be seen that the stylized problem of the above page can damage the data already on the next page. In particular, when the second encoding process is programmed to pass through the intermediate memory state, the program abort causes the stylization to end in the memory state, resulting in an incorrectly decoded lower page bit. _ Figure 42 shows how to protect critical data by storing replicated sections. For example, sections A, B, c, and 〇 can be stored in a duplicate copy. If there is data corruption in a copy of a section, you can read the other to replace it. Figure 43 shows the unsoundness in which the copy segments are typically stored in multiple state memories. As described above, in the exemplary 4-state memory, the multi-state page includes a logical lower page and a logical upper page which are respectively programmed in the two encoding processes. In the example shown, the page is four zones and the segments are wide. Therefore, the section Α and its copy are simultaneously stylized in the logical lower page 98704.doc -112 - 1288328, as well as for section B and its copy. Then, in the subsequent stylized second encoding process in the logical upper page, the segments C, C are also programmed simultaneously, as well as for the segments D, D. If a program abort in the middle of the stylized section C, C will destroy the section A, A in the page below. Unless the page section below is read and buffered before the top page is stylized, the damage will not be restored. Therefore, storing a copy of two key data at the same time, such as section A, A, cannot prevent it from being damaged by the problematic storage of subsequent sections C, C in its upper page. Figure 44A shows a specific embodiment of storing a copy of a key staggered copy to a multi-bear memory. Basically, the lower page, that is, the segments A, A and the segments B, B, are stored in the same manner as in FIG. However, in the upper page stylization, sections C and D are interleaved with c, d, c, d. If local page stylization is supported, the copies of the two segments c can be programmed simultaneously, as well as for the duplicates of the two segments D. If the program for the two segments c is aborted, only the next page is destroyed on one copy of the segment eight and one copy of the segment B. Another copy will remain unaffected. Therefore, if there are two copies of the key data stored in the first encoding process, it will not be affected by the simultaneous stylization of the subsequent second encoding process. Figure 44B shows another embodiment of storing only a copy of the key material to a logically above page of the multi-state memory. At this time, the information on the page below is not used. Key data and its copy, such as section A, A and section B, B will only be stored to the logical upper page. In this way, if there is a program abort, the key data can be written to another logical upper page, and any damage to the next page data will not matter. This approach basically uses half of the storage capacity of each 98704.doc • 113 - 1288328 multi-state page. Figure 44C shows a further embodiment of a duplicate copy of a key material stored in a binary mode of multiple state memory. At this point, each memory unit is programmed in binary mode, which is only limited to the time: two & fields. Therefore, only the -coding process is stylized, and stylization can be restarted in different locations when the occurrence of the program is aborted. This method also uses each multi-state page - half the storage capacity. The operation of the multi-state memory system in binary mode is described in U.S. Patent No. M 56,528, the entire disclosure of which is incorporated herein by reference. Figure 45 shows yet another embodiment of simultaneously storing a copy of the key material to two different relay blocks. If one of the blocks becomes unavailable, then the data can be read from another block. For example, key data is contained in sections A, B, C, D and E, F, G, HAI, Bu K, L. Each section will be stored in the copy. These two copies will be written to two different blocks, block 0 and block 1. If you write a copy to the lower logical page, another copy is written to the logical upper page. In this way, there will always be a copy of the page that is stylized to the top of the logic. If a program aborts, it can be reprogrammed to another logical top page. At the same time, if the next page has been damaged, there will always be another upper page copy in other blocks. Figure 46B shows yet another embodiment of a duplicate copy of a key material stored simultaneously using a fault tolerant code. Figures 46A and 41A show the limited voltage distribution of the 4-state memory array and are shown as a reference to Figure 46B. Tolerantly, any upper page program that can be transitioned in any intermediate state can be avoided. 98704.doc -114- 1288328. Therefore, in the first encoding process of the next page, the logic state (1, 1) changes the rabbit μ fishing (1, 〇), as the memory state "U" expressed as stylized erased is "γ". In the second encoding process where the upper page bit is "〇", if the page bit below the + π is "1", the logic state (1, transition to (0, 1), such as矣-& ... The table is not the erased erased memory state "U" is "XI. If you want ^, the square page bit is "〇", then the logic state (1, 〇) is changed to (〇 , 0) 'If the stylized memory state Γ γ' is "z". Since the page stylization only involves stylizing into the next adjacent memory state, the program abort cannot change the lower page bit. The copy of the key > material is preferably written as described above. Another way to avoid both depreciation of the two copies is to write the copy sequentially. This method is slower, and the copy itself represents two checks on the controller. Stylized success at the time of the copy. Figure 47 shows the possibility of two copies of the data. Table of status and data validity If the first and second copies do not have an ECC error, the stylization of the data can be considered to be completely successful. Valid data can be obtained from either copy. If the first copy does not have an ECC error, but the second If the copy has an ecC error, it means that the stylization is interrupted in the middle of the stylization of the second copy. The first copy has valid data. Even if the error is correctable, the second copy is unreliable. If the first copy has no ECC error and The second copy has been emptied (erased), indicating that the stylization was interrupted after the end of the first copy stylization but before the start of the second copy 98704.doc -115- 1288328. The first copy contains valid material. If the first copy If there is an ECC error and the second copy has been emptied (erased), it means that the normalization is interrupted in the middle of the first replica stylization. Even if the error is correctable, the first replica still contains invalid data. The following techniques are preferred because they utilize the existence of duplicate copies. Read and compare two copies. In this example, the two copies shown in Figure 47 The state can be used to ensure that there are no false positives. In another embodiment, the controller reads only one copy, and in order to account for speed and simplicity, the replica read is preferably rotated between the two replicas. When the controller reads the control data, it can read the copy, the next control read (any control read) should come from the copy 2, and then the duplicate ^^ in this way, you can continue and Regularly check the integrity of the two copies (ecc is checked), which reduces the risk of not being able to detect in time errors caused by deteriorating data retention. For example, if you normally only read duplicate 1, then copy 2 will gradually deteriorate to the extent that the error cannot be saved by the ECC, and the second copy can no longer be used. Preemptive data reconfiguration As described in connection with Figure 20, the block management system can be in flash memory during its operation. Maintain a set of control data. This group of control data is stored in the same relay block as the host data. As a result, the control data itself is subject to block management and is therefore subject to updates and, therefore, to the waste collection operations. It also describes the hierarchy of control data, where the control data in the lower level is updated more frequently than in the higher level. For example, assuming that each control block has ^^ 98704.doc -116 - 1288328 control segments to be written, the following sequence of control updates and control block reconfigurations typically occurs. Referring again to Figure 20, every N CBI updates can fill the CBI block and trigger CBI reconfiguration (rewrite) and MAP updates. If the chaotic block is closed, it will also trigger a GAT update. Each GAT update can trigger a MAP update. Each N GAT update fills the block and triggers the GAT block reconfiguration. In addition, when the MAP block becomes full, it also triggers the MAP block reconfiguration and the MAPA block (if it exists, otherwise the BOOT block points directly to the MAP). In addition, when the MAPA block becomes full, MAPA block reconfiguration, BOOT block update, and MAP update are also triggered. In addition, when the BOOT block becomes full, it will trigger the BOOT block reconfiguration in the action of another BOOT block. Since the formation of the hierarchy is: the top BOOT control data, followed by MAPA, MAP, and then GAT, therefore, in every N3 GAT updates, there will be "serial control update", in which all GAT, MAP, MAPA and BOOT The block will be reconfigured. In this case, there is also an obsolete item collection operation (ie, reconfiguration or rewriting) when the GAT update is caused by a chaotic or host update block closure due to host writes. In the case of a collection of obscure update blocks, the CBI is updated, which also triggers CBI block reconfiguration. Therefore, in this extreme case, it is necessary to collect a large number of discarded items of the relay block at the same time. As can be seen from the figure, each control data block of the hierarchy has its own periodicity in obtaining padding and accepting reconfiguration. If each control data block is normal, then the following situation will occur: the stage of a large number of blocks is reorganized, thus triggering a large number of reconfiguration wastes involving all of these blocks at the same time. 98704.doc -117- 1288328 Abandonment project collection. The reconfiguration of many control blocks can take a long time and should be avoided because some hosts do not tolerate long delays due to a large number of control operations. According to another aspect of the present invention, in a non-volatile memory having a block management system, a memory block can be implemented to control the collection of waste items or a preemptive reconfiguration to avoid a large number of update blocks. It happens that you need to reconfigure at the same time. This can happen, for example, when updating control data that is used to control the operation of the block management system. The hierarchy of control data types can coexist with varying degrees of update times, causing their associated update blocks to require collection or reconfiguration of obsolete items at different rates. There will be more than one specific number of simultaneous acquisitions of the obsolete items that control the data type. In extreme cases, the reconfiguration phase of all update blocks of the control data type is reorganized, causing all update blocks to be reconfigured at the same time. The present invention avoids this undesirable situation where current memory gymnastics can accommodate spontaneous waste collection operations at any time, and preemptive reconfiguration of update blocks can occur before the block is fully populated. In particular, 'priority will be provided to the block with the highest level data type of the slowest rate. In this way, after reconfiguring the slowest rate block, another relatively long period of obsolete item collection will no longer be needed. . Also, there is not much configurable reconfigurable concatenation of the 忮 rate block in the hierarchy.视为 Think of this method as a way to introduce some kind of jitter into the overall mixture of things in order to avoid the alignment of the various blocks in the discussion. Therefore, as soon as there is an opportunity, it is possible to reconfigure some of the slightly-filled blocks that are not completely filled with the margins of 98704.doc 1288328. In systems where the lower control data in the hierarchy becomes faster than the control data hierarchy of the higher control data in the hierarchy due to the concatenation effect, the priority is provided to the higher control data blocks in the hierarchy. An example of an opportunity to perform a spontaneous preemptive reconfiguration is when the host write itself cannot trigger a reconfiguration, so any pre-remaining time in its wait time can be utilized for preemptive reconfiguration. In general, the margin before the block that must be reconfigured is the predetermined number of unwritten memory cells before the block is full. What is considered is a margin sufficient to accelerate the reconfiguration before the fully populated block, but not too early, to avoid wasting resources. In a preferred embodiment, a predetermined number of unwritten memory cells are between one and six memory cells. Figure 48 is a flow chart showing the memory block of the preemptive reconfiguration storage control data. Step 1202 • Organize non-volatile memory into blocks, each of which has been divided into memory cells that can be erased together. Step 1204: Maintain different types of data. Step 1206: Assign a hierarchy to different types of data. Step 1208: Store updates of the different types of data in the plurality of blocks such that each block substantially stores the same type of data. Step 1210: • In response to a block having less than a predetermined number of empty memory cells and having the highest hierarchical data type of the plurality of blocks, the current update of the data for the block is reconfigured to another block. If it is not interrupted, go to step 1208. 98704.doc -119- 1288328 The example algorithm for implementing preemptive reconfiguration of the uncontrolled data in Figure 20 is as follows: If ((there is no collection of obsolete items due to user data) or (MAP has 6 or Less unwritten segments) or (GAT leaves 3 or fewer unwritten segments) If (BOOT leaves 1 unwritten segment) then reconfigure BOOT (ie, reconfigure to Block) No Bay ij If (MAPA has 1 unwritten section)

Then reconfigure MAPA and update MAP No Bay J if (MAP has 1 unwritten segment)

Then reconfigure MAP No Bay U if (the last update or the largest GAT has 1 unwritten segment)

Then reconfigure GAT No. If (CBI leaves 1 unwritten section) then reconfigure CBI No Bayu Otherwise leave, therefore, preemptive reconfiguration is usually completed without any use of 98704.doc 1288328 When the abandoned project is collected. In the worst case, when each host write triggers the collection of user data obsolescence items, but there is still enough time to perform a spontaneous reconfiguration of a block, a preemptive re-execution of a control block can be performed at a time. Configuration. Since the user data collection item collection operation and the control update may occur simultaneously with the entity error, it is preferable to have a large security margin by using 2 or more unwritten in the block as before. In the case of a memory unit (eg, a segment), the collection of obsolete items for preemptive reconfiguration or control is performed first. While the various aspects of the invention have been described with respect to the specific embodiments, it is understood that the invention is intended to be protected by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view showing the main hardware components of a memory system suitable for implementing the present invention. Figure 2 shows the date and time according to this issue.

A preferred embodiment of the month is organized into segments (or relay blocks) of the entity 耳 ear group and is the memory managed by the controller's memory manager. Figure 3(1)-3A(U1) shows a mapping between logical groups and relay blocks in accordance with a preferred embodiment of the present invention. Figure 3B shows a schematic diagram of the mapping between a logical group and a relay block. Figure 4 shows the alignment of the structure in the relay block and the real ® A 1:3⁄4 body. Figure 5A shows the block from the link. A relay composed of a ten-sided minimum erasing unit 98704.doc -121 - 1288328 ^ A specific embodiment in which a minimum erasure order from a plane to a relay block is made. Figure 5C shows another embodiment in which more than one MEU is selected from each direction to link to a relay block. Figure 6 is a block diagram of a relay block management system implemented in a controller and flash memory. Figure 7Α shows an example of writing a segment of a logically updated block in a sequential order in a logical group. Figure 7 shows an example of a segment of a chaotic update block written in a chaotic order in a logical group. Figure 8 shows an example of writing a segment of a sequentially updated block in a logical group in sequential order due to two separate host write operations with interrupts at logical addresses. Figure 9 is a flow diagram of a program for updating the data of a logical group for displaying an update block manager, in accordance with a general embodiment of the present invention. Figure 10 is a flow diagram showing the flow of updating the data of a logical group by the update block manager in accordance with a preferred embodiment of the present invention. Figure 11 is a flow chart showing in detail a summary procedure for closing the chaotic update block shown in Figure 10. Figure 11B is a flow chart showing in detail the compression procedure for closing the chaotic update block shown in Figure 1A. Figure 12A shows all possible states of a logical group, with possible transitions between various operations. Figure 12B is a table listing the possible states of a logical group. 98704.doc • 122- 1288328 Figure 13A shows all possible states of a relay block and their possible transitions under various operations. A relay block is an entity group corresponding to a logical group. Figure 13B is a table listing the possible states of a relay block. 14(A)-14(J) are state diagrams showing various operational effects on the logical group state and on the physical relay block. Figure 15 shows a preferred embodiment of an Configuration Block List (ABL) structure for recording the open and closed update blocks and the configured erased blocks. Figure 16A shows the data field of the Chaotic Block Index (CBI) section. Figure 16B shows an example of a Chaotic Block Index (CBI) section recorded in a dedicated relay block. Figure 16C is a flow diagram showing the access to the logical section of a given logical group for a chaotic update. Figure 16D is a flow diagram of data for a logical section of a given logical group for performing a chaotic update based on an alternative embodiment in which a logical group has been partitioned into subgroups. Figure 16E shows an example of a Chaotic Block Index (CBI) section and its functions in a specific embodiment in which each logical group is partitioned into a plurality of subgroups. Figure 17A shows the data field of the Group Address Table (GAT) section. Fig. 17B shows an example of a group address table (GAT) section recorded in a GAT block. Figure 18 is a schematic block diagram showing the distribution and flow of control and catalog information for the use and recycling of erased blocks. Figure 19 is a flow chart showing the physical address translation logic program. Figure 20 shows the operational hierarchy performed on the control profile 98704.doc -123 - 1288328 during the memory management operation. Figure 21 shows an array of memories constructed with multiple memory planes. Figure 22A shows a flow chart of a method with planar alignment updates in accordance with a general embodiment of the present invention. Figure 22B shows a preferred embodiment of the step of storing updates in the flow chart shown in Figure 22A. Fig. 23A shows an example of a logical unit that writes a person sequentially updating blocks in a sequential order regardless of plane alignment. Figure 23B shows an example of a logical unit that writes a chaotic update block in a non-sequential order, regardless of plane alignment. Figure 24A shows an example of a sequential update of Figure 23A with planar alignment and padding in accordance with a preferred embodiment of the present invention. Figure 24B shows an example of a chaotic update of Figure 23B with planar alignment and without any padding in accordance with a preferred embodiment of the present invention. Figure 24C shows an example of a chaotic update of Figure 23B with planar alignment and padding in accordance with another preferred embodiment of the present invention. Figure 25 shows an example memory organization in which each page contains two memory cells for storing two logical units (e.g., two logical segments). The memory structure of Fig. 26A and Fig. 26 is the same except that each page contains two sections instead of one. Fig. 26B shows a relay block having the memory cells arranged in a line graph as shown in Fig. 26A. The alternative shown in Figure 27 is as follows: Plane alignment can be performed in the update block without filling the logical unit to be copied from one location to another. 98704.doc -124- 1288328 Figure 28 shows a scenario in which a defective block repeats the rollup operation on another block when a program failure occurs during the rollup operation. Figure 29 is a schematic diagram showing a host write operation with a timing or write latency that allows sufficient time to complete the write (update) operation and the summary operation. Figure 30 is a flow diagram showing the failure of a program in accordance with the general scheme of the present invention. Figure 31A shows a specific embodiment of a program failure handling in which the third (last reconfiguration) block is different from the second (interrupt) block. Figure 3B shows another embodiment of a program failure handling in which the third (last reconfiguration) block is the same as the second (interrupt) block. Figure 32A shows a flow chart for the initial update operation that caused the summary operation. Figure 32B shows a flow chart of a multi-stage summary operation in accordance with a preferred embodiment of the present invention. Figure 33 shows an example sequence of the first and final stages of a multi-stage rollup operation. Fig. 34A shows an example in which the interrupt summary block is not used as an update block but as a summary block whose summary operation has been interrupted. Figure 34B shows the third and final stages starting from the multi-stage summary of Figure 34A. Fig. 35A shows an example in which the interrupt summary block is maintained as a newer block written by the receiving host instead of the summary block. Figure 35B shows the third and final stages starting from the multi-stage summary of Figure 35A in the second example. Figure 36A shows a phased program error handling method for the case where the host write triggers the shutdown of the update block and the update block is sequential. 98704.doc -125- 1288328 Figure 36B shows a phased program error handling method applied to the (local block system) in the updated instance of the update block. Figure 36C shows a staged program error handling a discarded item collection operation, or a cleanup in a memory block management system that does not support a logical group mapped to a relay block. Figure 37 shows an example of the scheduling of writing a cbI sector to an associated chaotic index sector block after writing the same logical group every N sectors. Fig. 3A shows the update block until the discrimination section is recorded therein after a predetermined number of writes. Figure 38B shows the update block of Figure 38A in which the data pages 1, 2 and 4 are recorded after the index section. Figure 38C shows the update block of Figure 38B with another write to trigger the logical segment of the next record of the index sector. Figure 39A shows the intermediate index written between the headers of the data sectors stored in the chaotic update block. Figure 39B shows an example of storing an intermediate index of intermediate writes in each of the sector headers written. Figure 40 shows the information in the hash index field stored in the header of each data section of the chaotic update block. Fig. 41A shows the threshold voltage distribution of the bucket state memory array when each memory cell stores data of two bits. Fig. 41B shows a prior art encoding process scheme using the Gray code ((4) code). Figure 42 shows the sections copied by the memory to defend (4) data μ 98704.doc -126 - 1288328. For example, sections A, B, C, and 〇 can be stored in a duplicate copy. If there is data corruption in a copy of a section, you can read the other to replace it. Figure 43 shows the unsoundness in which the copy segments are typically stored in multiple state memories. Figure 44A shows a specific embodiment of storing memory copies of key data staggered into multiple states. Figure 44B shows another embodiment of a page that only stores a copy of the key material in a logically above page of the multi-state memory. Figure 44C shows yet another embodiment of a duplicate copy of a key material stored in a binary mode of multiple state memories. Figure 45 shows yet another embodiment of simultaneously storing a copy of the key material to two different relay blocks. Figures 46A and 41A show the limited voltage distribution of the 4-state memory array and are shown as a reference to Figure 46B. Figure 46B shows yet another embodiment of a duplicate copy of a key material stored simultaneously using a fault tolerant code. g Figure 47 is a table showing the possible status of two copies of data and the validity of the data. Figure 48 is a flow chart showing the memory block of the preemptive reconfiguration storage control data. [Main component symbol description] 1 Defective block 2 Interrupt block, 3 Reconfigured block 98704.doc • 127- 1288328 10 Host 20 Memory system 100 Controller 110 Interface 120 Processor 121 Selective secondary processor 122 Read only Memory (ROM) 124 Selective Programmable Non-Volatile Memory 130 Random Access Memory (RAM) 132 Cache Memory 134, 610 Configuration Block List (ABL) 136, 740 Clear Block List (CBL) 140 Logical Pair Physical Address Translation Module 150 Update Block Manager Module 152 Sequential Update 154 Chaotic Update 160 Erasing Block Manager Module 162 End Block Manager 170 Relay Block Link Manager 180 Control Data Interchange 200 Memory 210 Group Address Table (GAT) 220 Chaotic Block Index (CBI) 230, 770 Erased Block List (EBL)

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MAP erased ABL block list open update block list associated original block list closed update block list erased original block list CBI block logical group original relay block chaotic update block MAP Block Erasing Block Management (EBM) Section Available Block Buffer (ABB) Erased Block Buffer (EBB) Cleared Block Buffer (CBB) MAP Section Source MAP Section Destination MAP section plane read and program circuit page controller buffer data bus -129-

Claims (1)

1288328 X. Patent Application Range: u A method for storing and updating bacon in a non-volatile memory organized into blocks, wherein each block has been divided into memory units that can be erased together, each memory The body unit is configured to store data of a logical unit, the method comprising: organizing the data into a plurality of logical groups, each logical group is a group of logical units; receiving host data encapsulated in the logical unit; a first-order, storing a first version of a logical unit of a logical group in a first block; and a second sequence different from the first-order, including a subsequent version of the logical unit The most exclusive version of the logical unit is stored in the second block; and in response to the predetermined trigger event, the record of the logical unit stored in the second block after storing the latest trigger event in a third block. The method of claim 1, further comprising: providing a header portion for each logical unit; and storing the intermediate logic unit in the first logical event unit after the predetermined event is triggered The directory of the intermediate logical units is stored in the unit's traitor. 44. The method of claim 1, wherein the non-volatile memory has a memory unit. Pre-action gate 4 · If the method of claim 1 is used, the basin is made of the non-volatile memory system as fast as 98704.doc 1288328 BhFKOM 5 · such as a month for the item 1 square, +. , ' 'eight non-volatile The sexual memory system is NROM. 6. The method of claim 1, wherein the non-volatile memory system is in a memory card, wherein the method of any one of claims 1 to 6, wherein the non-volatile memory ...a memory unit that stores one bit of data. 8. The method according to any one of claims 1 to 6, wherein the non-volatile memory 2 has a memory unit of data of each storage-bit. In the non-volatile memory organized into blocks, the method for storing and more complicated materials: wherein each block has been divided into memory cells that can be erased, and each memory cell is used for Storing a logical unit of data, the method comprising: , , data (4) into a plurality of logical groups, each logical group is a group of logical units; receiving host data encapsulated in the logical unit; according to a first order Storing a version of the logical unit in a tenth member block; and in accordance with a first order of the logical unit, in a second block including the , The latest update of the storage logic unit; and = response-predetermined trigger event, which is stored in the available block f of the second block, and is stored in the second block after the latest trigger event. A directory. 10. The method of claim 9, further comprising: 98704.doc 1288328 providing a header portion for each logical unit; and an intermediate logic unit stored in the second block after a predetermined predetermined trigger event A directory of the intermediate logical units is stored in the header portion of each of the intermediate logical units. The method of claim 9, wherein the non-volatile memory has a floating gate memory cell. 12. The method of claim 9, wherein the non-volatile memory system is flash EEPR 〇m 〇 13. The method of claim 9, wherein the non-volatile memory system is m. 14. The method of claim 9, wherein the non-volatile memory system is in a memory card. A method of requesting a js + +, _l u shell in items 9 to 14, wherein the non-volatile memory has a memory unit each storing one bit of data. The method of any one of claims 9 to 14, wherein the non-volatile memory has a memory unit each storing more than one bit of data. π - seeding - organized into blocks (4) methods of storing new data in volatile memory poems, J: Zhong Jiu F said that a, /, middle & blocks have been divided into memorable units that can be erased together, Each memory unit is used for storing a logic unit' method comprising: ^ ^ storing a logic unit in a first block; in response to a trigger event, storing in a beta knife of the non-volatile memory a directory of logical units in the first block. Provides a header portion for each logical unit; &, 'between 98704.doc 1288328 stored in the block after the latest scheduled event The logical unit, stores the directory of the intermediate logic unit of the 3H Temple in the header portion of each of the intermediate logic units. Storage 18. As requested in item 17 of the pole memory unit. ...the non-volatile memory has a floating gate 19. The non-volatile memory system in the request item 17 EEPROM ' ' ' is flashing 20. If the request item 17 is the same as 21. The party of claim 17; the non-volatile memory The system is a method of taking 。M., in the card, the non-volatile memory system in a memory 22. The method of claim 17 to 21 τ 1 , wherein the non-volatile body has a storage epoch - A memory unit that owes a 贝U 疋 贝 23 23 23 23 23 · · · · 如 · · 如 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 24.= A method for storing and morphing in a non-volatile memory organized into blocks. Each of the blocks has been segmented into a memory that can be erased. The memory cells are used for storage. a data of a logical unit, the method comprising: organizing data into a plurality of logical groups, each logical group being a group of logical units; receiving host data encapsulated in the logical unit; according to a first order, a logical block in a block-block a first version of the element; and storing a newest 98704.doc 1288328 version of the logical unit in a second block comprising subsequent versions of the logical units in a second order different from the first order; And a header portion of each logical unit; and storing the catalogue in the header portion of each logical unit stored in the second block. The logic unit stored in the second block. 2 5 · The method of claim 2, wherein the non-volatile memory has a floating gate memory unit. 26. The method of claim 24. The non-volatile memory system is a flash EEPROM. 27. The method of claim 24, wherein the non-volatile memory system is a dish (10). 28. The method of claim 24, wherein the non-volatile The memory system is in a memory card. 29. The method of any one of items 24 to 28, wherein the body has a memory unit that stores data of one bit, wherein the non-volatile memory 3 0. 24 to 28 A method of singularity, +^, and month 5, wherein the non-volatile memory has a memory unit each storing more than one dollar of data. 3 1 · - a type of tissue in a block The method for storing and changing materials in a non-volatile memory, wherein each block is divided into a memory unit that can be erased, and each memory unit is used to store data of a logic unit, and the method includes : arranging the tribute into a plurality of logical groups, each logical group is a group of logical units; receiving host data encapsulated in the logical unit; storing one in a first block according to a first order Logical group 98704.doc 1288328 a first version of the logical unit; and root 糠 - second order, in the second area of the spoon - it s stomach; f π # ^ subsequent versions of the logical unit store the logical unit曰The logical mask elements are presented with a new version, wherein the stored groups and sums;;: the first subgroup in the same order as the first order = the second subgroup = the second subgroup; and the album = maintain this part of the volatile memory Section two sub-groups of the early 7L logic of a directory. 32. The method of claim 31, wherein the method is a memory cell. m------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Take (10). The method of the Japanese Patent No. 3 1 wherein the non-volatile memory system is in a memory card. < 36. The method of any one of claims 31 to 35, wherein the non-volatile memory has a memory unit each storing data of one bit. 37. The method of any of clauses 31 to 35, wherein the non-volatile memory has a memory unit each storing more than one bit of data. 98704.doc