TWI272487B - Non-volatile memory and method with memory planes alignment - Google Patents

Abstract

A non-volatile memory is constituted from a set of memory planes, each having its own set of read/write circuits so that the memory planes can operate in parallel. The memory is further organized into erasable blocks, each for storing a logical group of logical units of data. In updating a logical unit, all versions of a logical unit are maintained in the same plane as the original. Preferably, all versions of a logical unit are aligned within a plane so that they are all serviced by the same set of sensing circuits. In a subsequent garbage collection operation, the latest version of the logical unit need not be retrieved from a different plane or a different set of sensing circuits, otherwise resulting in reduced performance. In one embodiment, any gaps left after alignment are padded by copying latest versions of logical units in sequential order thereto.

Description

1272487 IX. Description of the invention: [Technical field to which the invention pertains] Memory, in particular, has a conductor memory. The present invention generally relates to a non-volatile semi-volatile memory of a non-volatile semiconductor memory block management system. [Prior Art] This is a solid-state memory that can be used for non-volatile storage, especially for small-sized card readers and EEPRqm. The form of the flashing (10) , has recently become a storage device for a variety of mobile and handheld devices, in particular: electricity and consumer electronics. Unlike the compilation of solid-state memory (with the exception of memory), the flash memory system is non-volatile and retains its stored data even after the power is turned off. Also, it is not like the job (only reading 夬 夬 flash memory and disk storage device - all can be rewritten. Although: = car and two 彳 - in the big memory application 'flash memory use Increasingly. Based on rotating magnetic media, the feathers, and white storage devices, such as hard disk drives and soft 'discomfort' and swaying and handheld environments. This is because the disk drive tends to be bulky. Faults with high latency and high power requirements. These unwanted attributes make disk-based storage devices inaccessible for large mobile and portable applications. On the other hand, they are both inline and Leica. The flash memory in its form is ideally suited for mobile and handheld environments due to its small size, power-eliminating, high-speed performance, etc. η Crime writes or both flash EEPROM and EEpR〇 The similarity between M (electronic erasable and programmable:) is that it is a non-volatile memory that can be erased and can be used to convert new data into its memory unit. 98680.doc 1272487 In the field effect transistor structure, the bit is in the semiconductor substrate A floating (unconnected) conductive gate above the region and between the source and drain regions. A control gate is then provided over the floating closed pole. The amount of charge retained by the floating gate controls the limits of the transistor. Voltage characteristics. That is to say, in terms of the charge on the floating gate, the corresponding electric charge (limit) must be applied to the control gate before the transistor is "on" to allow its source and Conduction between the drain regions. In particular, flash memory such as flash erase (10) allows the entire block of memory cells to be erased at the same time. - The floating gate can maintain a certain charge range and, therefore, can be programmed into The limit voltage window (4) is the limit voltage level. The size of the limit voltage (4) is limited by the minimum and maximum limit of the device, and the minimum and maximum of the device: the limit level (4) can be programmed to the floating gate The range of charge on the pole. The limit window is generally determined according to the memory device (four), operating conditions and records. The original ^ in this south, each has a different, resolvable constant limit power; 1 position can be used Clear memory state in the specified unit The Tongshi will use the two mechanisms to program the transistor as a memory unit into a "programmed" & state. In "hot electron injection", apply;; and the same voltage of the pole It can accelerate the electrons across the channel area of the substrate. At the same time, the high voltage applied to the control idle pole can attract the hot electrons to ride the electricity to the floating gate through the thin air. The substrate % plus - south voltage is applied to the control gate. In this way, the electrons of the substrate can be attracted to the intermediate floating gate of the floating gate. Although it is customary to use the term "stylized, the description is by injecting electrons into the memory unit. The phase erases the charge-storing unit to write to the memory to change the state of the memory... See the more common terms, 98680.doc 1272487 for "write" or "record" exchange. The following devices can be used to erase the memory device. For the EEPROM, by applying a high voltage to the control gate, the substrate is induced to induce electrons in the floating gate to tunnel a thin oxide into the substrate channel region (ie, Wear and effect) can erase a memory unit. In general, eepr〇m can be erased on a byte by byte basis. For flash EEPROM, all memory can be erased every time or erased each time - more than one minimum erasable block 'where the smallest erasable block may be more than one area The segment, the sum, and the parent segment can store more than 5.2 bytes. The memory device typically includes more than one that can be mounted on a memory card. L, body tablets. Each memory chip includes a memory cell array supported by peripheral circuits such as decoders and circuits such as erase, write, and read. The more sophisticated memory (4) is accompanied by a controller that performs intelligent and higher-order memory operations and interface connections. There are many commercially available non-volatile solid state memory devices available today. These memory devices may be flash EEPROM or other types of non-volatile memory cells may be used. Examples of flash memory and systems and methods for fabricating the same are disclosed in U.S. Patent Nos. 5, G7M32E, 5, G95, 344, 5, 315, 541, 5, 343, G6, 仏 (6), 5, 3i3. , 42i, and 6,222,762. Specifically, the device of the hexagram structure with the structure of the celestial string is described in US Patent Nos. 5, 57, 3, $5, 9, 3, 495, and M46, 935. . Alternatively, a non-volatile memory 98680.doc 1272487 body device can be fabricated using a memory cell having an interface layer for storing charge. It replaces the previously described conductive floating via 70 with a dielectric layer. Such memory devices utilizing dielectric storage elements have been described by Ehan et al. in U.S.A., U.S.A., IEEE m. 〇nw, vol. 21, No. 11, pp. 543-545. :AN〇vei Localized Trapping,2-Bit N〇nv〇UtUe Mem〇"(10)" in the article, the 0N0 dielectric layer will extend across the source and the non-polar diffusion interval, and the charge of one of the bayonet bits will The dielectric layer near the drain is localized, and the charge of the other data bit is localized in the dielectric layer near the source. For example, U.S. Patent Nos. 5,768, 3% and 6,01 U 725 disclose a non-heroic (four) cell that traps a dielectric between two layers of dioxide dioxide. Multiple state data storage can be achieved by separately reading the binary state of the charge storage region separated by the space within the dielectric. To improve read and program performance, multiple electrical storage elements or memory transistors in the array are read or programmed in parallel. Therefore, the memory element (4) "page" will be read or programmed together. In an existing memory shelf, the '-column usually contains a number of interlaced pages or a column to form a page. All memory elements on one side will be read or programmed. In flash memory systems, erase operations may require orders of magnitude greater than read and program operations. Therefore, it is desirable to have a large size erase block. In this way, it is possible to reduce the total number of memory cells

Wipe time. W According to the nature of the flash memory, the data must be written to the erased memory location. If you want to update the data of a specific logical address of the host, the way 98680.doc 1272487 is to write the updated data to the same physical memory location. That is, recycling, which is ideal for the limited durability of this type of memory device. ° " Children, the logic does not change the mapping of the location of the body. However, this means that the entire erase block containing the physical location must be erased before being written with the updated data. This update method is inefficient 'because it needs to erase and rewrite the entire erase block, especially if the data to be updated only occupies a small portion of the erase block. In addition, it will cause more frequent memory block erase. Another problem with managing flash memory systems is that system control and directory data must be processed. This data is generated and accessed during the course of various memory operations. Due to &, its efficient processing and rapid access will directly affect performance. Since flash memory is used for storage and is non-volatile, it is desirable to be able to maintain this type of data in flash memory. However, because there is an intermediate file (four) system between the controller and the flash memory, it is impossible to directly access the feed control system and the catalog data tends to become active and become a segment' and this has a large size zone. Storage in a block erase system is not helpful. As is customary, this type of material is set in the (four) RAM, thereby allowing direct access by the controller. After the power of the memory device is turned on, the 'initialization program scans the flash memory' to compile the necessary system control and directory information to be placed in the controller Ram. This procedure is both time consuming and requires control state RAM. 'For the ever-increasing flash memory capacity, this is even more. US 6,567,307 discloses a method for processing sector updates in a large erasure block' which is included in multiple The erased block of the available memory area records the more 98880.doc -10- 1272487 new data 'and finally summarizes the valid sections in various blocks, and then rearranges the valid sections in logical sequential order before writing them . In this way, it is not necessary to erase and rewrite blocks at each of the tiniest updates. Both WO 〇 3/027828 and 〇 00/49488 disclose an updated memory system for processing large erase blocks, including dividing logical sector addresses in units of regions. The logical address range of a small area is reserved for active system control data that is separate from another area for user data. In this way, system control data manipulation in its own area does not interact with user data associated with another area. The update belongs to the logical segment level and the writer indicator points to the corresponding physical segment in the block to be written. The mapping information is buffered in RAM and finally stored in the section configuration table of the main memory. The latest version of the logical section will eliminate all previous versions of the existing block: these blocks thus become partially eliminated. Execution of waste: Project collection can maintain a partially eliminated block as an acceptable quantity. ^Technical systems tend to distribute updated data across many blocks or update poor materials, which can partially eliminate many existing blocks. The result is usually a large collection of obsolete items needed for partially eliminated blocks. This is very inefficient and leads to premature aging of the memory. Also, there is a lack of a systematic and efficient way to handle sequential updates compared to non-sequential updates. Therefore, high capacity and high performance non-volatile memory are generally required. In particular: more f must have a non-volatile memory that can perform memory operations in large blocks without the above-mentioned problem. SUMMARY OF THE INVENTION A solid non-volatile memory system is organized according to the group 98680.doc -11 - 1272487. Each entity group (relay block) is an erasable unit and can be used to store data of a logical group. The memory management system allows updating a logical group of data by configuring a relay block dedicated to the update data of the logical group. The update relay block records the updated feed in the order received, and there is no limit to whether the record is in the correct logical order (sequential) or not (chaotic) of the original storage. Finally, the update relay block is closed for additional recording. A number of procedures will occur, but will eventually end up with a relay block that replaces the original relay block that is completely filled in the correct order. In the case of confusion, the catalogue data will be maintained in non-volatile memory in a way that facilitates frequent updates. The system supports multiple logical groups that are updated simultaneously. One feature of the present invention allows data to be updated in a logical group by group manner. Therefore, when updating the logical group, the distribution of the logical unit is limited to the extent of the update/hungry memory unit. This is especially true when the logical group is usually contained within a shell block. During the update of a logical group, one or two blocks that buffer the updated logical unit must typically be assigned. Therefore, it is only necessary to perform obsolete project collection on a relatively small number of blocks. The collection of obsolete items in a chaotic block can be performed by summarization or compression. Compared with the sequential block, the economic efficiency of the update process will become more and more obvious in the general processing of the update block, so there is no need to configure any ambiguous ghosts for the chaotic (non-sequential) update. All update blocks are configured as sequential update blocks, and any update block can be changed to a chaotic update block. More specifically, an update block can be arbitrarily changed from a sequential to a chaotic. 98680.doc -12- 1272487 Efficient use of the system (4) Allows simultaneous updating of multiple logical groups... Further increase efficiency and reduce over-consumption. Each memory scattered on multiple planes is aligned according to another ancient method of the present invention; ^ki JhK., for a tissue that is organized into a plurality of erasable blocks and by a memory plane a memory array that is configured (and thus can read a logical unit in parallel or program a plurality of logical units in parallel into the plurality of planes) to be updated in a second region of a particular memory When the original logical unit of the block is supplied, it is supplied with the required logical unit to remain in the same plane as the original. This can be done by recording the updated logical unit to the next available location of the second block that is still in the same plane. Preferably, the logic cells are stored in a plane in the same displacement position as the other versions, such that all versions of a given logic unit are served by the same set of sensing circuits. According to this preferred embodiment, any intermediate gap between the upper stylized memory unit and the next available planar aligned memory unit is filled with the current version of the logical unit. The current version of the logical units logically located after the last programmed logical unit and the current logical unit located in front of the logical units stored in the next available planar aligned memory unit The version is filled in the gap to complete the filling operation. In this way, all versions of the logical unit can be maintained in the same plane with the same displacement as the original, so that in the waste project collection operation, it is not necessary to extract the latest version of the logical unit from different planes to avoid performance degradation. In a preferred embodiment, the latest version can be used to update 98680.doc -13 - 1272487 or to fill each memory cell on the plane. Thus, the logical units can be read out in parallel from each plane, which will have a logical sequence without further rearrangement. ^ This scheme shortens the time of the total chaotic block by allowing the most = version ' of the logical unit of the logical group to be rearranged on the plane and without having to collect the latest version of the different memory planes. This is advantageous in that the host interface's validity b specification defines the maximum wait time for the memory system to complete the sector write operation. Staged Program Error Handling According to another aspect of the present invention, in a memory having a block management system, during a time-critical memory operation, a program failure in the block can be continued by interrupting the block (breakout) Stylized operations in Mock) to deal with. Later, in less urgent times, the data recorded in the failed block before the interruption can be transferred to other blocks that may also be interrupt blocks. The failed block can then be discarded. In this way, when a defective block is encountered, it cannot be processed because it must lose the data stored in the defective block immediately and exceed the specified time limit. This mishandling is especially important for discarding project collection operations, so it is not necessary to repeat the entire job for a new pay block during an emergency. Thereafter, at a suitable time, the data of the missing block can be saved by reconfiguring to other areas. Program failure handling is especially important during rollup operations. Normal summary operation: The current versions of all the logical units of the logical group resident in the original block and the update block are summarized into the summary block. During the total operation of the capsule, if a program failure occurs in the summary block, another block that is interrupted as 98680.doc -14 - 1272487 2 is provided, and the remaining logical units (4) are transferred. In this way, the ..., more than one person can still be specified in the normal summary operation right = within the exception processing. At the appropriate time, the logical units processed by the group are summarized into the total operation of the interrupt area. The appropriate time Chiang a / day, where the results of 1 and % will be in the face of some of the host write operations :: there is time to perform the period of the capsule total period. - One such suitable time; = another - a host write room with updated but unrelated summary operations. In essence, the summary of program failure handling can be considered to be implemented in multiple phases. In the first phase, after the program failure occurs, the logical unit 2 will be totaled in more than one block to avoid the summary of each logical unit more than once (four). The final stage will be completed, where the logical group (four) will be totaled. In the blocks, it is preferable to put all the material units into the interrupt summary block in a sequential order. $Non-sequential update block index According to another aspect of the present invention, in a non-volatile memory having a block management system supporting an update block having a non-sequential logic unit, the non-sequential 4-zone The index is buffered and stored in mm and periodically stored in non-volatile memory. In a specific embodiment, the index is stored in a block dedicated to storing the index. In another embodiment, the index is stored in the update block itself. In yet another embodiment, the index is stored in the header of each logical unit. On the other hand, the logical unit written after the previous (four) update but before the next (four) update stores its (four) t signal in the header of each logical unit. 98680.doc -15- 1272487 In this way, the power can be determined to be the most recent write: _ after 'do not have to perform scanning during initialization, the block is managed into a position of eight: 琏 early 70. In yet another aspect, the group. ^Order and part of the non-sequential means Hx on the logical sub-control data integrity and management according to the invention - if the data is maintained in "such as part or all of the control data in the ^ ^, control items, then guarantee an additional level Reliability. The execution method of the system is Λ ^, and the two-pass encoding process (two_pass) mb is used to stylize the same group with the success rate - remember the mercy; Multiple state benefits 任何 Any materialization errors in the weight process t are written in 1:1: The data created by the human maze process. The copy also helps the paste ''' 贞 (ie 'two copies have good ECC but data It is not possible to increase the amount of material available. (4) Techniques for data replication are considered. In a specific embodiment, after two programs of a given lean material are programmed in the early stylized coding process, The stylized encoding process can avoid stylizing the memory unit for storing at least one of the two copies. In this way, when the subsequent stylized encoding process terminates and destroys the data of the earlier encoding process before completion, At least one of the two copies is not Will be affected. In another embodiment, two copies of a given material are stored in two different blocks, and at most one of the two copies is a memory unit. Will be stylized in the following stylized encoding process. 98680.doc -16- 1272487 In another embodiment, after storing two copies of a given material in a stylized encoding process, it is no longer Any further stylization is performed on the set of memory cells used to store the two complexes. This can be achieved by stylizing the two replicas during the final stylized encoding of the memory monoblock. In yet another embodiment, the (four) copies of a given data can be stylized into a multi-state memory in a binary stylized mode so that the programmed ones are not The memory unit performs any further stylization. In another implementation, for the use of two encoding process programs: technology to continuously program multiple bits of the same group of memory cells of multi-state memory In the system, 'a fault-tolerant code is used to encode multiple memory states, so that the data created by the earlier stylized encoding process is not affected by errors in the subsequent stylized encoding process. According to another aspect of the present invention, In the non-volatile memory of the block management system, the "control waste collection" of the memory block can be implemented. ^Preemptive reconfiguration to avoid a large number of update blocks happening exactly = need to be reconfigured This can happen, for example, when updating the control data used to control the operation of the block manager. The level of the control data type can coexist with the number of different manufacturers of the update, resulting in the associated update block. Collection or reconfiguration of waste projects at different rates. In the case of more than one specific item that occurs when the waste project of the poor type is controlled to fall into the π team, the update block of all control data types is renewed. The configuration phase will be reorganized, and all update blocks will need to be reconfigured at the same time as 98680.doc 1272487. The features and advantages of the present invention will become apparent from the following description of the preferred embodiments of the invention. [Embodiment] Figure 1 shows in schematic view the main more components of a memory system suitable for implementing the present invention. 3 Responsive System 2 〇 usually operates from the host 1 through the host interface. The memory system is usually in the form of a memory card or an embedded memory system. The memory system 20 includes a memory 2 that is controlled by the controller 100 to operate. The memory 200 includes one or more arrays of non-volatile memory cells distributed over one or more integrated circuit wafers. The controller 1 includes: an interface 11〇, a processor 120, an optional sub-processor 121, an R〇M 122 (read-only memory), a RAM 130 (random access memory), and an optional programmable non-volatile Sex memory 124. The interface 110 has a component that connects the controller to the host and another component that is coupled to the memory 200. The firmware stored in the non-volatile R〇M 122 and/or the optional non-volatile memory 24 can provide the processor 1 code to implement the functions of the controller 100. The processor 12 or the optional sub-processor m can process the error correction code. In a specific embodiment of the invention, the controller 1 can be implemented by a state machine (not shown). In yet another specific embodiment, controller 100 can be implemented within a host. Logic 舆 physical block structure FIG. 2 is a memory according to a preferred embodiment of the present invention, which is woven into a plurality of physical segment groups (or relay blocks) and managed by the memory of the control device. To manage. The memory is organized into a number of "blocks" in which each of the relay blocks is a group of entities that can be erased together. 98680.doc -18 - 1272487 S〇, ..., Sn_io host 10 can be found in the file The memory 200 is accessed when the application is executed under the system or the operating system. Generally, the host will address the data 'where' in units of logical sectors, for example, each section may contain 512 bytes of data. The host usually reads or writes the memory system in units of logical clusters, and each logical cluster is composed of one or more logical segments. In some host systems, optional host-side memory management may exist. To perform lower-level memory management of the host. In most cases, during read or write, host 1 will essentially issue instructions to memory system 2 to read or write. a program segment containing a string of data sectors having consecutive addresses. A memory-side memory tube (4) is implemented in the old system 100 of the memory system 2 to manage the flash memory. In the plural " block of body 200 Storing and extracting data of a logical section of the host. In the preferred embodiment, the memory manager includes a plurality of software modules for erasing and reading the relay blocks. Jobs and write jobs. The female memory manager also maintains system control and directory data related to its operations in the flash memory and the controller RA; Fig. 3A(i)_3 A (iii) is a schematic diagram of a mapping between a logical group and a relay block according to the preferred embodiment of the present invention. The relay block of the physical memory has N physical segments. For storing N logical segment data of _ logical group: Figure 3A (1) is the data from the logical group g 'where the logical segments present a continuous logical sequence 卜, bu Ni. Figure 3A (9) (4) It is stored in the same logical order in the same data in the block 98680.doc -19- !272487. When stored in this way, the relay block will be chronologically "monthly" . In general, the relay block may have data stored in a different order, in which case the relay block is so-called "non-sequential" or "chaotic". There will be a shift between the lowest address of the logical group and the lowest address of the mapped relay block. At this point, the logical sector address will wrap around from the bottom of the logical group to the top in a meandering manner within the relay block. For example, in 囷3 A(iii), the relay block will be stored in its first position starting from the logical section & Upon reaching the last logical segment N-1, the relay block 曰"0 returns to sector 0, and finally stores the data associated with the logical segment in its last physical segment. In a preferred embodiment, page offsets are used to identify any displacements, identifying the starting logical sector address of the data stored in the first-physical section of the relay block. When two blocks differ by only one page private day, the two blocks are considered to store their logical segments in the same order. Figure 3B is a schematic illustration of the mapping between a plurality of logical groups and a plurality of relay blocks. Each logical group is mapped to a unique relay block except for a few logical groups in which the material is being updated. After a logical group is updated, it may be mapped to a different relay zone. The ghost can maintain the mapping ring in a logical pair of physical directories, as will be explained in detail later. f Consider the logical group-to-relay block mapping relationship of the gossip type. For example, the co-pending and co-owned US patent application filed by Alan Smclaim and the same day of the present invention, entitled "Adaptive Metablocks" 98680.doc -20- 1272487, discloses a relay of variable size. Block. This document incorporates in its entirety the entire disclosure of the co-pending claims. The characteristic of this syllabic is that the system and the system are operated by a single logical division, and the entire logical position of the ten-think system is handled in the same way in the logical segment group. . For example, a section containing system data and a section containing user data can be distributed anywhere in the logical address space. Unlike systems with the first w technology, there is no special segmentation or partitioning of system segments (ie, sections related to file configuration tables, directories, or subdirectories) to localize updates that may contain high and small sizes. In the logical address space section. Rather, the scheme for updating the logical group of segments is effectively handled as a typical access mode typical of the system segment and typical of the slot data. Figure 4 shows the alignment of the structure in the relay block and the physical memory. Flash memory contains blocks of memory cells that can be erased together as a single unit. The two erase blocks are the smallest erase unit of the flash memory or the smallest erasable unit (MEU) of the memory. The minimum erase unit is the hardware design parameter of the memory. However, in some memory systems that support multiple MEU erases, a "super MEU" containing more than one MEU can also be set. For flash EEPROM, a MEU can contain one segment, but preferably includes multiple segments. In the example shown, it has M segments. In a preferred embodiment, each segment may store 5 12-bit data and have a user data portion and a header portion for storing system or additional item data. If the relay block is composed of one MEU and each MEU contains one segment, each relay block will have N = Ρ * 区段 segments. At the system level, the relay block represents a group of memory locations, such as . 98680-doc -21 - 1272487 Sections that are erased together. The physical address space of the flash memory is processed, the group relay block, where the relay block is the smallest erase unit. In the manual, words such as “relay block” and “block” are synonymous, and use: Define the minimum erasing unit for media management at the system level, " mouth to remove the small position or MEU-word It is used to indicate the minimum erased two bits of the flash memory. To connect a few minimum erase units (MEUs) to form a relay block. In order to maximize the stylization speed and erase speed, parallel methods are used as much as possible by configuring multiple page information to be parallelized. (located in I MEU) ' and configure multiple meu to be erased in parallel. In flash memory, a page is a group of memory cells that can be combined together in a single operation. A page can contain one or more sections. Also, the memory array can be divided into more than one plane, wherein _ ^ mouth month b privately or erases " MEUs in * planes. Finally, the planes can be distributed in a plurality of § memory wafers. In flash memory, a MEU can contain one or more pages. Several MEUs within a flash memory wafer can be organized in a plane. Since one MEU of each plane can be programmed or erased at the same time, it is advantageous to select one MEU from each plane to form a plurality of MEU relay blocks (see Figure 5B below). Figure 5A shows a relay block formed by a minimum erasing unit that connects different planes. Each of the relay blocks (e.g., MBO, MB 1, ...) is constructed of a plurality of MEUs in different planes of the memory system, wherein different planes may be distributed in one or more of the wafers. The relay block link manager 170 shown in Fig. 2 can manage the link of the MEUs of the respective relay blocks. If one of the MEUs does not fail, set the ....7 retaining the composition of the coffee during the initial formatting process at the beginning of 98680.doc -22- 1272487. The "block" and throughout the system lifetime _ show a specific embodiment of selecting from the planes - the minimum erasing unit (meu) to join into the relay block. =: shows: select more than one from each plane _ In another embodiment, in the other embodiment, more than one MEU can be selected from the = face to form a _ super cle. For example, the example ~ brother ' - super MEU may be It consists of two coffee machines. At this time, more than one coding process is taken to perform reading or writing operation. The day is raised and co-owned by Cados Gonzales et al. on the same day as the present invention. US patent application titled "Field - Determine Grouping 〇f Heart Coffee _ Curry (10)

Structures also reveals that a plurality of meu are linked and rejoined into a relay block. The entire disclosure of this co-pending application is incorporated herein by reference. Relay Block Management Figure 6 is a schematic block diagram of a relay block management system implemented in controllers and flash memory. The relay block management system includes various functional modules implemented in the controller, and maintains various control data (including catalog materials) in the form and list distributed hierarchically in the flash memory and the control RAM 130. The function modules implemented in the controller 100 include: an interface module 11〇, a logical pair entity address translation module 140, an update block manager module 150, an erase block manager module 16〇, and a relay. Block Link Manager 170 〇98680. Doc -23- 1272487 〇 4 4 relay block management system interface host system. The logical-to-real address translation module 140 maps the logical address of the host to the physical memory location. The update block manager module 15G manages the #material update operation of a given data logical group in the memory. The block manager 16G has been erased to manage the relay area. The ghost erased and its configuration for storing new information. Relay Block Link Management f 170 manages the links of the sub-groups of the smallest erasable block to form a given relay block. These modules will be detailed in their individual sections. During the operation, the relay block system will generate and cooperate with the control data (such as bit stop, control and status information) to operate. Since many control data tend to be small data that is frequently changed, it cannot be efficiently stored and maintained at any time in a flash memory having a large block structure. In order to store relatively static control data in non-volatile flash memory, and to find a small number of relatively variable control data in the controller RAM for more efficient update and access, hierarchical and Decentralized solution. In the event of a power outage or failure, 'this scheme allows scanning of non-volatile ticks in the group's control data to quickly build control data in the volatile controller. This is possible because the invention can be limited The number of blocks associated with the possible activity of the data for a given logical group. In this way, the scan can be restricted. In addition, some of the control data that requires persistence is stored in the non-volatile relay area updated by the segment. In the block, each update will record a new segment that replaces the previous segment. The control data will use the segment index II case to record the update by segment in the relay block. μ Non-volatile flash memory 2〇 _ A large amount of relatively static control data is stored. This includes · · Group Address Table (GAT) 210, mixed block block prime 98860. Doc -24- 1272487 (CBI) 220, erased block list (EBL) 23〇 and MAP 240. GAT 21 〇 can record the mapping between logical groups of segments and their corresponding relay blocks. These mappings will not change unless updated. The CBI 220 can record the mapping of logically non-sequential segments during the update. EBL 23 0 records the pool of relay blocks that have been erased. The MAP 240 is a bit map that displays the erased state of all of the relay blocks in the flash memory. The volatile controller RAM 130 stores a small portion of the control data that is frequently changed and accessed. This includes a configuration block list (ABL) 134 and a clear block list (CBL) 136. The ABL 134 records the configuration of the relay block for recording updated data, while the CBL 136 records the deconfigured and erased relay blocks. In the preferred embodiment, the RAM 13 can be used as a cache memory for the control data stored in the flash memory 200. The update block manager update block manager 15 (shown in FIG. 2) processes the update of the logical group c. According to the aspect of the present invention, each logical group of the updated section is configured to record updates. Dedicated update relay block for data. In a preferred embodiment, any block of the logical group - or multiple segments - will be recorded in the update block. The update block can be managed to receive updated data in sequential order or in sequential (also known as "chaotic") order. Chaotic update block allows the section data to be updated in any order within the logical group, and individual sections can be arbitrarily repeated. In particular, it is not necessary to reconfigure any of the data sections, and the sequential update block can become a listening update block. Chaotic data updates do not require any (four) fixed block configuration'. Any non-sequential write of logical addresses can be automatically incorporated. Therefore, unlike the systems of the prior art, which are different from the prior art systems, 98680 is not necessary. Doc -25- 1272487 Specially handles whether each update block of this logical group is logically sequential or non-sequential. The general update block is only used to record various blocks in the order requested by the host. For example, even if the host system data or system control data tends to be updated in a chaotic manner, it is not necessary to process the logical address space corresponding to the host system data in a different manner than the host user data. In contrast, the data of the complete logical group of the segment is stored in a logically sequential order = early-relay block. In this way, the index of the stored logical section can be predefined. When a relay block stores all segments of a given logical group in a predetermined order, it can be said to be "complete." As for the update block, when the most f is filled in the logically sequential order, the new block will become the updated full relay block that can replace the original relay block at any time. On the other hand, if the update block fills up the j new data in the different order of the logical and complete blocks, the update block is a non-sequential or chaotic update block, then the sequence-only block must be further processed so that the final block can be pressed. Same as the full block: the order to store the updated data of the logical group. In the preferred embodiment, it is in a logically sequential order in a single relay block. Further processing involves summarizing the updated segments in the update block and the unchanged regions in the original block to yet another update relay block. The summarized update area 2 is then in a logically sequential order and can be used to replace the original block. Under the = predetermined condition, there will be - or multiple collapse procedures before the summary program. f #序/, is to re-record the segment of this chaotic update block into a superimposed mix: 4 block same day guard removes any duplicate logical segments that have been eliminated by subsequent updates of the same logical segment. The update scheme allows multiple executions of up to a predetermined maximum value to be performed simultaneously 98680. Doc -26- 1272487, each thread is a logical group that is updated with its dedicated update relay block. Sequential Data Update When you update data belonging to a logical group first, the relay block and the update block that is dedicated to the update data of the logical group are configured. When an instruction to write a block of one or more segments of a logical group is received from the host (the existing medium, the block has stored all the complete segments), the update block is configured. For the fs machine; the write operation will record the data of the first block on the update area. Since each host writes one of the consecutive logical addresses or multiple blocks, it will follow the first An update is always on the feature. In subsequent host writes, the update blocks in the same logical group are recorded in the update block in the order received from the host. One block is accepted as a sequential update block, and the segments updated by the host in the associated logical group are logically sequential. All segments updated in this logical group are written to this sequential update block until the block is closed or converted to a fuzzy update block. Figure 7A shows an example of writing a segment in a logical group of sequential update blocks in sequential order due to two separate host write operations, while the corresponding segment in the original block of the logical group becomes obsolete. In the main pseudo-intrusion operation #1, the data of the logical segment LS5-LS8 is updated. The data updated to LS5, -LS8' will be recorded in the newly configured dedicated update block. For convenience, the first product # § to be updated in the logical group will be recorded in the dedicated update block starting from the location of the first physical segment. —^ 敎 In terms of the first logical segment to be updated, it is not necessarily a logical segment of the group, so, 98680. Doc -27- 1272487 There will be a displacement between the start of the logical group and the start of the update block. This bit shift is referred to as a "page mark" as previously described in connection with Figure 3A. Subsequent segments will be updated in a logically sequential order. In the last zone of the write logical group, the group address will wrap around and the write sequence will continue from the first segment of the group. In master write operation #2, the section of the data in logical section LS9-LS12 is updated. The data updated to become LS9'-LS12 will be recorded in the dedicated update block directly in the position after the end of the last write. The figure shows that two hosts are written as follows: The updated material in the update block, ie LS5’-LS 12, is recorded in a logically sequential order. The update block can be thought of as a sequential update block because it has been filled in a logically sequential order. The updated data recorded in the update block can be used to eliminate the corresponding data in the original block. Chaotic data update When any segment updated by the host in the associated logical group is logically non-sequential, the chaotic update block can be started for the existing sequential update block/the heart update block is the data update area. The form of the block in which the associated logical group, and the logical segments within can be updated in any order and can be repeated arbitrarily. It can be established by converting the sector written in the host to a logically non-sequential %, from a sequential update block to a region & phantom write within the updated logical group. All subsequent segments updated in this logical group are written to the next available segment location in this random update block, regardless of its logical segment address within the cluster. Figure 7B shows the vane column of the logical group of the chaotic update block written in chaotic order due to five separate host write operations, while the logical group 98680. Doc -28- 1272487 The replaced segment in the original block and the copied segment in the chaotic update block become obsolete. In host write operation #1, the logical segments LS 1 O-LS 11 of a given logical group stored in the original relay block are updated. The updated logical section LSlO'-LSll' will be stored in the newly configured update block. At this point, the update block is a sequential update block. In the host write operation #2, the logical extents LS5-LS6 are updated to LS5'-LS6' and recorded in the update block immediately after the last write. This converts sequential update blocks into confusing update blocks. At the host write operation #3, the logic segment LS10 is updated again and the next position where it has been recorded in the update block becomes LS10". At this time, the LS10" in the update block can replace the LSI in the previous record ( V, and LSI0' can replace LS10 in the original block. In host write operation #4, the data of logical sector LSI 0 is updated again and recorded in the next position of the update block to become LSI0'&quot Therefore, LSI0,, is now the last and only valid poor material of logical segment LS10. In host write operation #5, the data of logical segment LS30 is updated and recorded in the update block. It becomes LS3CT. Therefore, this example shows that multiple logical segments within a logical group can be written into a chaotic update block in any order and any repetition. Forced sequential update Figure 8 shows due to two logical bits An example of a segment of a sequential update block written sequentially in a logical group with interrupted host write operations. In the host write #1, the updated data record of the logical segment LS5-LS8 is recorded. In the dedicated update block It is LS5'-LS8'. In the host write #2, the update data of the logical sector LSI4-LS 16 is recorded after the last write 98680. In the update block of doc -29- 1272487, it becomes 1^14, -1^16'. However, there is an address jump between 1^8 and 1^14, and a host write of #2 usually makes the update block non-sequential. Since there are not many address jumps, one option is to copy the data of the middle section of the original block to the update block before performing the host write to perform the padding operation (#2Α). In this way, it can be saved. Update the sequential nature of the block.Figure 9 shows a flow diagram of a program for updating the information of a logical group by the update block manager in accordance with a general embodiment of the present invention. The update process comprises the following steps: Step 260: The memory is organized Each of the blocks is divided into a plurality of memory cells that can be erased together, and each of the memory cells is used to store data of a logical unit. ν 262 · 4 data is organized into plural Logical group, each logical group is divided into a plurality of logical units. Step 2 6 4: In the standard example, according to the first specified order, preferably logically sequential (four) order, the logical group (four) (4) The material element is stored in the memory unit of the original block. In this way, the index of the individual logical unit in the access block can be known. Step 270: For a given logical group (eg, LGx) It is requested to update the logical unit within the LGX. (The logical unit update is an example. Generally, the update will be a block consisting of one or more consecutive logical units.) Step 272: Update logic of the request The unit will be stored in the second block dedicated to recording the update of the LGX. The order of recording is based on the second order, usually 98680. Doc -30- 1272487 = Update the order of the requests. A feature of the present invention allows for the initial updating of blocks of data recorded in a logically sequential or chaotic order. Therefore, the block is updated according to the second order. The first block may be a sequential update block or a chaotic process. When the program loop returns to step 270, the second block continues to record the logical unit of U. The first block will be closed when the closed predetermined condition is formed to receive further updates. At this point, the process proceeds to step 276. Step 276: Determine whether the closed second block records its update logical unit in the same order as the original block. When the two block record logical units differ only by the stomach surface mark, the two blocks are considered to have the same order' as described in connection with Figure 3 。. If the two blocks have the same order, the private sequence is continued to step 28, otherwise, it must be in step Μ. Perform abandoned project collection. Step 280 - Since the second block has the same order as the first block, it can be used to replace the original first block. The update process then ends at step 299. Step 290: Collect the latest version of each logical unit of a given logical group from the second block (update block) and the first block (original block). The summarized logical units of a given logical group are then written to the third block in the same order as the first block. Step 292: Since the third block (summary block) has the same order as the first block, it can be used to replace the original first block. The update process then ends at step 299. 98680. Doc -31· !272487 Step 299: When the end program completes the update block, it will become the new standard block for the given logical group. The update thread for this logical group will be terminated. - Figure 10 shows a flow diagram of a program for updating a block manager to update data for a logical group in accordance with a preferred embodiment of the present invention. The update procedure includes the following steps: Step 310: For a given logical group (eg, LGJ data, it will request ^ logical section within the new LGX. (The section update is an example. - General Lu' update will be A segment consisting of LG"- or multiple consecutive logical segments.) Step 3U: If the LGx-specific update block does not yet exist, proceed to step 10 to step 4H) to initiate a new update thread for the logical group. . This can be done by means of c: configuring a more complex block dedicated to updating the data of the logical group. If there is already an updated update area, proceed to step 314 and begin recording the update section to the update block. Step 314: If the current update block has been confusing (i.e., non-sequential), then proceed directly to step 51G to record the requested update segment to the mixed temple update block. If the current update block is sequential, proceed to step 3 16 to process the sequential update block. Step 316: The feature of the present invention allows an update block to be initially set for use in a logically sequential or chaotic order. However, because the group will eventually store its data in the relay block in the logical sequence (4), it is therefore desirable to keep the updated block (4) as much as possible. Next, when _-updates the block to proceed to 98680. Doc -32- 1272487 When you update, you will need less processing because you do not need to collect waste items. Therefore, it is judged whether the requested update follows the current sequential order of the update block. If the update is followed sequentially, proceed to step 5g to perform the sequential update, and the update block will remain sequential. On the other hand, if the update is not followed (chaotic update), it will convert the sequential update block into a chaotic update block when no action is taken. In the specific embodiment, no action is taken to save the situation, and then the program proceeds directly to step (4) G, which allows the update to turn the update block into a chaotic update block. °° Optional Forced Sequencing Procedure 隹 Another (4)^ example of the implementation of the mandatory sequencer step 320' to save the sequential update area ^ as much as possible due to the chaotic update of the suspension. There are two cases, both of which require copying the original block's fallback to maintain the sequential order of the logical segments recorded on the updated block. The first case is where the update can establish a short address jump. The first case is to end the update block early to keep it in order. The forced sequencer step 320 includes the following sub-steps: Step 330. If the logical address jump of the update establishment is not greater than the predetermined number, the program proceeds to the forced sequence update procedure of step (10), and the sequence ends. The step state, in order to consider whether it is suitable to force the execution of the predetermined design parameters, then update the block to phase. Step 340. If the number of unfilled physical segments is Cc (the representative value is half of the updated block size) 98680. Doc -33- 1272487 The pair is not used, so it will not be closed early. The process proceeds to step 370, and updating the block can become confusing. On the other hand, if the update block is substantially filled, then it is considered to have been fully utilized, so proceed to step 3 to force the sequence to end. Step 3 5 0 • Forced sequential update allows the current sequential update block to remain sequential as long as the address jump does not exceed the predetermined number cb. Essentially, the section of the associated original block of the update block is copied to fill the gap spanned by the address jump. Therefore, before proceeding to step 5, the block is updated sequentially with the information of the intermediate address to record the current update sequentially. Step 360: If the current sequential update block has been substantially filled, rather than being converted to a chaotic update block by the suspended mess update, then the forced sequence end allows the current sequential update block to be closed. A chaotic or non-sequential update definition is an update with the following items: no forward address transitions, reverse address transitions, or address repetitions covered by the above address hop exceptions. In order to prevent the sequential update block from being converted for a chaotic update, the unwritten segment position of the update block is filled by copying the sector of the original partial demise block of the associated block. Then completely eliminate and erase the original block. Now, the update block of the destination has a complete set of logical segments and then ends up as a complete relay block that replaces the original relay block. The program then proceeds to step 430 to configure the update block at its location to accept the record of the pending segment update requested in step 31. Convert to chaotic update block Step 370: When the suspended update is not in sequential order and may or may not be available, if the forced sequence condition cannot be met, the program proceeds to step 5ι 98684. Doc -34 - 1272487 allows the sequential update block to be converted to a chaotic update block by allowing a suspension update segment with a non-sequential address to be recorded on the update block. If the maximum number of chaotic update blocks are present, the chaotic update block that has not been accessed for the longest time must be closed before allowing the conversion to proceed; thus, the maximum number of chaotic blocks will not be exceeded. The identification of the oldest unaccessed chaotic update block is the same as the general example described in step 420, but is limited to the chaotic update block. At this point, closing the chaotic update block can be accomplished by a summary as described in step 55. Configuring a New Update Block Restricted by the System Step 410: The procedure for configuring the erase relay block to update the block begins with determining whether the predetermined system limit is exceeded. Due to limited resources, the memory management system typically allows a predetermined maximum number of Cas of update blocks that can exist simultaneously. This limit is the total number of sequential update blocks and chaotic update blocks, and is also a design parameter. In a preferred embodiment, this limit is, for example, a maximum of 8 update blocks. Also, due to the high demand for system resources, there is a corresponding predetermined limit on the maximum number of chaotic update blocks that can be simultaneously opened (eg, sentences. Therefore, when CA update blocks have been configured, only The next configuration request can be satisfied after the existing configuration request is closed. The program proceeds to step 420. When the number of open update blocks is less than cA, the program proceeds directly to step 430. Step 420: Exceed the update block When the maximum number of Ca is exceeded, the oldest unaccessed update block is closed and the discarded item collection is performed. The oldest unaccessed update block is identified as the update block associated with the longest unaccessed logical block. The block that has not been accessed for the longest time, the access includes the writing and the selective reading of the logical segment. The 98680 of the update block is maintained in the order of access. Doc -35- 1272487 / month early; when initializing, no access order is assumed. When the update block is in the order of the update block, the same procedure as described in the combination of step 36 and the step will be followed. When the update block is confusing, the same % order of the combination step will be followed. The close space can be moved to configure a new update block in step 43. V Step 43 0 • Configuring a new relay block as the update block specific to the given logical group LGx can satisfy the configuration requirement. Next, the program proceeds to step 5 1 0. Recording the update data on the update block Step 5 1 0 • Record the requested update section on the next available shell position of the update block. Then, the program proceeds to Step 52: Determine whether the update block is ready to end. The update block ends step 520: if the update block still has space to accept the additional update, proceed to step 522. Otherwise, proceed to step 57 to end the update area. The ghost writes in the uranium pleading attempt to write more than the logical area I of all the spaces of the block, and there are two possible embodiments for filling up the updated block. In the first embodiment, the write will be written. Request score In two parts, where the first part can be written up to the last physical section of the block. The block is then closed and the second part of the write is processed as the next requested write. In another embodiment, The block retains the write of the request when it fills the remaining segments, and then closes it. The write for the δ month is processed as the write for the next request. Step 522: If the update block is sequential, proceed to Step 53: to perform a sequential shutdown. If the update block is confusing, proceed to step 98680. Doc • 36- 1272487 Step 540 to close the mess. Step by Step Update Block Step 530: Since the update block is sequential and fully populated, the logical group stored therein is complete. The relay block is complete and can replace the original relay block. At this point, the original block will be completely eliminated and erased. The program then proceeds to step 570 where the update of the given logical group is terminated.仃,, chaotic update block end Step 540: Since the update block is non-sequentially populated, it may contain multiple updates of some logical segments, so the waste project collection is performed to save the effective poor material. The chaotic update block can be compressed or summarized. At step 542, the program to be executed will be determined. ° Step 542: The compression or summary to be performed will depend on the degradation of the update block. If a logical segment has been updated multiple times, its logical address will be highly degraded. Multiple versions of the same logical section will be recorded on the update block, and only the last recorded version is a valid version of the logical section. In an update block with multiple versions of logical segments, the number of distinct logical segments will be much less than for logical groups. In the preferred embodiment, when the number of logical segments in the ft new area has more than a predetermined design parameter Cd (the representative value is half of the logical group size), the ending procedure is at step 55. 〇 Execution summary, otherwise the program will proceed to the compression of step 560. Step 550 · If the chaotic update block is to be summarized, the original block and the updated block will be replaced by the new private quasi-relay block containing the summary information. Summary 98680. After doc -37- 1272487, the update thread will end in step 57. ~vStep 560 • If you want to compress the chaotic update block, it will be replaced with a new update block containing the compressed data. After compression, the processing of the compressed update block will be , , , . The bundle is in step 57G. Alternatively, I can be delayed until the update block is written again, so the exclusion is followed by a possible I4 without a summary of the intermediate updates. Then, when the next request in step 5〇2 is required to be updated in LGx, the new update block is used in the incoming step update of the given logical block. When v completes the program to create a complete update block, the block becomes a new standard block for a given logical group. The update thread for this logical group will be terminated. When the end of the program builds a new update block that replaces the existing update block, the new update block is used to record the next update requested for the given logical group. When the update block has not ended, processing will continue when the next request in the LGX is updated in step 3 j 。. As can be seen from the above procedure, when the chaotic update block is closed, the updated data recorded thereon is further processed. In particular, the collection of obsolete items of valid data is performed by the following procedure: a program compressed to another chaotic block, or a summary of the original blocks associated with it to form a new standard sequential block. Fig. 11A is a flow chart showing in detail a summary procedure for closing the chaotic update block shown in Fig. 10. The chaotic update block summary is one of two possible programs that are executed when the update block is finished, such as when the update block has filled the last physical segment location it was written to. The summary is selected when the number of logical segments that are written in the block exceeds the predetermined design parameter CD. The summary procedure shown in Figure 5 5 5 0 contains the following sub-steps: Step 5 5 1 · When the mixed IL update block is closed, it will be configured to replace it. 98680. New trunk block for doc -38- 1272487. Step 552: Collect the latest version of each logical segment and ignore all the eliminated segments in the chaotic update block and the associated original block. Step 554: Record the collected valid segments in a logical sequential order on the new relay block to form a complete block, that is, a block of all logical segments of the logical group recorded in sequential order. Step 5 5 6 · Replace the original block with a new complete block. Step 558: Erasing the updated block and the original block. Fig. 11B is a flow chart showing the compression procedure for closing the chaotic update block shown in Fig. 1 for the fine display. Compression is selected when the number of logical segments that are written in the block is lower than the predetermined design parameter CD. The compression procedure step 560 shown in Figure 1A includes the following sub-steps: Step 5 61: When the chaotic update block is compressed, a new relay block is replaced. Step 562: Collect the latest version of each logical segment in the existing chaotic update block to be compressed. Step 564: Record the collected segments on the new update block to form a new update block with the compressed segments. Step 5 6 6: Replace the existing update block with a new update block with a compressed section. Step 568: Erasing the updated block that has ended. Logic and Relay Block Status Figure 12A shows all possible states of a logical group, and the possible transitions between them under various operations. 98680. Doc -39- I272487 Figure 12B is a table listing the possible states of a logical group. The logical group status is defined as follows: 1 • All logical segments in the 奎·· logical group have been written into a single relay block in a logical sequential order, which may utilize page mark winding. 2. No, wear eight: no logical segments have been written in the logical group. The logical group will be marked as a medium I block that is not written and has no configuration in the group address table. Returns a predetermined data pattern in response to a host read for each segment in this group. 3. Sequence hot dance: Some sections in the logical group have been written into the relay block in a logical sequential order, possibly using page markers, so it can replace the corresponding logic of any previous complete state in the group. Section. 4 · Bunun Dance: Some sections within a logical group have been written into the relay block in a logically non-sequential order, possibly using page markers, so they can replace the corresponding ones of any previous complete states in the group. Logical section. Sections within a group can be written to - the latest version of the above will replace all previous versions. Figure 13A shows all possible states of a relay block, and possible transitions among various operations. Figure 13B shows all possible states of the relay block, and the possible transitions between them in various operations: ', 1 · · #馀: All sectors in the relay block have been erased. . The order is odd: the relay block has been partially written, and its sections are in sequential order, possibly using page markers. All sections belong to the same 98680. Doc -40- 1272487 Logical group. 3 _This: The relay block has been partially or completely written, and its segment is logically out of order. Any zone can be written more than once. All zones belong to the same logical group. 4. End #: The relay block has been completely written in the logical sequential order, possibly using page markup. The section has been phased out due to hosting costs. The relay block was previously obsolete for complete but at least one update. 14(A)-14(J) are state diagrams showing various operational effects on the logical group state and on the physical relay block. Fig. 14(4) shows a state diagram corresponding to the logical group of the first-writer operation and the transition of the relay block. The host writes __ or multiple segments of a previously unwritten logical group to the newly configured erased (four) block in a logically sequential order. The logical group and the relay block enter the sequential update state. Figure 1 shows a state diagram corresponding to the logical grouping of the first complete operation and the transition of the relay block. The sequential update logical group of the previously unwritten person becomes complete because the host sequentially writes all the sections of the person. If the memory cuts the predetermined data and fills the remaining unwritten segments to fill the group, it will also change. The relay block becomes complete. Fig. 14(C) shows a state diagram of the logical group and the relay block transition of the first mess operation. The sequential update logical group of the previously unwritten person becomes confusing when the host writes at least one segment out of order. Fig. 14(D) shows a state diagram of the logical group of the first compression operation and the transition of the relay block. From the old block, the previously unwritten chaotic update logic 98680. Doc -41 - 1272487 All valid sections in the group are copied to the new chaotic relay block and then erased. Fig. 14(E) shows a state diagram of the logical group and relay block transition corresponding to the first summary operation. Move previously unwritten chaos from the old chaotic block Update all valid segments within the logical group to fill the newly configured erased blocks in a logically sequential order. Zones that are not written by the host are populated in a predetermined data mode. Then erase the old chaotic block. Fig. 14(F) shows a state diagram corresponding to the logical group of the sequential write operation and the transition of the relay block. The host writes one or more segments of the complete logical group to the newly configured erased relay block in a logically sequential order. The logical group and the relay block become in a sequential update state. The previously complete relay block becomes the original relay block. Fig. 14(G) shows a state diagram corresponding to the logical group of the sequential padding operation and the transition of the relay block. The sequential update logical group becomes complete when the host sequentially writes all its segments. This can also occur when the sequential update logical group is populated with the valid section of the original block to complete its collection of obsolete items, after which the original block is erased. Figure 14 (H) shows a state diagram corresponding to the logical group and relay block transitions of the non-sequential write operation. The sequential update logical group becomes confusing when the host writes at least one segment non-sequentially. Non-sequential segment writes can cause the updated block or the valid segment in the corresponding original block to become obsolete. Fig. 14 (1) shows a state diagram corresponding to the logical group of the compression operation and the transition of the relay block. All active segments in the chaotic update logical group are copied from the old block to the new chaotic relay block' and then erased. Original block 98680. Doc -42- 1272487 will not be affected. Fig. 14(J) shows a state diagram corresponding to the logical grouping of the summary operation and the transition of the relay block. All active segments within the chaotic update logical group are copied from the old chaotic block to populate the newly configured erased blocks in a logically sequential order. Then erase the old chaotic block and the original block. Update Block Tracking and Management Figure 15 shows a preferred embodiment of the structure of an Configuration Block List (ABL) for tracking open and closed update blocks and erased blocks for configuration. The configuration block list (ABL) 61 0 will be stored in the controller RAM -130 to allow management of the erased block configuration, configured update blocks, associated blocks and control structures to enable correct The logic translates to the physical address. In a preferred embodiment, the ABL includes: a list of erased blocks, an open update block list 614, and a closed update block list 616. The opened update block list 614 is an open update area in the ABL. The block project group of the attributes of the block. The list of updated update blocks has one item of each data update block currently open. Each item retains the following information. LG is the logical group address dedicated to updating the relay block. Sequential/chaotic is the state in which the update block is populated with sequential or confusing update data. MB is the relay block address of the update block. The page mark is the starting logical section of the record at the first physical location of the update block. The segment number written represents the segment number currently written on the update block. MB◦ is the relay block address of the associated original block. Page Tag is the page mark of the original block associated with it. The closed update block list 616 is a subset of the configuration block list (ABL). 98680. Doc • Block project team for 43- 1272487. shut down

The starting logical section of an entity location record. The list of update blocks in the ABL with the attributes of the closed update block has a closed logical group address dedicated to the ghost. The MB page mark is the original block of the associated block in the update block, but its item has the following information in the logical vs. main entity directory. LG is the relay block address of the current secret animal. Chaotic Block Index The Sequential Update Block has data stored in a logically sequential order, so it is easy to find any logical section in the block. The hash update block has logical segments that are not stored in order and can store multiple update generations of one logical segment. Additional information must be maintained to record where each valid logical segment is placed in the chaotic update block. In a preferred embodiment, the chaotic block index data structure allows for tracking and fast access to all active segments in the chaotic block. The chaotic block index is independent of the logical address space of the small area and can effectively handle the hotspots of system data and user data. The index data structure essentially allows index information with infrequent update requirements to be maintained in the flash body to avoid significant impact on performance. On the other hand, the list of recently written segments in the chaotic block is retained in the chaotic section list of the controller RAM. Also, the cache memory of the index information of the flash memory is retained in the controller RAM to reduce the number of flash sector accesses for address translation. The index of each chaotic block is stored in the chaotic block index (CBI) section of the flash memory. Figure 16A shows the data field of the Chaotic Block Index (CBI) section. Chaotic area 98680.doc -44 - 1272487 The block index section (CBI section) contains an index of each section of the logical group mapped to the chaotic update block, which can define the logical group segments in the chaotic update block or The location within the original block associated with it. The CBI section includes: a chaotic block index field for recording the valid section in the chaotic block, a chaotic block information field for recording the chaotic block address parameter, and a relay block for recording the CBI section (CBI area) The section index field of the valid CBI section within the block). Figure 16B shows an example of a chaotic block index (cbi) section recorded in a dedicated relay block. A dedicated relay block may be referred to as a CBI block 620. When the CBI section is updated, it is written to the next available physical sector location in CBI block 620. Thus, multiple copies of the CBI section can exist in the CBI block, with only the last written copy being valid. For example, the CBI section of logical group LG1 has been updated three times with the latest version of the active version. A set of indices of the last written CBI section in the block identifies the location of each valid section in the CBI block. In this example, the last written CBI section in the block is the CBI section of LG^6, and its index set is a valid index set that replaces all previous index sets. When the CBI block finally becomes fully populated with the CBI section, then all valid sections are rewritten to the new block location to compress the block during the control write operation. Then erase the entire block. The chaotic block index field within the CBI section contains an index entry for each logical segment within the logical group or a subgroup that maps to the chaotic update block. Each index item represents the displacement within the chaotic update block where the valid data for the corresponding logical segment is located. The reserved index value represents valid data for no logical segments in the chaotic update block, and the corresponding segment in the original block representing the association is valid. The cache memory of some chaotic block index field items will be retained in the 98680.doc -45 - 1272487 controller RAM. The chaotic block information block in the CBI section contains an item about each chaotic update block in the system to record the address parameter information of the block. The information in this block is only valid in the last written section of the CBI block. This information will also appear in the data structure of the RAM. The items of each chaotic update block include three address parameters. The first number is the logical address of the logical group (or logical group number) associated with the chaotic update block. The second parameter is the relay block address of the chaotic update block. The second parameter is the physical address offset of the last segment written into the chaotic update block. The displacement information sets the scan start point of the chaotic update block during initialization to reconstruct the data structure in the RAM. The section index field contains entries for each valid CBI section in the CBI block. It defines the displacement of the most recently written CBI section within the CBI block for each of the licensed chaotic update blocks. The reserved value of the displacement in the index represents that the licensed chaotic update block does not exist. Figure 16C is a flow diagram showing the access to data for a logical segment of a given logical group that is undergoing a chaotic update. During the update process, the update data is recorded in the chaotic update block, while the unaltered data is left in the original relay block associated with the logical group. The procedure for accessing the logical section of a logical group under a chaotic update is as follows: Step 650: Start looking for a given logical section of a given logical group. Step 652: Find the last written CBI section in the CBI block. Step 654: Find the chaotic update block or the original area 98680.doc -46- 1272487 block associated with the given logical group by querying the chaotic block information field of the last written cm segment. This step can be performed any time before step 662. Gaming 658 - If the last written CBI segment points to a given logical group, then the CBI segment can be found. Proceed to step 662. Otherwise, proceed to step 660. Step 660: Find the CBI section of the given logical group by querying the section index field of the last written CBI section. Step 662: Find a chaotic block or a given logical segment in the original block by querying the chaotic block index field of the CBI section found. Figure 16D shows a flow diagram of accessing data for a logical segment of a given logical group that is undergoing a chaotic update, in accordance with an alternative embodiment in which a logical group has been partitioned into sub-groups. The limited capacity of the CBI segment can only record a predetermined maximum number of logical segments. When a logical group has more logical segments than a single CBI segment can handle, the logical group is split into a plurality of subgroups having CBI segments assigned to each subgroup. In one example, each of the packets has a capacity sufficient to track the logical group consisting of 256 segments and up to eight chaotic update blocks. If the logical group has a size greater than 256 segments, there are separate cm segments for each 256 segment subgroup within the logical group. The CBI section can exist for up to 8 subgroups within a logical group to support logical groups up to 2048 segments. In a preferred embodiment, an indirect indexing scheme is employed to facilitate index management. Each item of the section index has direct and indirect blocking. The direct segment index defines the displacement within the CBI block for all possible CBI segments of a particular chaotic update block. The information in this block is only valid in the C BI section written at the end of the 5H specific chaotic update block. The value of the displacement of the 98686.doc -47- 1272487 displacement means that the CBI section does not exist because the corresponding logical subgroup of the chaotic update block either does not exist or because the updated block is configured. not up-to-date. The indirect section index may define the displacement within the CBI block in which the most recently written CBI section of each chaotic update block of the license is located. The reserved value of the displacement in the index represents that the licensed chaotic update block does not exist. Figure 1 6D shows a procedure for accessing a logical section of a logical group under a chaotic update, the steps of which are as follows: Step 670: Split each logical group into a plurality of subgroups and assign a cbi area to a subgroup. Step 680: Start looking for a given logical segment of a given subgroup of a given logical group. Step 682: Find the last written CBI section in the CBI block. Step 684: Find the chaotic update block or the original block associated with the given sub-group by querying the chaotic block information field of the last written CBI section. This step can be performed any time before step 696. Step 686: If the last written cbi segment is directed to a given logical group, then the process proceeds to step 69 1 . Otherwise, proceed to step 690. Step 690: Indirect segment indexing by querying the last written CBI segment

Blocker' finds the last written CBI section in multiple CBI sections of a given logical group. Step 691: At least one CBI section associated with one of the subgroups of the given logical group has been found. carry on. Step 692: If the found CBI section points to a given subgroup, then 98680.doc -48 - 1272487 may look for a CBI section of the given subgroup. Proceed to step 696. Otherwise, proceed to step 694. Step 694: Find the CBI section of the given subgroup by querying the direct section index field of the CBI section currently being sought. Step 696: Find a chaotic block or a given logical segment in the original block by querying the chaotic block index field of the CBI section of the given subgroup. Figure 16E shows an example of a Chaotic Block Index (CBI) section and its functions in a specific embodiment in which each logical group is partitioned into a plurality of subgroups. The logical group 700 originally stores its complete data in the original relay block 702. The logical group is then updated with the configuration-specific chaotic update block 704. In this example, logical grouping 700 is partitioned into subgroups, each of which has 256 segments. In order to find the i-th segment in subgroup B, the last written CBI segment in CBI block 620 is first looked for. The chaotic block information field of the last written CBI section can provide the address of the chaotic update block 704 looking for a given logical group. At the same time, it can also provide the location of the last segment written in the chaotic block. This information is useful when scanning and rebuilding indexes. If the last written CBI section result is one of the four CBI sections of a given logical group, it is further determined whether it is the CBI section of the given subgroup B containing the i-th logical section. If so, the chaotic block index of the CBI section will point to the location of the relay block where the data of the i th logical section is stored. The segment location will be in the chaotic update block 704 or in the original block 702. If the last written CBI segment result is one of the four 98680.doc -49 - 1272487 CBI segments of the given logical group but However, if it does not belong to subgroup b, it will query its direct section index 'to find the CBI section of subgroup B. After looking for this exact CBI segment, the chaotic block index is queried to find the third logical segment in the chaotic update block 7〇4 and the original block 702. If the CBI section result written after the table is not one of the four CBI sections of a given logical group, the indirect section index is queried for one of the four sections. In the example shown in Fig. 16E, the CBI area of the subgroup c is found. This CBI section of subgroup C then queries its direct section index to find the exact CBI section of subgroup B. This example shows that when querying a chaotic block index, it will find that the i th logical segment is unchanged and will find its valid data in the original block. The same considerations are also made when looking for the jth logical segment in a subgroup C of a given logical group. This example shows that the last written CBI section result is not any of the four CBI sections of a given logical group. Its indirect segment index points to one of the four segments of a given group. The last written result of the four pointed to is also the CBI section of subgroup C. When querying its chaotic block index, it will be found that the jth logical sector is found at the specified location in the chaotic update block 7〇4. There is a list of chaotic sections of the chaotic update blocks in the system in the controller RAM. Each list contains a record of the segment that was written to the chaotic update block since the last CB in the flash memory. The number of logical sector addresses (which may remain in the chaotic section list) for a particular chaotic update block is a design parameter for a representative value of 8 to 16. The optimal size of the list can be determined by the trade-off between the effect of the write-off of the chaotic data and the scan time of the zone during the initialization. During system initialization, in order to identify the valid segments written since the previous update of one of its associated CBI segments, each chaotic update block must be scanned. In the controller RAM, it will constitute a chaotic section of each chaotic update block > month early. It is only necessary to scan each block in the last written C BI section from the last sector address defined in the chaotic block information field of each block. When a chaotic update block is configured, the CBI section is written to correspond to all of the update stitch subgroups. The logical and physical addresses of the chaotic update block are written to the chaotic block information block available in the segment, where the null value entry is in the chaotic block index block. A list of chaotic sections will be opened in the controller RAM. When the chaotic update block is closed, the CBI section is written with the block logic and physical address removed from the chaotic block information field in the section. The list of corresponding chaotic sections in RAM becomes unused. The list of chaotic sections corresponding to the controller RAM can be modified to include a record of the section written to the chaotic update block. When the mixed |L section list in the controller RAM is not written to any free space recorded by other sections of the chaotic update block, the updated CBI section is written for the logical subgroup of the section in the list. And then clear the list. When CBI block 620 becomes full, the valid CBI section is copied into the configured erased block and the previous CBI block is erased. Address Table The logic-to-physical address translation module 14 shown in Figure 2 is responsible for associating the logical address of the host in the flash memory with the corresponding physical address. The mapping between logical groups and entity groups (relay blocks) is stored in the non-volatile flash memory 98680.doc -51 - 1272487 200 and the more volatile Raz 13〇 (see Figure 丨). A set of tables and lists that are distributed. The address list is maintained in flash memory containing the address of the relay block for each logical group in the memory system. In addition, the logical-to-physical address record of the most recently written section is temporarily retained in RAM. These volatile records can be reconstructed from the block list and the data section headers in the flash memory when the system is initialized after startup. Therefore, the address table in the flash memory only needs to be updated occasionally to reduce the percentage of over-utilization of the control data. The hierarchy of the address records of the logical group includes: a list of updated blocks opened in the RAM, a list of closed update blocks, and a group address table (GAT) maintained in the flash memory. The list of updated update blocks is a list of data update blocks currently open in the controller RAM for writing updated host segment data. The block's items are moved to the closed update block list when the block is closed. The closed update block list is a list of the data update blocks that have been closed in the controller RAM. A subset of the items in the list are moved to the section in the group address table during the control write operation. The Group Address Table (GAT) is a list of the relay block addresses of all logical groups of host data in the memory system. The GAT contains an item for each logical group that is sequentially ordered according to logical addresses. The nth item in the GAT contains the relay block address of the logical group with the address η. In a preferred embodiment, the GAT is a table in a flash memory containing a set of sectors (referred to as GAT regions) having items defining the relay block addresses of each logical group in the memory system. segment). In flash memory, the GAT segment is looked up in one or more 98680.doc -52 - 1272487 dedicated control blocks (called GAT blocks). Figure 1 7A shows the data field of the Group Address Table (GAT) section. The GAT segment can have a capacity of a GAT project that is large enough to contain a set of 128 consecutive logical groups. Each G AT segment consists of two components, namely a set of GAT entries for the relay block addresses of each logical group in the range, and a GAT segment index. The first component contains information for finding a relay block associated with a logical address. The second component contains information for finding all valid G AT segments within the GAT block. Each GAT project has three fields, namely: a relay block number, a page mark as previously described in connection with Figure 3 A(iii), and a flag indicating whether the relay block has been reconnected. The GAT section index lists the parts of the valid GAT section in the GAT block. This index will be replaced in each GAT segment but will be replaced by the version of the next written gat segment in the GAT block. Therefore only the version in the last written G AT section is valid. Figure 17B shows an example of recording a group address table (GAT) section in one or more GAT blocks. The GAT block is a relay block dedicated to recording the gAT sector. When the GAT segment is updated, it is written to the next available physical segment location in the GAT block 720. Thus, multiple copies of the GAT segment can exist in the GAT block, with only the last written copy being valid. For example, the gat area 4 and 25 5 (indicators containing the logical group LG3%8 _ LG4 〇 98) have been updated at least twice with the latest version of the valid version. A set of indices of the last written gap segment in the block identifies the location of each valid segment in the GAT block. In this example, the last written GAT segment in the block is the GAT segment 236, and its index group is a valid index group that replaces all previous index groups. When the GAT block becomes fully populated with the GAT segment, all valid segments are again written to 98680.doc -53 - 1272487 to the new block location to compress the block during the control write operation. Then erase the entire block. As described above, the G AT block contains items of a group of logically consecutive groups in the area of the logical address space. The G AT segments within the G AT block each contain 128 logically logical group mapping information for consecutive logical groups. Within the address range spanned by the GAT block, the number of GAT segments required to store all logical group items occupies only a small portion of the total segment location within the block. Therefore, the GAT segment can be written to the next available segment location in the block to update it. The index of all valid GAT segments and their locations in the GAT block is maintained in the index block in the most recently written GAT segment. A small portion of the total segment occupied by the active GAT segment in the GAT block is the system design parameter, which is typically 25%. However, there are up to 64 valid GAT segments in each GAT block. In systems with large logical capacity, it may be necessary to store GAT segments in more than one GAT block. At this time, each GAT block is associated with a fixed range logical group. G AT update execution can be part of the control write operation, which is triggered when the ABL runs out of configured blocks (see Figure 18). Its execution is performed with abl fill and CBL clear operation (4). During the GAT update operation, a GAT segment has a member whose GAT item is updated with the corresponding item in the closed update block list. The update will remove any corresponding from the Closed Update block list ((3) muscle). project. You I ^ 4 4 + for example ' will select the new GAT to be updated according to the first item in the list of updated update blocks. The update section can be written to the next available section location in the GAT block. When no segment location is available for the _0, t, updated GAT segment, 98680.doc -54 - 1272487 GAT rewrite operation occurs during the control write operation. The new GAT block will be configured and the valid GAT segment defined by the GA Buto will be copied in a sequential order from the complete gat block. Then erase the entire GAT block. The GAT cache memory is a copy of the sub-divided items of the 128 items of the GAT section in the controller RAM 130. The number of GAT cache memory items is a system design parameter with a value of 32. Each time an item is read from the gAT section, the corresponding segment sub-segmented memory is created. Multiple GAT caches will be maintained. The number is representative of the tin design parameters. GAT cache memory is overwritten based on items that have not been subdivided by different sections for the longest time. Erased Relay Block Management The erase block manager 16 shown in Figure 2 can manage the erase block using a list of maintained directory and system control information. These lists are distributed among the controller RAM 130 and the flash memory 2A. When the erased relay block must be configured to store the user data or the storage system control data structure, the next available relay area in the configuration block list (abl) in the controller RAM is selected. Block number (see Figure 15). Similarly, after the trunk block is removed and its day t is erased, its number is added to the clear block list (CBL) that is also retained in the controller. Relatively static catalog and system control data is stored in flash memory. These include a list of erased blocks that list the erased states of all the relay blocks in the flash memory, and a list of blocks that have been erased by the bit map () and the MAP system are stored in the individual sectors, and It is recorded in a dedicated relay block called "MAP Block". These lists, which are distributed in the controller RAM and flash memory, provide the level of the erased blocks 98680.doc -55 - 1272487 to effectively manage the use of erased blocks. Figure 18 is a schematic block diagram showing the distribution and flow of control and directory information for the use and recycling of erased blocks. The control and directory (4) are maintained in a list that is retained in the controller ram 13〇 resident in the flash memory 2 or in the MAp block 750. In the preferred embodiment, the controller RAM 13 保留 retains the configuration block list (ABL) 610 and the clear block list (CBL) 74 〇. As previously described in connection with Figure 15, the configuration block list (ABL) can record which relay block has been recently configured to store user data or store system control data structures. When a new erased trunk block must be configured, the next available trunk block number is selected in the configuration block list (ABL). Similarly, the Clear Block List (CBL) is used to record the updated relay blocks that have been unconfigured and erased. ABL and CBL are reserved in the controller RAM 13 0 (see Figure 1) for quick access and easy manipulation when updating blocks in the tracking effect. The configuration block list (ABL) records the configuration of the pooled and erased trunk blocks of the erased trunk block that will become the update block. Thus, each of these relay blocks can be illustrated by an attribute specifying whether it is an erased block, an open update block, or a closed update block in an ABL suspended configuration. Figure 18 shows that the ABL contains: an erased ABL list 612, an open update block list 614, and a closed update block list 616. In addition, associated with the opened update block list 614 is the associated original block list 615. Similarly, associated with the closed list of updated blocks is the associated erased original block list 617. As previously shown in Figure 15, these associated lists are a subset of the open update block list 614 and the closed update block list 616, respectively. The erased ABL block list 612, the opened update block list 614, and the closed update block list 616 are all subsets of the configuration block list (ABL) 610, in each list. The items have corresponding attributes. The MAP block 750 is a relay block dedicated to the erase management record in the flash memory 200. The MAP block stores a time series of MAP block segments, wherein each MAP segment is not an erase block management (EBM) segment 760, or a MAP segment 780. When the erased block is recirculated when the configuration is exhausted and the relay block is retracted, the associated control and directory data is preferably included in the logical section that can be updated in the MAP block, where the updated data will be updated. Each item is recorded in a new block section. Multiple copies of EBM section 760 and MAP section 780 may be present in MAP block 750, with only the latest version being active. The index of the location of the valid MAP section is contained in the field of the EMB block. A valid EMB segment is always written to the MAP block during the control write operation. When MAP block 750 is full, all valid sectors are rewritten to the new block location and compressed during the control write operation. Then erase the entire block. Each EBM section 760 contains an erased block list (EBL) 770, which is a list of subset addresses of the erased block population. The erased block list (EBL) 770 can be used as a buffer containing the erased block number, from which the relay block number is periodically taken to refill the ABL and periodically The block number is added to this buffer to re-empt the CBL. The EBL 770 can be considered as a buffer for the following: an available block buffer (ABB) 772, an erased block buffer (EBB) 774, and a cleared block buffer (CBB) 776. 98680.doc -57- 1272487 The available block buffer (ABB) 772 contains a copy of the ABL 6 10 project immediately following the previous ABL fill operation. It is actually a backup copy of the ABL after the ABL fill operation. The erased block buffer (EBB) 774 contains the erased block addresses previously transmitted from the MAP section 780 or the CBB list 776 (described below), and the addresses can be transmitted during the ABL fill operation. To ABL 610. The cleared block buffer (CBB) 776 contains the address of the erased block that has been transferred from the CBL 740 during the CBL clear operation and then transferred to the MAP segment 780 and the EBB list 774. Each MAP section 780 contains a bit mapping structure called "MAP". The MAP uses a bit of each of the relay blocks in the flash memory to indicate the erase status of each block. Bits corresponding to the block addresses listed in the ABL, CBL, or erased block list in the EBM section are not set to the erase state in the MAP. The block configuration algorithm will never be used in MAP, erased block list, ABL or CBL, any block that does not contain a valid data structure and is not designated as an erased block' therefore cannot access this Class blocks are used to store hosts or control data structures. This provides a simple mechanism to exclude blocks with defective locations from the accessible flash memory address space. The hierarchy shown in Figure 18 effectively manages erased block records and provides complete security for the list of block addresses stored in the controller's RAM. The erased block items can be exchanged between the list of block addresses and one or more MAP segments 780 in an infrequent manner. The information in the erased block list and the address translation table stored in the plurality of segments of 98880.doc -58 - 1272487 stored in the flash memory during system initialization after the power is turned off, and limited A small number of referenced data blocks in the flash memory are scanned to reconstruct the lists. The deduction used to update the hierarchy of erased block records can be configured using the erased block in the following order: the block from the map block 750 is in the address sequence The block address clusters from the CBL 740 are interleaved in the order in which they are updated by the host. For most of the trunk block size and system memory capacity, a single MAP segment provides a one-dimensional mapping for all of the relay blocks in the system. In this case, the erased blocks must be configured for use in the same address order as recorded in this MAP segment. Erase Block Management Operations As mentioned above, ABL 610 is a list of address items that can be configured to use erased blocks, and relay blocks that have recently been configured as data update blocks. The actual number of block addresses in the ABL is between the maximum and minimum limits of the system design variables. During manufacturing, the number of abl items that are formatted is a function of the type and capacity of the memory card. In addition, since the number of available erased blocks is reduced due to block failures during the lifetime, the number of items in the ABL is also reduced to approach the end of the system life. For example, after a fill operation, items in the 可 can specify blocks that can be used for the following purposes. Each block has a part of the project that is written to the data update block and does not exceed one to twenty items of the erase block of the limit update block of the largest update block that is simultaneously opened. , with = the four items of the erased block of the block. 98680.doc -59- 1272487 ABL Fill Operation Since the ABL 610 becomes exhausted due to configuration, it needs to be refilled. The operation of padding the ABL occurs during the control of the write operation. This is triggered by the fact that the block must be configured, but the ABL contains an erased block item that is not sufficient for configuration as a data update block or some other control data update block. During control writes, the ABL fill operating system and the GAT update operation are performed simultaneously. The following actions occur during the ABL fill operation. 1 • Retain ABL projects with the attributes of the current data update block. 2. Keep the abl item of the attribute of the data update block closed, unless an item of the block is being written in the simultaneous GAT update operation. 'In this case, the ABL will be removed from the ABL. project. 3. Keep the abl project for the unconfigured erase block. 4. Compress the ABL to remove the gap created by the removal of the item to maintain the order of the items. 5. Completely populate the ABL by appending the next available item from the EBB list. CBL Clear Operation CBL is a list of erased block addresses in the controller RAM. The restrictions in the block number of the block are the same as those in the ABL. Empty (3) [Operation of the operation control during the write operation. Therefore, it is updated with the 胤 心 ;; 夕 、, project and write it to CBB list 776. 98680.doc -60 - 1272487 MAP Exchange Operation When the EBB list 774 has been emptied, the MAP swap operation between the erase block information and the EBM section 760 in the MAP section 78 can occur periodically during the control write operation. . If all erased trunk blocks in the system are recorded in the EBM section 760, no MAP section 78 will exist and no MAP parent swap will be performed. During the MAP exchange operation, the MAP section for feeding the erased block to EBB 7 74 is considered to be the source MAP section 782. Conversely, the MAP segment used to receive the erased block from CBB 776 is considered a destination MAP segment 784. If there is only one MAP section, it can be regarded as the source and destination MAP section, which is defined as follows. The following actions are performed during the MAP exchange. 1 • Select a source MAP segment based on the incremental indicator. 2. Select a destination MAP segment based on the block address in the first CBB project that is not in the source MAP segment. 3. Update the target MAp section in the manner defined by the relevant project in the CBB and remove the items from the CBB. 4. Write the updated destination MAP segment into the MAP block unless there is no separate source MAP segment present. 5. Update the source map section ' in the manner defined by the relevant project in the CBB and remove the items from the CBB. 6. Add the remaining items in the CBB to the EBB. 7. The EBB is filled as much as possible using the erased sector address defined by the source MAP section. 8 - Write the updated source MAP section to the ]VIAP block. 98680.doc -61 - 1272487 9. Write an updated EBM section to the MAP block. List Management Figure 18 shows the distribution and flow of control and catalog information between various lists. For convenience, the operation of moving items or changing item attributes between list elements is identified as [A] to [0] in Fig. 18, as explained below. [A] When the erase block is configured as the update block of the master data, the project attribute in the ABL is changed from the erased ABL block to the open update block. [B] When an erased block is configured as a control block, its items in the ABL are removed. [C] When an ABL project with open update block attributes is created, the associated original block field is added to the project to record the original relay block address of the updated logical group. This information is available from GAT. [D] When the update block is closed, its project properties in the ABL are changed from the open update block to the closed update block. [E] When the update block is closed, its associated original block is erased, and the attribute of the associated original block block in the ABL item is changed to the erased original block. . [F] During the ABL fill operation, any closed update block whose address is updated in GAT during the same control write will remove its entry from abl. [G] During the ABL fill insertion, when the item that has closed the update area ghost is removed from the ABL, the item whose associated original block has been erased will be moved to 98680.doc 62- 1272487 [Η] In addition to controlling the block, the items it uses are added to the CBL. [I] During the ABL fill operation, the erased block item is moved from the EBB list to the ABL and assigned the attributes of the erased ABL block. [J] After modifying all relevant ABL items during the ABL fill operation, the block address in the ABL will replace the block address of the ABB list. [K] is performed simultaneously with the ABL fill operation during the control write, moving the items of the erased block in the CBL to the CBB list. [L] Move all related items from the CBB list to the MAP destination section during the MAP exchange operation. [M] Move all related items from the CBB list to the MAP source section during the MAP exchange operation. [N] After [L] and [M] during the MAP exchange operation, move all remaining items from the CBB list to the ebb list. [〇] After [N] during the MAP exchange operation, if possible, move items other than the items moved in [Μ] from the MAP source section to populate the EBB list. Logical to Physical Address Translation To find the physical location of a logical segment in flash memory, the logical-to-physical address translation module 140 shown in Figure 2 can perform a logical-to-physical address translation. In addition to the recently updated logical group, most of the translations can be performed using the Group Address Table (GAT) resident in the flash RAM 200 or the GAT cache memory in the controller RAM 130. The address translation of the recently updated logical group will require a list of addresses of the updated blocks that are primarily resident in controller RAM 130. Therefore, the logic of the logical sector address depends on the type of block associated with the logical group in which the physical address translation 98680.doc -63 - 1272487 is located and the logical group in which the sector is located. The types of blocks are as follows: • Complete block, sequential data update block, mixed data update block, and closed data update block. Figure 19 is a flow chart showing a logical versus physical address translation procedure. Essentially, the logical block address is used to query various update directories (for example, the updated update block list and the closed update block list) to find the corresponding relay block and entity segment. If the associated relay block does not belong to the update program, the directory information is provided by GAT. Logical to physical address translation includes the following steps: Step 800: Given a logical sector address. Step 810: Query the given logical address of the updated block list 614 opened in the controller RAM (see Figures 15 and 18). If the query fails, proceed to step 82, otherwise proceed to step 83 {). Step 820: Query the given logical address in the closed update block list 616. If the query fails, the given logical address does not belong to any part of the update program. • Proceed to step 87 for gat address translation. Otherwise proceed to step 86〇 for a closed update block address translation. Step 830: If the update block containing the given logical address is sequential, the process proceeds to step 840 to perform sequential update block address translation. Otherwise, proceed to step 850 for chaotic update block address translation. v v 840 • Use the sequential update block address translation to obtain the relay block address. Proceed to step 88. Step 850:|Use the chaotic update block address translation to obtain the relay block bit 98680.doc -64- 1272487. Proceed to step 880. Step 860: Use the closed update block address translation to obtain the relay block address. Proceed to step 880. Step 870: Use the group address table (GAT) translation to obtain the relay block address. Proceed to step 880. Step 8 8 0 ·· Convert the relay block address to a physical address. The translation method depends on whether the relay block has been reconnected. Step 890: The physical sector address has been obtained. These various address translation processes are described in more detail below: Sequential Update Block Address Translation (Step 840) From the information of the updated Update Block List 614 (Figures 15 and 18), the block association can be directly completed and updated sequentially. The address translation of the target logical sector address in the logical group is described below. 1 • From the “Page Mark” and “Writed Section Number” blocks of the list, it can be determined whether the target logical section has been configured in the update block or its associated original block. 2 • The relay block address suitable for the target logical segment can be read from the list. 3 • The appropriate “Page Mark” field determines the sector address within the trunk block. The chaotic update block address translation (step 85〇) and the address translation sequence of the target logical sector address in the logical group associated with the chaotic update block are as follows. 1. If it is determined from the list of chaotic sections in the RAM that the section is the most recently written section ', the address translation can be done directly from its position in this list. 98680.doc -65- 1272487 2. The most recently written section in the CBI block contains the entity address of the chaotic update block associated with the target logical sector address in its chaotic block data block. It also contains the displacement within the CBI block of the CBI section last written to this chaotic update block in the indirect section index block (see Figures 16A-16E). 3_The information in these fields is cached in the ram without having to read the section during subsequent address translation. 4. Read step 3 of the CBI section identified by the indirect section index field. 5. The direct segment index field cache of the recently accessed chaotic update subgroup is stored in RAM without the need to perform the read at step 4 to repeat the same chaotic update block. 6. The direct section index field read in step 4 or step 5 can then identify the CBI section associated with the logical subgroup containing the target logical sector address. 7. Read the hash block index entry of the target logical sector address from the CBI section identified in step 6. 8. The recently read chaotic block index block can be cached in the controller RAM without the need to perform the read at steps 4 and 7 to repeatedly access the same logical subgroup. 9. The Chaos Block Index item defines the location of the target logical section in the chaotic update block or associated original block. If the valid copy of the target logical segment is in the original block, it can be found using the original relay block and page tag information. Closed Update Block Address Transfer (Step 860) The address of the target logical sector address in the logical group associated with the updated block can be directly completed and closed from the information of the updated updated block list. 98880.doc -66- 1272487 (see Figure 18), explained below. 1 · k π 单中 can buy the relay block address assigned to the target logical group. 0 2. From the “Page Mark” block in the list, the block address in the relay block can be determined. G AT address translation (step 870) If the logical group* is subject to a reference to the block update list that is turned on or off, its entry in the GAT is valid. The address translation sequence of the target logical sector address in the logical group referenced by the GAT is as follows. 1. Evaluate the range of available GAT cache memory in RAM to determine if the target logical group's items are included in the GAT cache. 2. If the target logical group is found in step 1, the gat cache memory contains complete group address information, including the relay block address and page mark, thus allowing translation of the target logical sector address. 3. If the target address is not in the GAT cache, the GAT index of the GAT block must be read to identify the location of the G AT segment with respect to the target logical group address. 4. The GAT index of the last accessed GAT block will remain in the controller ram and can be accessed without reading the segment from the flash memory. 5 • A list of the relay block addresses of each G AT block and the number of segments written into each GAT block is stored in the controller ram. If the necessary GA index is not available at step 4, it can be read from the flash memory immediately. 6. Read the gat section about the target logical group address from the extent position in the block of the G A-segment 98680.doc -67- 1272487 defined by the G AT index obtained at step 4 or step 6. The gat cache memory is updated with a subdivision of the section containing the target item. 7. Obtain the target segment address from the relay block address and the "page tag" field in the target GAT project. Relay block-to-physical address translation (step 880) If the flag associated with the relay block address represents that the relay block has been re-linked, the associated LT segment is read from the BLM block to The erase block address of the target area 4 and the address is determined. Otherwise, it will be terminated from the relay block address - the block address is erased. Controlling Data Management Figure 20 shows the level of operation performed on the control data structure during the memory management operation. Data update management operations can work on various lists that reside in RAM. The control write operation can be performed on each of the flash memory, and can also interact with the control data section and the dedicated block in the RAM, and also exchange data in the list.

, CBL, and when the S erases a control block, when an item is written into the GA, it is written into a chaotic update block list. When the erased block is configured as an update area, the update block will be updated or the closed update block f will be updated. When a segment updates the update chaotic segment control write operation, the information 98880.doc -68 - 1272487 from the control data structure in the RAM is written into the control data structure in the flash memory, necessary The other supported control data structures in the flash memory and RAM are updated accordingly. Control write operations are triggered when the ABL does not contain any other items of the erased block that are to be configured to update the block, or when the CBI block is rewritten. In a preferred embodiment, the ABL fill operation, the CBL clear operation, and the EBM sector update operation are performed during each control write operation. When the MAP block containing the EBM segment is full, the valid EBM and MAP segments are copied to the configured erased block and the previous MAP block is erased. During each control write operation, writing a GAT segment also modifies the list of updated blocks that are closed. When the GAT block is full, a GAT rewrite operation will be performed. As described above, after a few chaotic section write jobs, a CBI section is written. When the CBI block becomes full, the valid CBI section is copied into the configured erase block and the previous CBI block is erased. As mentioned above, the MAP exchange operation is performed when there are no other erased block items in the EBB list of the EBM section. Each time the MAP block is rewritten, the MAP address (ΜΑΡΑ) section for recording the current address of the MAP block is written in the dedicated μAPA block. When the MAPA block is full, a valid MAPA segment is copied to the configured erased block and the previous APA block is erased. Each time the block is rewritten, the boot section is written to the current boot block. When the boot block is full, the valid boot sector of the current version of the boot block is copied to the backup version, which then becomes the current 98680.doc -69 - 1272487 version. The previous current version will be erased and become a backup version, and a valid boot section will be written back to it. Alignment of Memory Dispersed on Multiple Memory Planes As previously described in connection with Figures 4 and 5A-5C, in order to increase performance, more than 2 memory planes are operated in parallel. Basically, each plane has its own sensed amplification, and as part of the master and program circuitry, parallel services span the corresponding pages of the memory cells of the plane. When multiple planes are combined, the pages can be operated in parallel to improve performance. Another aspect of the invention is that a frame is organized into a plurality of smeared I: blocks and is composed of a plurality of memory planes (so that logical units can be read in parallel or a plurality of logical units can be programmed in parallel To such a memory array, when the original logical unit stored in the T-block of the specific memory is to be updated, the required logic unit is maintained to keep the logical unit of the I. In the same plane as the original. This can be done by the following equation: Record the updated logical unit to the τ_ available positions of the 4 blocks still in the same plane. Preferably, the logic unit is stored in the same displacement position as the other versions of the system, such that the given logic unit lean version is served by the same set of sensing circuits. In the preferred embodiment of the present invention, the current version of the logical unit is padded, and any intermediate between the upper-synchronized memory unit and the next available plane-aligned memory unit is After the stylized logical unit ',: the most important logical plane is located in the next available plane: the j version is in front of the logical unit in the meta:::::Memory The fill version can be completed by filling in the gap version 98680.doc -70- 1272487. In this way, all versions of the logical unit can be maintained in the same plane as the original and the same 4 shifts, so that in the waste project collection operation, it is not necessary to extract the latest version of the logical unit from different planes, and the performance is degraded. In the preferred embodiment of the t-item, the latest version can be used to update or fill each memory cell on the plane. Thus, the logical units can be ordered from each plane, which will have a logical order without further rearrangement. ... This scheme shrinks by allowing the latest version of the logical unit of the logical group to be rearranged on the plane and does not have to collect the latest version of the different memory planes: summarizing the time of the chaotic block. This is very advantageous, in which the validity of the host interface b specification can be used to complete the maximum waiting of the segment write operation by the memory system. Figure 21 shows a memory array composed of a plurality of memory planes. Memory: The plane can come from the same § memory wafer or multiple memory chips. Each plane 910 has its own read and program circuitry 912 to parallel pages 914 of the memory unit. Without loss of generality, in the example shown, the memory array has four planes that operate in parallel. In general, a logical unit is the smallest unit accessed by the host system. Usually a logical unit is a section of size 512 bytes. Pages are parallel in the plane Read or stylized t-large unit 1 A logical page often contains - or multiple logical units. Therefore, when a plurality of planes are combined, the maximum number of units read or programmed in parallel can be regarded as a relay page of the memory unit, wherein the relay page is composed of pages of planes of the plurality of planes. For example, 98680.doc -71 · 1272487, such as the MP 〇 relay page has four pages, that is, pages from the respective planes, ρ], and P3 where the logical pages LPQ, LP, LP2, A are stored in parallel. Therefore, the read and write performance of the memory is increased by four times compared to the operation in only _ planes. The %5 memory array is further organized into a plurality of relay blocks, such as ΜΒ〇, .., MBj', in which all memory cells in each of the relay blocks can be erased. For example, the MB 〇 relay block is composed of a plurality of memory: a logical page 914 for storing data, such as a logical page in a uvLIW A, dust block according to the order in which it is filled in the relay block. Distributed in four planes PG, pi, p2, and (d) in a predetermined sequence. For example, when logical pages are filled in a logically sequential order, the planes are accessed in a cyclical order of the first page in the first plane, the second page in the second plane, and the like. After the last time is reached, the padding is repeated in a loop to restart from the first plane of the next relay page. In this way, successive logical pages can be accessed in parallel when all planes are in parallel operation. And: t, if there is a parallel plane operation and the relay block is filled in a logical sequential order, the kth logical page in the relay block will be resident in plane X, where x = kM〇 Dw. For example, when there are four planes, the W and 4 junction logic fills the block sequentially, the $th logical page as will be resident in the plane given by 5 MOD 4, ie flat, as shown in Figure 。. The memory operation of each memory plane towel is performed by the _ group read/write circuit 912. The data entering and leaving each read/write circuit is transmitted through the bus lines 9 under the control (4). The control (4)-like buffer 922 can assist in the transmission of buffered data via the data bus. Yuri 98680.doc -72- 1272487 When the operation of the first plane requires access to the data of the second plane, a two-step procedure is required. The controller first reads the data of the second plane and then transmits it to the first plane via the data bus and the buffer. In fact, in most memory architectures, the transfer of data between two different locations requires the exchange of data through data bus 920. At a minimum, this involves transferring from a set of read/write circuits in a plane and then into another set of read/write circuits in another plane. In the case where the planar system is from a different wafer, it will need to be transferred between the wafers. The present invention provides a structure and scheme for memory block management to avoid accessing data from one plane to another to maximize performance. As shown in Fig. 21, a relay page is composed of a plurality of logical pages (each located in one of the planes). Each logical page may consist of more than one logical unit. When data is to be recorded on a logical unit by block in a block spanning the planes, each logical unit will fall into one of the four memory planes. Planar alignment issues occur when updating logical units. In the current example, for ease of explanation, the logical unit is treated as a logical segment of 5 12 bytes, and a logical page is also a logical unit wide. Since the flash memory does not allow a portion of the block to be written without first erasing the entire block, the update of the logical page is not written to the existing location, but is recorded in the block unused. In the location. The previous version of the logical unit is then considered to be obsolete. After some updates, the block may contain some logical units that have become obsolete due to the update. This block can then be said to be "not clean", and the obsolete item collection operation ignores the dirty logical unit and collects the latest version of each 98680.doc -73- 1272487 logical list s and re-records it in a logically sequential order. In multiple new blocks. (4) Wiping and recycling unclean blocks. When the Tian-Hai updated logic unit is recorded in the next unused location in a block, it is usually not recorded in the same memory plane as the previous version. When a waste project collection operation is to be performed, such as summary or 昼&’, the latest version of the logical unit will be recorded in the same plane as the original one to maintain the original order. However, if you have to extract the latest version from another plane, performance will be reduced. Thus, in accordance with another aspect of the invention, the original logical unit of the first block of the plane is given. This can be done by recording the updated logical unit to the next available location of the second block that is still in the same plane. In a preferred embodiment, the current version of the logical unit that is the same relative position as the original unit in the original block is filled (9), filled by copying any of the previous stylized memory units and The next available plane aligns the intermediate gap between the memory cells. Figure 22A shows a flow chart of a method with planar alignment updates in accordance with a general embodiment of the present invention. Step 950: In a non-volatile memory organized into a plurality of blocks, each block is divided into a plurality of (four) cells that can be erased, and each of the § memory cells is used. For storing data of a logical unit. Step 952: constituting the memory by a plurality of memory planes, each plane having a set of sensing circuits for parallel service memory pages, the memory page having one or more memory cells. Step 954: storing the first version of the logical unit in a first order in a first memory block of the first block of the 98680.doc -74- 1272487 version of the logical single block, and storing the plurality of memory cells in one of the memory planes The step team is stored in the second block according to a second version different from the first order: each subsequent version: = in the lower subunit of the same memory plane as the first version, so as to be available The same sense of the group: "Recalling all versions of the logical unit in the facet. ~_ Identical Figure 22A shows a preferred embodiment of the storage in the flow chart shown in Figure 22A. Step 956' of step V includes steps 957, 958, and 959. Steps to divide each block into relay pages, each

The flat-page is composed. This step can be performed at any of the storage steps. W (4) 958: According to the second order in which the first order is different, the logical list 4 = this is stored in the second block, and each subsequent version is stored in the page and the first (version) displacement. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , An example of a logical unit that writes blocks sequentially. This example shows that each logic (four) is large = one logical segment 'for example. , (3)... In the example of the four planes, the parent block (for example, MB°) can be regarded as being divided into a plurality of relay pages 98680.doc -75 - 1272487 MP〇, MP!, ···, where each relay page (For example, Mp〇) each contains four segments (e.g., LSO, LSI, LS2, and LS3), each segment coming from planes P0, P1, P2, and P3, respectively. Therefore, the block is filled into the logical units in the planes P〇, PI, p2, and p3 in a cyclical order, in the host write operation #1, and the logical sector LS5丄S8 is being updated. Information in the middle. The update will be LS5 and the _LS8% data will be recorded in the newly configured update block starting at the first available location. In master write operation #2, the block of the data in the logical section LS9-LS12 is being updated. The updated data is recorded in the update block immediately after the end of the last write. The figure shows that the way of two host writes is to record the update data in the update block in logical sequential mode, namely LS5, _LS12. The update block can be thought of as a sequential update block because it has been filled in a logically sequential order. The updated data recorded in the update block can be used to eliminate the corresponding data in the original block. However, the update logic segment is recorded in the update block based on the next available location but regardless of the planar alignment. For example, the segment LS5 is originally recorded in the plane P1 but the updated LS5 is now recorded. Similarly, all other update sections are not aligned. Figure 23B shows an example of a logical unit that writes a chaotic update block in a non-sequential order regardless of plane alignment. In host write operation #1, the logical segment LS1〇-LSU stored in the given logical group of the original relay block is updated. The updated logical section LS1〇'-Lsii' will be stored in the newly configured update block. At this point, update the 98680.doc -76- 1272487 block as a sequential update block. In the host write operation #2, the logical extents LS5-LS6 are updated to LS5'-LS6' and recorded in the update block immediately after the last write. This converts sequential update blocks into confusing update blocks. At host write operation #3, the logical segment LS 10' is updated again and recorded in the next position of the update block to become LS10". At this time, !^1〇" in the update block can replace the previous record. LS10' ' and LS10' can replace Lsl〇 in the original block. In the host write operation #4, the data of the logical section Ls1〇 is updated again and recorded in the next position of the update block to become LS10,,. Therefore, LS10,,, is now the last and only valid version of the logical segment LS10. All previous versions of Lsl〇 are now obsolete. In the host write operation #5, the data of the logical section LS30 is updated and recorded in the update block to become 1^3〇. In this example, it can be seen that logical units within a logical group are written to the chaotic update block in any order and with any repetition. Similarly, the update logic segment is recorded in the update block based on the next available location but regardless of the plane alignment. For example, the segment L § 1 〇 was originally recorded in plane P2 (i.e., MP2, third plane), but updated [si 〇, now recorded in P0 (i.e., MP〇', first plane). Similarly, in the host write #3 'the logical segment LS10 will be updated again to LS10' and placed in the next available position where the result is also in plane Ρ0 (the first plane of ΜΡΓ). Therefore, generally It can be seen from the figure that recording the update section to the next available position of the block causes the update section to be stored in a plane different from its previous version, with a sequential update of the plane alignment of the filled gap. Block 98680.doc -77- 1272487 Figure 24A shows a sequential update example of Figure 23A with plane alignment and padding in accordance with a preferred embodiment of the present invention. In host write operation #1, The data updated to LS5, -LS8, is recorded in the newly configured update block starting from the first available plane alignment position. In this example, LS5 is originally in P1, and ?1 is the second plane of the relay page. , the LS5'-LS7' will be programmed in the corresponding plane of the first available relay page Mp〇 of the update block. At the same time, the current version of the logical section LS4 in the front block will be relayed in the original block. Fill the unused number in ΜΙγ The gap of the plane. Then the original LS4 is processed into the eliminated data. Then the remaining LS8' is recorded in the first plane of the next relay page Mp〆 and is aligned in the plane. In the host write operation #2, The data updated to LS9, _LS12, is recorded in the update block of the next available + face alignment position. Therefore, the LS9 is recorded in the next available plane-aligned memory unit, that is, the first plane of Μ" At this point, no gaps are created and no padding is required. The update block can be thought of as a sequential update block because it has been filled in a logically sequential order. In addition, it will be updated by each logical unit and its original The same is in the same plane but planarly aligned. The chaotic update block with plane alignment with intermediate gaps Figure 24B shows the chaos of Figure 23B with plane alignment and without any padding in accordance with a preferred embodiment of the present invention. Update the example. In the host write operation #丨, the updated logical area is stored in the newly configured update block. It will not be stored in the next available one. In the unit, it is stored in the next available plane pair 98680.doc -78-1272487 memory unit. Since LS10, and LSI Γ are stored in planes Ρ2 and Ρ3 respectively (( of the original block> The third and fourth planes of 2), the next available plane-aligned memory unit will be in the third and fourth planes after the update block. At this time, the update block is non-sequential, which will be pressed The pages of "Unfilled", "Unfilled", LSI〇', and LSI 填充 are populated in the order of the relay page. In master write operation #2, the logical segment LS5-LS6 is updated to LS5 LS6 and recorded in the next available horizontally aligned update block. Therefore, the second (Ρ1) and third (Ρ2) planes of the original block or the LS5 and LS6 of the memory unit are programmed into the update block, and the available relay page MPi' Corresponding plane. This leaves the first unused plane in front of ΜΡι. At host write operation #3, update logical segment LS1〇 again, and record it in the next plane alignment position of the update block to become LS丨〇". Therefore, it will be written to the next available third. The plane, in Mp2, will leave a gap in the front in the first two planes of "B, the last plane and MP2'. This will eliminate the LS10 in the MP〇,. In host write operation #4, the data in the logical section 1^1〇, is updated again and recorded in the update block in the update block. , the next available third plane becomes LS10,,'. Therefore, LS10,,, is now the last and only valid version of the logical segment Lsi〇. This leaves a gap consisting of the last plane of MP2, and the two planes of MP/. In the host write operation #5, the data of the logical section LS3〇 is updated and recorded in the update block to become LS3〇. Since the original LS3〇 is resident in the P2 or 3rd plane of the relay page, it will be written to the next available plane in the update block 98680.doc -79 - 1272487. At this point, it will be the third plane of Μ". A gap will be created due to the last plane of MP3' and the first two planes of the MIV. Because the example shows that the plane alignment can be performed, in any order and any repetition, the multiple logical segments in the logical group are written into a chaotic _ _ ghost in the subsequent waste project collection operation, which will be conveniently All versions of a given logical section, especially the latest version, are serviced by the same sense and/or circuit. ~ Chaotic update block with plane alignment to fill the filled gaps. Figure 24C shows a chaotic update example of Figure 23A with planar alignment and padding in accordance with another preferred embodiment of the present invention. This operation is the same as that shown in Figure 24Β, but the intermediate gap is filled first with padding. In host write operation #1, the gap generated by the first and second unused planes of the relay page 填补ρ〇 is first filled with the current versions of ls8 and LS9 resident in the original block. This will eliminate 1^8 and 1^9 in the original block. At this time, the update block is a sequential update block, wherein the order of filling the relay page ΜΡ〇' is LS8, LS9, LS10, and LS11. In host write operation #2, a gap is created due to the first unused plane in the previous MPi, which will be padded with LS4 first. This will eliminate the LS4 in the original block. As before, the second write converts the sequential update block into a chaotic update block. In the host write operation #3, a gap is generated due to the last plane not used in MP!, and the first two planes of MP/. The last plane of MPi' is padded with LS7 after the last stylized LS6', and then the first two planes of MP2 are filled with the logical units (ie LS8 and LS9) before LS1. This will 98680.doc -80- 1272487 retire MP0, Lsl〇, and LS7_LS9 in the original block. In host write operation #4, a gap consisting of the last plane of the MIV and the first two planes of Μΐγ will be generated. The last plane of ΜΙγ can be filled by the last page written by the user uS1G in the relay page μρ2', and then the current version of the LS11 of the logic unit. The first two planes of Μιγ can be filled by lS9 respectively, and the relay page MIV A is the same as the previous logic unit. In the host write operation #5, it will also be followed by LSU, respectively. "And, come to the gap between the rear plane of the MP3 and the first two planes of the MP4'. Thus, this example shows that a plurality of logical segments within a logical group can be written into a chaotic update block in any order and any repetition, in a planar alignment manner. In a preferred embodiment, a relay page contains loop pages from individual planes. Since relay pages can be read or stylized in parallel, it is convenient to implement host updates at the granularity of the relay page. When there is any padding, it can be recorded with the update logic unit of the relay page. In the particular embodiment shown in the example of Figures 24A and 24C, during each host write, padding is performed on the memory bank it is not used before the programmatically updated memory plane is aligned. The action of any unused memory cells after the next-synchronized memory unit is delayed by the next host write. In general, any unused memory cells in the front will be filled in the boundaries of each relay page. In other words, if the previous gap spans over two relay pages, then the logical sequence of each relay page is logically sequenced and the padding is performed on each relay page, but regardless of the number of 98680.doc -81 - ^/ 2487 In the case of a (4) block, if it is a partial write, the subsequent page can be written by the following: In the other embodiment, the second fill: the full fill. Move to the next - relay page 7 The relay page filled with the file can be named. There are various changes that can be made depending on the flexibility supported by the individual memory architecture. The independent feature of the single-formed relay F-plane/item of the item or the deduction can be independently read and the pages of each page in the plane = face. The above example has the largest stylized unit to become a page. The relay page... can be programmed with local relay pages on all pages. For example, to relay the first three pages of the page, 'and then program the fourth page Γ, there is, in the plane layer, level 'a physical page can contain one or more memories two early ^ if each memory unit The data of one section can be stored, and the κ body page can store one or more sections. Some memory architectures can support: In the private encoding process, the selected logical units are privately advertised at different times. Logical unit alignment for chaotic updates of logical groups in the memory plane In the block memory management system, logical groups of logical units are stored in the original block in a logically sequential order. When updating a logical group, a partial 1-sided stylization is supported, in which a subsequent version of the logical unit is stored in the update block by suppressing the selected memory unit in the page. If the logical unit is stored confusingly (ie, 'non-sequentially') in the update block, the obsolete project collection is finally performed to collect the latest version of the original block and the logical unit in the update block to sequentially integrate it into the new original. Block. If all of the updated versions of the given logical singles 98880.doc -82 - 1272487 储存 are stored in the update block aligned with the original version in their original block, causing the same set of sensing circuits to access all versions, then the waste茱 Project collection operations will be more effective. According to another aspect of the present invention, in the above-described block memory management system, when five memory elements are organized into a series of memory pages (where each page of the memory unit is parallelized by a set of sensing circuits) If all versions of a given logical unit have the same displacement position in the stored page, then all versions are aligned. Figure 25 shows an example memory organization in which each page contains two memory cells for storing two logical units (e.g., two logical segments). In the original block, because the logical segments are stored in a logical sequential order, the logical segments LSO and LSI are stored in the page p〇, and the logical segments l; § 2 and LS3 are stored in the page. In 1, and the logical segments LS4 and LS5 are stored in the page P3. It can be seen that in the pages of the two sections, the page displacement of the first section from the left is "〇", and the page displacement of the second section is Γ 1". The updated logical segment is recorded in the update block when updating the logical group of logical segments sequentially stored in the original block. For example, the logical segment LS2 is resident in the page p〇 with the displacement r 〇" in the original block. If in the first write, if it will! When ^2 is updated to LS2', it will be stored in the first available location of the update block with the same page offset "〇". This will be in the first memory unit of page P0f. If LS5 is updated to LS5' in the second write, it will be stored in the first available position with the same page displacement "Working Update Block. This will be on page P1 with a displacement of "1" The younger brother is in the body unit. However, before storing LS 5 ', the latest version of the logical section that will maintain the logical sequential order at least in each page will be copied in 98680.doc -83 - 1272487 , to fill the p〇 with the displacement first. "未" is not used in the tenth body and the displacement "〇" in P1'. At this time, LS3 will be copied to P0, the displacement is "1" position, and LS4 is copied to ρι, and the displacement is "〇". If LS2 is updated to LS2" again in the third write, it will be stored in the displacement "〇" of P2. If LS22 and LS23 are updated to LS22' and LS23', respectively, in the fourth write, they are stored in the displacements "〇" and 1" of p3, respectively. However, before that, the unused memory cells with a bit shift of "1" in P2 are filled with LS3. The above update sequence assumes that individual sections can be programmed within the page. For a memory architecture where partial page stylization is not supported, the sections within the page must be stylized together. At this time, in the first write, (3), and LS3 will be programmed into p〇, medium. In the second write, [Μ and B 85 are initialized to P1'. In the third write, LS2,, and LS3 are programmed together into P2, and so on. Planar alignment within the relay page Alternatively, the stylized unit can have the granularity of the relay page. If the granularity of the writer's chaotic update block becomes a relay page, then the items of the CBI block towel described in connection with Figures 16A and i6B will be related to the page, rather than the segment. The added granularity will reduce the number of items that must be recorded for the chaotic update block' and allow the index to be directly eliminated at 5 noon and the single (four) segment 0 for each relay block. The memory structure of Figure 26A and Figure 21 is the same. Just that each page contains two sections instead of solid. Due to &, the relay page Μρ can be seen from the figure. Now each has its own 98680.doc -84 - 1272487 page that can store the data of two logical units. If each logical unit is a zone slave, the logical sections are sequentially stored in the plane and "I and the MP0 of LS2 and LS3 in plane P1. = 6B shows that the layout shown in Fig. 26A has a linear map layout. The relay block of the memory unit. In contrast to the single-segment page of Fig. 21, the logical segment is stored in a cyclic manner in four pages having two segments in each page. If there are w parallel-operated planes and each page has K hidden bodies 7L, the logical block sequentially fills the relay blocks, and the kth logical page in the relay block will be resident in the plane X, wherein x = k, _ W where k — INT(k/K). For example, there are four planes, W = 4, 2 segments per page, K = 2, then for k = 5, the fifth Logic section (3), which will reside in the plane given by 2, ie plane 2, as shown in Fig. 24A. One and the same, aligned. As usual, the same principle applies to the above example of implementing the above plane. In the case of a multi-flat, 垔 垔 面条 构 构 中 和 和 和 和 和 和 和 具有 具有 具有 具有 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ It is also advantageous to maintain the alignment of the segments in the page. In this way, the sensing circuit of the same group of Eclipse is beneficial to different versions of the same logical segment. V ancient effective execution such as segment reconfiguration and "money taking _Modify-Write" fall. Name 斟谳; and long-term m m 乍 when aligning the order of the segments within the page, you can

Use the same technique as aligning the page 盥 & &&# 』 J W ~ 面面. According to the specific system, it can be filled or robbed to prevent any intermediate gaps. Alignment of logical unit planes without filling Figure 27 shows an alternative scenario. Do not need to fill to recover from - 98684. Doc -85- 1272487 Get the other logical 仗 j仗 update block in the same block. The intersection of the update block and the update block can be regarded as the four buffers of the updated logical unit received from the plane alignment of the host. The next available memory is in the appropriate buffer. Each logical unit received from the host. & τ true complement, that is, the sequence of the program meta-address, there may be bait logic early in each plane. The number (4) logical unit is stylized in the chaotic update block, which can contain an updated version of all logical units of the logical relay page, as used for Μη. It can also contain all the logical units of the small two =, such as for the Mp, ▲ page with PMP 。. In the example of Mps, the corresponding original block MBG takes the missing logical unit Μ*. It is especially effective for the financial record in the record. In this way, all logical pages of a page can be fed in a single-parallel read operation, even if individual logical pages are not from the same column. , staged program error handling: When there is a program failure in the block, then all the materials to be stored in the block are usually private to another block and the failed block is marked as bad. Depending on the timing specifications of the operation in which the failure occurred, there may not be enough time to move the stored data to another block. The worst case scenario is a program failure during a normal obsolete project collection operation, where another identical obsolete project collection operation is required to reconfigure all data to another block. In this case, 'may be violated—the write latency limit specified for a given host/memory device, which is typically designed to accommodate 98680. Doc -86 - 1272487 Non-two) waste project collection operations. Figure 28 shows a scheme in which a defective block repeats the summary operation on another block when a program failure occurs during the summary operation. In this example, block 1 is the original block that stores the complete logical unit of the logical group in a logically sequential order. For ease of illustration, the original block contains sections A, b, c, and D, each of which stores a logical unit of a subgroup. When the host updates the special logical unit of the group, a newer version of the logical unit is recorded in the update block, block 2. As previously described in connection with the update block, depending on the host, this update can record logical units in a sequential or non-sequential (chaotic) order. Finally, the update block is closed for the progress update because the update block is full or for some other reason. When the update block (block 2) is closed, the current version of the logical unit resident on the update block or the original block (block 丨) is summarized on the new block (block 3) to form The new original block of the logical group. This example shows that the update block contains a newer version of the logical unit in sections B and D. For convenience, the sections B and D are displayed in the block 2 not necessarily at the position where they are recorded, but are aligned with their original positions in the block 1. In the summary operation, the current version of all logical units originally resident in the logical group of block 1 is recorded in the summary block (block 3) in sequential order. Therefore, the logical unit of the sector A is copied from the block i to the block 3, and then the block B is copied from the block 2 to the block 3. In this example, when copying the logical unit of the sector C from the block 1 to the block 3, the defect of the block 3 will cause the program to fail. One way to resolve a program failure is to restart the summary program on a brand new block (block 4). Therefore, sections A, B, C, and D are copied in block 98680. Doc -87- 1272487 1 The total operation of the dish in the defective block 3 results in the copying of up to two areas filled with logical units: Set to have the special _ tolerance of the completion _. For example, when writing: a memory device, it is expected that the write operation will be completed internally, and it is known as "writing 箄 zinc day 4 „ Between the w and the temple %”. When a memory device, such as a memory card, is busy writing data to the host, it will send a message. State to the host. If rBUSY η 士 士( 碌 」 状 W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W The time is completed by the write (update) operation and the summary operation or the write operation of the write wait time. The master has a write latency Tw which provides sufficient time to complete the write operation to update block 972 (Fig. 29(a)). As described above in the block management system, a host write to the update block can trigger a total operation of the capsule. Therefore, the timing also allows for summary operations other than updating the operating milk 2 (Fig. 29(B)). However, the rollup operation must be restarted in response to a failed rollup that will take too much time and exceed the specified writer wait time. According to another aspect of the present invention, during the memory operation of the memory I' having the block management system during the time-critical memory operation, the program failure in the block can be interrupted by the interrupt block (break〇ui bi〇ck). The stylized operation to handle later, in less urgent times, can transfer the data recorded in the failed block before the interruption to other blocks that may also be interrupt blocks. Then there is the block where Lai failed. In this way, when a defective block is encountered, the data will not be lost due to the need to transmit the data stored in the defective block immediately and exceed 98680. Doc -88- 1272487 The limit between % of the fingerprints can be processed. This erroneous handling is particularly heavy for the waste bins, so there is no need to repeat the entire job for a new block during an emergency. Thereafter, at a suitable time, the data of the defective block can be saved by reconfiguring to other blocks. Figure 3 is a flow chart showing the failure of the program according to the present invention. - Step 1GG2 - The non-volatile memory is organized into blocks, and each block is divided into memory cells that can be erased, and each memory unit can store data of a logical unit. Program Failure Handling (Phase 1) Step 1012. Store a series of logical unit data in the first block. Step 14 In order to respond to the storage failure of the first block after storing some of the logical units, the subsequent logical unit is stored in the second block which is the interrupt block of the first block. Program failure handling (final stage) v Step 020. In response to the predetermined event, the reverse order το stored in the first block is transferred to the third block, and the third block and the second block may be the same or different. Step 1022: Discard the first block. Figure 3 is a specific embodiment of a program failure handling in which the third (fetched reconfiguration) block is different from the second (interrupted) block. During Phase 1, a series of logical units are recorded on the first block. If the logical unit is from a host write, the first block can be considered an update block. If the logical unit is a summary from a compression operation, the first block can be considered heavy 98680. Doc -89- 1272487 New configuration block. If a program failure occurs in block 1 at some point, the port provides the second block as an interrupt block. Logical units that fail to record in the block and subsequent logical units are recorded on the interrupt block. In this way, no extra time is required to replace the failed block 1 and the data resident on it. In the intermediate phase II, all the recorded logical units in the sequence can be obtained between the block and the block 2. In the final phase III, the logical unit will be reconfigured to block 3, which can be used as a reconfigured block, to replace the failed block and the data resident on it, thus saving the data in the failed block. Then discard the failed block. The final phase is scheduled so that it does not conflict with the timing of any simultaneous memory operations. In this particular embodiment, reconfiguration block 3 and interrupt block 2 are differentiated. It is convenient for the Ting to record the interrupt block with additional logical units during the intermediate phase. HUb, the interrupt block has become an update block and may not be suitable for reconfiguring the logical unit of the defective block. Fig. 3 is a further embodiment of the failure handling of the 耘 type, wherein the third (last reconfiguration) block and the second (interrupted) block phase (f). The stage work and the same are the same as the first embodiment shown in Fig. 31. However, in the stage (1), the logical unit of the (4) trap block 1 is reconfigured to the interrupt block 2. This would be convenient if the additional logical unit other than the original sequence of the first 4 write operations recorded the interrupt block for 2 days. In this way, the block required to store the logical unit in question is the smallest. Specific Examples of Program Failure Dispositions During Aggregation Program failure handling is especially important during summary operations. Normal capsule operation 98680. Doc -90- 1272487 can summarize the current versions of all the logics that are resident in the original block and the updated block, if left-alpha, and the flat-ear group, to the summary block. During the period of the capsule IΑμ, if a program failure occurs in the 茱w block, it will benefit from the other block that is used as the interrupt 茱~, block to receive the remaining logical units. ,heart. According to this method, = copy the unit more than - times, (4) can complete the exception processing within the total: period. At the appropriate time, all the unprocessed logical units of the group are summarized to the interruption.  In the tail, you can complete the ... operation. The appropriate time will be the period during which you have time to perform the summary period. One such suitable time slot = another host with a new but unrelated capsule operation is written to the second level. The summary of program failure handling can be considered as multi-stage. In the first phase, after a program failure occurs, the logical unit 2 is totaled into more than one block to avoid summarizing each logical unit more than once. The final phase is completed at the appropriate time, where the logical group (4) is totaled into one block, preferably all logical units are collected in the summary block in a sequential order. Information on the unit of the unit Figure 32A shows a flow chart of the initial update operation that results in the overall operation of the capsule. Step 1102: Organize the non-volatile memory into blocks, and divide each block into memory units that can be erased. Each memory unit can store a logic V 11 G4 mussel material into a plurality of blocks. A logical group, each logical group being a group of logical units that can be stored in a block. Step 1112: Receive host data encapsulated in the logical unit. 98680. Doc -91 - 1272487 Step 1114: According to the first version of the first group, the younger version of the logical group that avoids the dog 1 is selected, and a*w is used to establish the original block of the logical group. Step 1116: According to the second shun, the second version of the logical unit including the logical group is stored in the second block, and the update block of the logical group is established. Step 1119: Execution of the obsolete item collection is performed in the above-mentioned part of the T&&event' to collect the logical version of the logic in the various blocks and re-record it to the new block. Figure 3B shows a flow chart of a multi-stage summary operation of a preferred embodiment of a library in accordance with the present invention. Summary Failure Disposition (Phase I) 1122 and Steps Summary of Error Handling, Stage Operation 112, contains step 1124. Step 112 2: store the target versions of the logical chest 4 and the early 70 of the logical group in the third block in the order of the first) itching; η ΑΛ丨丨 s - * ^ terms. To create a summary block of logical groups. Step U24: In response to the storage failure of the summary block, the logical units of the logical group not included in the third block are stored in the fourth block in the same order as the first sequence to provide an interrupt summary block. Since the data in block 1 and block 2 has been transferred to block 3 and block 4, block 1 and block 2 can be erased to free up space. In the preferred embodiment, block 2 to EBL (list of erased blocks, see Fig. 8) can be released immediately. Block 1 can only be released under the following conditions: if it is a closed update block and there is another block pointed to by the corresponding GA Ding project 0 98680. Doc -92- 1272487 On the shell, block 3 will become the original block of the logical group, and block 4 will become the block update block of block 3. After completing Phase I, the memory device sends a message to the host by releasing the BuSY signal. Intermediate Operation (Phase II) Phase II, intermediate operation 1130, can occur before the phase out of summary operation 114. As suggested by any of steps 1132, 1134, 1136, there may be several possible scenarios. Step 1132. Or, in the write operation of the logical group, the fourth block (interrupt summary block) is written as the update block. If the host writes the logical group in question, block 4, which is the interrupt summary block and which has now replaced the sequential update block, will be used as the normal update block. Depending on the host write, it can be maintained in a sequential or chaotic state. As an update block, it will trigger the closing of another chaotic block at some point, as described in the previous preferred embodiment. If the host writes to another logical group, it proceeds directly to the stage hi operation. Step 1134: In the read operation, the memory in which the third block is the logical group original block and the fourth block is the update block is read. At this time, the logical units of the sectors A and B are read from the block 3 of the original block of the logical group, and the logic of the sectors c and D are read from the block 4 of the updated block of the group. unit. Since only segments a and b can be read from block 3, pages that have failed to be stylized cannot be accessed, and portions that have not been written later cannot be accessed. Although the GAT directory in the flash memory has not been updated and it still points to 98680. Doc -93- 1272487 Block 1 of the original block, but does not read any data from it, and this block itself has been erased earlier. Another possibility is that the host reads the logical units in the logical group. At this point, the logical units of segments A and B are read from block 3 of the original block for the logical group, and the logic for reading segments c and D from block 4 for the sequential blocks of the group. unit. Step 1136: or in power-on initialization, by scanning the contents to re-identify any of the first to fourth blocks. Another possibility in the intermediate phase is to turn off the power to the memory device and then restart. As described above, during power-on initialization, the block in the configuration block list (the erase block block to be used, see Figure 及5 and Figure 18) is scanned to identify the original block that has become a special state in the logical group. Defect summary block (block 3) and associated sequential update block (block 4). The flag in the first logical unit of the interrupt block (block 4) will indicate that the associated block is the original block that has encountered a program error (block 3). Block 3 can be found by looking up the block directory (GAT). In a specific embodiment, the flag is programmed to the first logical unit of the interrupt summary block (block 4). This can assist in indicating the special state of the logical group. That is, it has been aggregated into two blocks, namely, block 3 and block 4. An alternative to using flags to identify logical groups with defective blocks, using features that are not as full as the original block (unless the error occurred on the last page, and there is no ECC error on the page after the fetch). The block is a defective block. Also, depending on the embodiment, there will be an information record about the failed group/block of the control data structure stored in the flash memory, and 98680. Doc -94- 1272487 No /, 疋 is written in the interruption of the general block (block flag. Free 4) brother - section of the header area is completed (stage III) Step 1142: in response to the scheduled The event, for the first case when the fourth block is not further recorded since the stage, in the same order as the first order, where the current version of all unprocessed logical sheets of the logical group is stored; For the second case when the fourth block has been further recorded since the stage], the third and fourth blocks are summarized into the fifth block. /Step 1144: Afterwards, for the first case, when the memory is operated, the total block of the fourth block is used as the original block of the logical group; for the second case, when the memory is operated, the fifth block is used. Raw as a logical group: Block: The final summary in Phase III can be performed as long as there is any chance that it will not violate any of the restrictions between the four (4). Preferably, when there is another update operation of a logical group that does not have a capsule total operation, "pigw" is placed on the next host write time slot. If the host writer of another logical group triggers its own obsolete item ^, the stage 汇总 summary will be postponed. Figure 3 3 shows an example sequence of the first and final stages of a multi-stage rollup operation. The host write latency is the width of each host write slot with duration 1. The host write i is a simple update, and the current version of the first set of logical units in the logical group is recorded on the associated update block. At host write 2, an update occurs on logical group LGI, causing the update block to be closed (eg, full). A new update block is provided to record the remaining updates. Providing a new update block will trigger the collection of abandoned items, resulting in a closure of 98680. Doc -95- 1272487 The summary operation of LG# to recycle the blocks to be reused. The current logical unit of the LG4 group is recorded in the sequential block in sequential order. The summary operation can continue until a defect is encountered in the summary block. It is then called Phase I summary, where the summary operation continues on the interrupt summary block. At the same time, the final summary of LG4 (Phase III) will wait for the next opportunity. A write to the logical unit of logical group lg2 also occurs at host write 3' to trigger LG. Summary. This means that the time slot has been fully utilized. At host write 4, the operation simply logs some of the logical units of the 仏 to its update block. The time remaining in the time slot provides an opportunity to perform the final summary of LG4. DETAILED DESCRIPTION OF THE INVENTION Example of the phase I and phase III operations of the multi-stage 适用 适用 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Fig. 34A shows an example in which the interrupt summary block is not used as an update block but as a summary block whose summary operation has been interrupted. In particular, the figure "A" refers to the host "#2' shown by %, where the host writes an update belonging to the logical unit called the logical group, and during this time, this operation also triggers association with another logical group LG4. A summary of the blocks. The original block (block 1) and the update block (block 2) are formed in the same manner as the example of the map μ. Similarly, during the summary operation, the summary region peak 3 is known to be defective in the logical unit of the total segment C of the capsule. However, unlike the re-aggregation scheme shown in Figure ^, the multi-stage scenario can continue the summary operation on the newly provided block (block 4) that can be considered as the interrupt summary block. Therefore, the I-segment I summary operation has been in the summary block (block 3) in the total capsule segment A and = 98680. Logic block of doc -96- 1272487. When a program failure occurs in the summary block, the remaining logical units in blocks C and D are sequentially copied to the interrupt summary block (block 4). If the host originally writes the update in the first logical group triggers the summary operation of the block associated with the second logical group, the update of the first logical group is recorded to the update block of the first logical group. (usually a new update block). At this point, the interrupt summary block (Block 4) will not be used to record any update data outside of the summary operation and will maintain the interrupt summary block that must be completed. Since the data in blocks 1 and 2 is now completely contained in another block (block 3 and block 4), it can be erased for recycling. The address table, (GAT), is updated to point to block 3 as the original block of the logical group. The directory information of the update block (in the ACL, see Figure 15 and Figure 18) is also updated to point to the block 4 of the sequential update block that has become a logical group (eg, LG4). The summary logic The group is not confined to one block, but is distributed over the defect block (block 3) and the interrupt summary block (block 4). An important feature of this scenario is that the logical units in the group will only be aggregated once during this phase, but the summary is spread over more than one block. In this way, the summary operation can be completed within the normally specified time. Figure 34B shows the third and final stages starting from the multi-stage summary of Figure 34A. As described in connection with Figure 33, the phase 执行 茱 will be executed at a suitable time after the first phase (e.g., during subsequent host writes that do not trigger the accompanying summary operation). In particular, Fig. 34A refers to a time slot in which the host write #4 shown in Fig. 33 occurs. During this period, the host write can update the logical unit belonging to logical group lg2 without triggering another additional summary operation. Therefore, there are 98680. Doc -97- 1272487 facilitates the operation of the remaining period μ phase m in the time slot to complete the aggregation of the logical group LG4. This operation summarizes all unprocessed logical units of LG4 that are not yet in the interrupt block into the interrupt block. In this example, this means that the section AAB is copied from block 3 in logically sequential order to the interrupt block (block 4). Due to the wraparound scheme of the logical unit in the block and the use of the page mark (see Figure 3A) 'even if the example is displayed in block 4, the segments 8 and 6 will be recorded after the segments C and D, but will still be The sequence of records is considered to be equivalent to the sequential order of A, B, c, D. Depending on the embodiment, it is preferred to obtain from the block 3 the current version of the unprocessed logical unit to be copied, since it is already in a summarized form, but it can also be used from blocks that have not been erased. 2 collected. After the final summary is completed on the interrupt block (block 4), it is designated as the original block of the logical group and is updated with the appropriate directory (eg, GAT, see Figure 17A). Similarly, the failed physical block (block 3) is marked as bad and is excluded. Other blocks, blocks and blocks 2 will be erased and recycled. At the same time, the update of LG2 will be recorded in the update block associated with LG2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INTERRUPTION ACCUMULATION BLOCKS FIG. 35A and FIG. 35B respectively show a second case of Phase I and Phase III operations of the multi-stage summary of the examples of FIGS. 28 and 33. Figure 3 5 A shows an example in which the interrupt summary block is maintained for the receiving block written by the receiving host instead of the total block. This applies to host writes such as updating logical group lg4, and in this program, it also triggers the sum of the same logical group. As in the case of Figure 34A, the combination of Block 1 and Block 2 in Block 3 will be 98680. Doc -98- 1272487:Into the 仃' until the program failed to process the section c. The summary is then continued on the interrupt summary block (block 4). After summarizing the unprocessed 70-degree logical unit (eg, in section C&D) in the interrupt block (block 4), it does not wait for completion of the logical group summary in phase III, but maintains the interrupt area. Blocks are Update Blocks This case is particularly suitable for situations where a host writes an updatable logical group and triggers a summary of the same logical group. In this example, this records the record of the host update of the logical group LG# in the interrupt summary block (block 4) instead of the new update block. This update block (previously the interrupt summary block (block 4)) can be sequenced or confusing based on the host data recorded therein. In the example shown, block 4 has become confusing because the subsequent newer version of the logical unit in segment C causes the previous version in block 4 to be phased out. During the intermediate phase, block 3 will be treated as the original block of LG#, and block 4 will be the associated update block. Figure 35B shows the third and last 13⁄4 segments starting from the multi-stage summary of Figure 35a in the second example. As described in connection with Figure 33, Phase III summary will be performed at the appropriate time after the first phase, as during subsequent host writes that do not trigger the accompanying summary operation. During this period, the host writes can update the logical units belonging to the logical group without triggering another additional summary operation. Therefore, it is advantageous to use the time remaining in the time slot for the phase III operation to complete the aggregation of the logical group LG4. The discarded items of logical group L G4 are then collected from block 3 and block 4 to the new summary block (block 5). Block 3 is then marked as bad, block 4 is recycled, and the new summary block (block 5) becomes the new logical group LG* 98680. The original block of doc -99- 1272487. Other blocks, Block 1 and Block 2, will also be erased and re-circulated. Other Specific Embodiments of Phased Program Failure Handling The examples described in Figures 31A, 31B, 34A, 34B, 35, and 35 are applicable to a preferred block management system in which each physical block (relay block) Only logical units belonging to the same logical group are stored. The invention is equally applicable to other block management systems in which no logical group is aligned to a physical block, such as the block management system disclosed in WO 03/027828 and WO 00/49488. Some examples of implementing a phased program failure handling method in these other systems are shown, for example, in Figures 36A, 36B, and 36C. Figure 36A shows a phased program error handling method for the case where the host write triggers the shutdown of the update block and the update block is sequential. The closing in this example is accomplished by copying the remaining valid data (B and C) of the original block 2 to the sequential update block 3. In the example where the program in the data part c stylized starting point fails, part C is programmed to the reserved block 4. The new host data can then be written to the new update block 5 (not shown). Phases II and III of this method are the same as in the case of a closed block. Fig. 36B shows a staged program error handling method applied to (local block system) in the example of updating the update block. In this example, the logical group is stored in the original block 1 and other update blocks. The summary operation includes copying the data of the original block 1 and other update blocks 2 to one of the update blocks (block 3 in the figure returned according to some rules). The main difference from the already explained case is that block 3 has been partially written. Figure 36C shows a staged program error handling the collection of abandoned items, or 98680. Doc -100- 1272487 does not support cleanup in the memory block management system mapped to the logical group of relay blocks. Such a memory block management (cyclic storage) system is described in WO 03/027828 A1. The obvious feature of the circular storage system is that it does not configure blocks for single-logical groups. It supports multiple logical groups of control data in the relay block. The collection of obsolete items involves the removal of blocks from the partially eliminated blocks. The valid data segments that may not have any relationship (random logical block addresses) are taken to the reconfigured blocks where there may already be some data. If the reconfigured block becomes full during operation, another block will be opened. Non-Sequential Update Block Index In the above paragraph regarding chaotic block indexing and in conjunction with Figures 16a-16e, the CBI section can be used to store an index that can record logical sector locations that are randomly stored in a chaotic or non-sequential update block. According to another aspect of the present invention, in a non-volatile memory having a block management system supporting an update block having a non-sequential logic unit, an index of a logical unit buffering a non-sequential update block stored in the RAM is Stored regularly in non-volatile memory. In a specific embodiment, the index is stored in a block dedicated to storing the index. In another specific embodiment, (3) storing the index in the update block. In yet another specific embodiment, the index is stored in the header of each logical unit. In another aspect, the logical singles written after the last index update but before the next index update store their index information in the header of each logical unit. In this way, after the power supply is interrupted, it is not necessary to perform a scan during initialization, and the position of the most recently written logical unit can be determined. In yet another aspect, the block & component is partially and partially non-sequentially directed to more than one logical subgroup. 98680. Doc -101 - 1272487 Index metrics for CBI segments stored in CBI blocks after a predetermined trigger event. According to the scheme described in connection with Figures 16A-16E, the list of recently written segments in the chaotic block is retained in the controller. In RAM. The CBI section containing the latest index information is written to the flash memory (CBI block 620) only after a predetermined number of writes to the logical group associated with the given chaotic block. In this way, the number of CBI block updates can be reduced. The list of recently written segments in the logical group is retained in the controller RAM before the next update of the CBI segment in the logical group. This list will be lost when the memory device encounters a power down, but can be rebuilt by scanning the update block during initialization after power is turned on. Figure 37 shows a scheduling example of writing a CBI section to an associated chaotic index section block after writing the same logical group every N sectors. This example shows two logical groups LG3 and LGU that are updated simultaneously. Initially, the logical segments of [(^) are stored in the original block in sequential order. The updates of the logical segments in the group are recorded in the associated update block in the order specified by the host. This example shows confusion. The sequence is updated. At the same time, the logical group fGU is updated in the same way as its update block. After each logical sector is written, its location in the update block is retained in the controller RAM. After each predetermined trigger event, the current index of the logical segment in the update block is written to the non-volatile hash index segment block in the form of a chaotic index segment. For example, a predetermined trigger event may occur in each After N writes, where N is 3. Although the examples provided relate to the lean logic unit as a segment, it should be understood by those skilled in the art that the logical unit may also be some other aggregate, such as containing a segment or The page of a group of sections. Also, the 98680 in the sequential block. Doc -102- 1272487 A page is not necessarily a logical page, because the page mark that is wrapped around may be the first page. Index index of the CBI section stored in the chaotic update block after the predetermined trigger event. In another specific embodiment, the index indicator is stored in the chaotic update block itself after each write. In the CBI section. This scheme is the same as the specific embodiment in which the index is also stored in the CBI section. The difference is that in the above specific embodiment, the CBI section is recorded in the CBI section block, not in the update block itself. This method is based on keeping all chaotic block index information in the chaotic update block itself. 38A, 38B and 38C respectively show the state in which the updated blocks of the CBI section are also stored in three different stages. Fig. 3 8 A shows an update block in which the c B j section is recorded until after a predetermined number of writes. In this example, after the host has sequentially written to logical section 〇-3, then another version of private 7 that is written to the logical section 发出 will be issued, thus destroying the sequential sequence of data writes. The mixed IL block index carried in the cBI section is then implemented, and the update block is converted into a chaotic update block. As mentioned above, CBI is an index of the index of all logical sections containing chaotic blocks. For example, the 0th item represents the displacement of the update block of the second logical section, and likewise, the nth item represents the displacement of the nth logical section. The CBI section can be written to the next available location in the update block. In order to avoid frequent Shaanxi flash memory fetching, the CBI segment will be written after each ^^ data segment is written. In this case, 'N is 4. If power is lost at this time, the last written segment becomes a CBI segment and this block is treated as a chaotic update block. 98680. Doc - 103 - 1272487 Figure 38B shows the update block of Figure 38A in which the logical sections 1, 2 and 4 are recorded after the index section. A newer version of logical section 丨 and 2 replaces the old version previously recorded in the update block. In the case of the power cycle at this time, the last written segment must be found first, and then up to 1^ segments must be scanned to find the last written index segment and the most recently written data segment. Figure 38C shows the update block of Figure 38B with another write to trigger the logical segment of the next record of the index sector. Another current version of the CBI section can be recorded in the same update block after another (N==4) sector write. The advantage of the /匕 scheme is that there is no need for separate CBI blocks. At the same time, there is no need to worry about whether the additional data area of the physical flash zone is large enough to accommodate the number of items required for the index of the valid section in the chaotic update block. The chaotic update block contains all the information, and the address translation does not require external data. This makes the algorithm simpler, which reduces the number of control updates for CBI block compression; it also makes the concatenation control update shorter. (See above for section (10) Block Management). ::There is a tribute to the most recent write section of the data section header in the chaotic update block: On the other hand, after the fine write, the index will be recorded in the A 单元 单元 unit. The current information stored in the non-volatile memory and the logical unit of the middle writer is stored in the additional item written in each logical unit. "In this way, after the power is restarted, it is not necessary to sweep the ghost" It can be written from the section of the port and then added to the additional part of the file. The information about the logical unit written after the index of the previous one is updated. The θ display is stored in the chaotic update area. An intermediate index written between the headers of each data section in the block, 98680, doc -104 - 1272487. Figure 39B shows an example of storing an intermediate index of intermediate writes in each section header of the writer. After writing four segments ls〇_lS3, the C index is written as the next _ segment in the block. Thereafter, the logical (four) segments LS, LS, 2, and Lb are written. Block. Each time, the header stores the index of the wipes of the logical unit of the writer since the last CBI index. The header in the call will have an index that provides the displacement (ie, position) of the upper CBI index and the LSS. Similarly, the header in 'ls4 will have the upper-cm index and 1^'1 and 1^. The index of the displacement of '2 (ie, position). The data section after the write always contains information about up to N last written pages (ie, the CBI section until the last write). The (four) time 'up-CBI index can provide index information written by the logical unit before the CBI index section, and the index information of the logical unit of the subsequent writer can be found in the header of the last written data section. This has the advantage that it is not necessary to scan the block for the sector to be written later to determine its position during initialization. The scheme of storing the intermediate index information in the header of the data section is also applicable to the CBI index sector. Updating the block itself or in a separate CBI section block, as described above. Indexing indicators stored in the chaotic update block data section headers In another embodiment, the entire CBI index will be stored In the chaotic update block The additional item portion of each data section. Figure 40 shows the information in the chaotic index block stored in the header of each data section of the chaotic update block. The section header has limited information capacity and can therefore be used by any single zone. Section 98680. The index range provided by doc -105 - 1272487 is designed as part of a hierarchical indexing scheme. For example, a section within a particular plane of memory can provide an index to a section that is only within that plane. There is also the ability to divide the range of logical addresses into sub-ranges to allow for an indirect indexing scheme. For example, if a segment with 64 logical addresses can be stored in a plane, then each segment can have 3 clamps for the segment displacement value, and each shelf can store 4 displacement values. The first clamp defines the logical displacement range (M5 ' 15-31 '32_47, and the physical displacement of the last written segment within 48_63. The first stop can define 4 subranges of each 4 segments within its relevant range. The value of the body displacement. The third block defines the value of the body displacement of the four segments in its associated sub-range. Therefore, by reading the indirect displacement values of up to 3 segments, the chaotic update can be determined. The physical displacement of the logical section within the block. The advantage of this scheme is that there is no need for a separate CBI block or CBI section. However, this only applies to the additional data area of the physical flash sector large enough to accommodate the confusion. When updating the number of items required for a valid section index in a block. The limited logical range within a logical group of chaotic update blocks is within a logical group, which reduces the logical range of segments that can be written out of order. The main advantages of the technology are as follows: Since only one multi-session page needs to be read (in the multi-wafer example, the page can be read in parallel), all the data of the destination page can be obtained (assuming the source and destination are aligned, if Not aligned, you need To be read another, so that the copy of the sequential write data can be completed more quickly 'so the extent outside the range is kept in the original block, and the waste collection operation can be performed in a shorter time. Also, using the replica feature on the wafer, you can copy the data from the source to the destination without transferring data back and forth between the controllers. If the source is 98680. Doc -106 - 1272487 It has been a problem, as happened in a chaotic area, you need to read up to - pages per section to collect all the segments to be written to the destination. In a specific embodiment, 'there is not actually limiting the logical range to a certain number of segments, but by limiting the number of CBIs (only limiting the confusion of large groups/relay blocks is reasonable, Because it requires multiple chaotic block indexes to cover the entire logical group range). For example, if a relay block/group has 2048 segments, it would require up to M@cm segments, each covering a contiguous logical range of 256 segments of a subgroup. If the number of cBIs is limited to 4, the chaotic block can be used to write up to 4 subgroups of any of the segments (any one of them). Therefore, the logical group is allowed to have up to 4 partial or complete chaotic subgroups, and at least 4 subgroups will remain fully sequential. If a chaotic block has 4 active CBI segments associated with it, and the host writes a segment outside of these CBI segments (chaotic subgroups), then the chaotic logical group should be closed. But this is highly unlikely, because in real applications, the host does not need more than 4 256 segments of chaos (subgroups) in the 2048 segment range (logical group). As a result, under normal circumstances, the collection of obsolete items will not be affected, but the precautions of the restriction rules form an extreme example of the waste collection being too long (which will trigger the host's timeout). Partially sequential chaotic update block index When a sequential update block is partially written before converting the block to the chaotic management mode, all or part of the sequential update segment of the logical group may continue to be processed to have been sequentially updated, And chaotic update management can only be applied to a subset of the address range of the logical group. Control data integrity and management 98680. Doc -107· 1272487 Data stored in a memory device may become corrupted due to a power interruption or a specific memory location becoming defective. If a memory block defect is encountered, the data is reconfigured to a different block and the defective block is discarded. If the error does not increase, the error correction code (ECC) stored with the data can be corrected during execution. However, there will still be times when Ecc can't correct the depleted material. For example, when the number of error bits exceeds the capacity. This is unacceptable for key information such as control information associated with the memory block management system. An example of the control data is the directory information and the block configuration information of the memory block management system: as described in connection with FIG. As mentioned above, the control can be held in the ν-speed RAM and the slower non-volatile memory block. Any of the frequently changed control data will be maintained with regular control writes: to update the equivalent information stored in the non-volatile relay block. Sexual but slower flash ‘, the body stores control data in non-volatile 1 as shown in Figure 20 in GAT, CBI, MAP, and. Therefore, the level of the shell material structure will be maintained in the flash memory π = π operation description control information structure information key data backup Π 4 control data structure. I. Another material of the present invention, if maintained by n's, such as partial or total control data, is performed in a county-by-case manner; = the item is used in two 'services' additional levels of reliable surname technology to continuously program the same cardiac memory system Nowadays, L and the body are multi-dimensional. Any stylized mismatch in the sub-encoding process 98680. Doc -108- 1272487 Unable to destroy the first-attack write abort, ^t, process establishment data. Copying also helps detect Ding, detect false positives, and (P, two copies have good: ECC but the data is not J-day plus the jaws and other New Zealand has been considered.,, 17 sin. Some techniques for data replication are in a specific embodiment. ^ ^ Two copies of the given data are programmed for storage in the Germanized encoding process, and the subsequent stylized encoding process can avoid the program mode. In German: At least one memory unit. In this way, the programmatic coding process in the post-production is in the case of & ^ 4 绝 ^ ^ 1 ❿ 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在At least one of the two transcripts will not be subjected to another specific example, and two copies of the sheep's heart will be stored in two different blocks, and the 荨At most one of the two replicas, only one of the memory cells of the right is prepared for the sequel, and θ is programmed in the following stylized encoding process. In another specific embodiment, in a box of scorpions Two, a private data encoding process to store a given data After replica, figurines five X m ^, inflammation of the heart-Jun is no longer present in the complex for these two memory storage. The unit group implements any further / privateization. This can be achieved by arranging the two copies of the memory in the final stylized coding process of the memory unit group. In yet another embodiment, the two copies of a given data can be programmed into a multi-state memory in a binary stylized mode, such that the programs are not The memory unit is subjected to any further stylization. In yet another embodiment, the program is used for two encoding processes 98680. Doc -109- 1272487 ^Technology for multi-byte memory systems that continuously program multi-bits of the same set of memory cells 'will use fault-tolerant codes to encode multiple memory-like sorrows, enabling earlier stylized coding processes The information created will not be affected by errors in subsequent stylized coding. The complexity of data replication can be caused in multiple state memories in which each memory unit can store more than one bit of data. For example, a 4-state memory can be represented by two bits. One prior art technique is to program this memory using a two-pass encoding process. The first bit (lower page bit) can be programmed by the first encoding process. Thereafter, the same unit can be parsed in the second encoding process to represent the desired second bit (the upper page bit > in order to avoid k and the value of the first bit in the second encoding process, The state of the first bit of the memory state depends on the value of the second bit. Therefore, during the stylization of the second bit, if an error occurs due to a power interruption or other reasons, and an incorrect memory state is caused, The value of the first bit is also destroyed. Figure 41A shows the threshold voltage distribution of the 4-state memory array when each memory cell stores two bits of data. These four distributions represent four memory states. The total of U", "X", rY" and "z". Before staging the memory soap 7L, it will be erased to its "U" or "unwritten" state. When stylized, it will progressively reach the memory states "χ", "Y" and "z". ^", Figure 41B shows the existing two-coded program stylization scheme using Gray code. These four states can be Two bit representations, ie, the lower page bit and the upper page Faces, such as (upper page bit, lower page bit). For pages that are to be stylized in parallel, there are actually two logical pages 98680. Doc -110- 1272487 Face: The page below the logic and the page above the logic. The first-stylized encoding process /, will redeem the logic below the page. With proper encoding, instead of resetting the page below the logic, the subsequent second stylized encoding process on the same page of the unit will normalize the page above the logic. The commonly used code is Graymar, where ', there are self-bits that change when transitioning to an adjacent state. Therefore, this code has the following advantages: There are fewer requirements for error correction, because only the axe and one bit. The general scheme for using Gray code is to assume that Γ1" stands for "unprogrammed" conditions. Therefore, the erased memory state Γυ" can be expressed as] above page two! The page below the yuan is a bit. ,1). In the one-person encoding process of the page below the stylized logic, any unit storing the data "0" will therefore have its logical state transition from (X, 1) to (X, G), where "X" represents the upper two bits. "Any (d〇n丨t care, /古^^ care)" value. However, since the upper direction is of the formula:, in order to be consistent, "Γχ" can be marked as "," and the error is represented by "轾" as the memory state "X". That is to say, before the second program encoding process, the lower azimuth value "〇" can be expressed as a memory state. Performing a second encoding process stylizes the bits of the page above the logic. Only these need to be in the upper page bit of the 1-4. After the first encoding process, page "-7' is programmed in the logic state (1,1) or (1,〇). In order to save the value of the page below in the second encoding process, you must read "〇" or 4" in the lower position. For the transition from (i, g) to (Μ): ; the memory unit is programmed into the memory state "γ". For the transition from 〇 υ to (°, 1), the memory unit is stylized into a memory shape 98680. Doc -111 - 1272487 State "z". In this way, during the reading, by deciding the state of the memory in the unit, the lower page bit and the upper page can be decoded: However, the two encoding process of the Gray code is programmed in the program. When it is wrong, it will become a door. For example, the stylization of the square page bit into "〇" in the lower azimuth will cause (U) to change her.累To reorganize the memory unit from "U" through "χ" and Γγ to Ζ". If a power interruption occurs before the stylization is completed, the unit will end in the transition memory state... "X". When reading: Memory Sheet 70, "Χ" is decoded into logic state 0, G). This pair of upper ^ : square : yuan causes an incorrect result 'since it should be (〇, υ. Similarly, if the stylization is financially broken when it reaches "γ", it will correspond to (〇, 〇). The upper position is now correct, but the lower position is still wrong. So 'I see the problem of stylized above the page can damage the bedding already on the page below. Especially when the second coding process is programmed (4) In the state, the program towel will cause the stylization to end in the memory, resulting in the decoding of the lower page bit. The heart map 42 shows the defense by __ heart. For example, sections A, B, C, and D can be stored in a duplicate copy. If there is data corruption in a section copy, then another one can be read instead. Figure 43 shows where the copy section will normally be The non-soundness stored in the multi-state memory. As described above, in the exemplary modal memory, the multi-face actually includes the logical lower page and the logical upper page which are respectively programmed in the two encoding processes. In the example, the page is A wide area segments. Thus, eight segments are stylized and will also copy at logical 98,680. Doc -112- 1272487 In the same way, the same is true for section B and its copy. Then, in the subsequent stylized second encoding process in the logical upper page, sections C, C are also programmed simultaneously, and for section D, D as well. If the program is aborted in the middle of the stylized section C, C, it will destroy the service A, A in the page below. Unless the page section below is read and buffered before the top page is stylized, the damage will not be restored. Therefore, storing a copy of two key data at the same time, such as section A, A, cannot prevent it from being damaged by the problematic storage of subsequent sections C, C in its upper page. Figure 44A shows a specific embodiment of storing a copy of a key material staggered copy into a multi-state memory. Basically, the lower page, that is, the segments A, A and the segments B, B, are stored in the same manner as in Fig. 43. However, in the upper page simplification, the section C&D is interleaved with its copy into c, C, D. If local page stylization is supported, the copies of the two segments c can be programmed at the same time as well as for the duplicates of the two segments D. If 两个k to abort the two segments, only the next page will be destroyed on one copy of segment A and one copy of segment B. Another copy will remain unaffected. Therefore, if there are two copies of the key data stored in the first encoding process, then ^ ♦ does not affect the simultaneous stylization of the first encoding process. Fig. 44B shows another specific embodiment in which only the copy of the key data is stored in the logical upper page of the multi-character. At this time, the data of the following page is not used. The key data and its copy, such as section A, A and the section 'broken to the logical upper page. In this way, if there is a program abort', the key data can be written to another logical upper page, and any damage to the following page data will not matter. This method is basically Use each 98680. Doc -113- 1272487 Half the storage capacity of the ugly page. Figure 44C shows another embodiment of a duplicate copy of a key material stored in a binary mode of multiple state memories. At this point, each memory unit is programmed in binary mode, with only its limit range divided into two areas. Therefore, only one encoding process is stylized, and stylization can be restarted in different locations when the occurrence of the program is aborted. This method also uses half the storage capacity of each multi-state page. The operation of the multiplexed memory system in binary mode is described in U.S. Patent No. 6,456,528, the entire disclosure of which is incorporated herein by reference. Figure 45 shows yet another embodiment of simultaneously storing a copy of the key material to two different relay blocks. If one of the blocks becomes unavailable, the data can be read from another block. For example, key data is contained in sections A, B, C, D and E, F, G, Η and 1, 尺, 尺, B. Each section will be stored in the copy. These two copies will be written to two different blocks, block 0 and block 1. If you write a copy to the lower logical page, another copy will be written to the logical upper page. In this way, there will always be a copy of the page that is stylized to the top of the logic. If a program aborts, it can be reprogrammed to another logical top page. If the next page is corrupted, there will always be another copy of the upper page in the other blocks. Figure 46 is a diagram showing a copy of a copy of a key material simultaneously stored using a fault tolerant code. Fig. 46 and Fig. 4 show the limit voltage distribution of the 4-state track array and are shown as a reference for Fig. 46?. The fault-tolerant code ^ can avoid any upper surface of the transition in any intermediate state ^ 98680. Doc -114- 1272487. So under the hundred &< b The first encoding process of the page, the logic state (1,1) is changed to (1 V, if the memory state of the table is not erased, the value of the memory is "υ" is "γ" In the second encoding process of the page above, the suffrage η and the page bit below the page are "1", then the logic state (1,1) turns = (G, 1) 'If the stylized erased memory state "U" is Χ", if the lower page bit is "〇", the logic state (1, 〇) changes to (0, ... as represented as stylized The memory state "γ" is "ζ." Since the dead page is only programmed to be the next adjacent memory state, the program can not change the lower page bit. The serial copy of the key data is copied. It is better to write people at the same time as above. Another way to avoid the two copies of U Bay on the same day is to copy the copy of the book. This method is slower. The 4 copies themselves represent whether they are stylized when the controller checks two copies. Success. Figure 47 shows the possible status and data of two copies of the data. If the first and second copies do not have an Ecc error, the stylization of the material can be considered to be completely successful. Valid data can be obtained from either copy. If the first copy does not have an ECC error, but the second copy has an Ecc error. The unformatted form is interrupted in the middle of the second copy of the stylization. The first copy contains valid data. Even if the error is correctable, the second copy of the data is relied upon. If the first copy has no ECC error and the second copy has been emptied (Erase) means that the stylization is broken after the end of the first copy stylization but before the start of the second copy of 98680.doc -115- 1272487. The first copy contains valid data. If the first copy has ECC The error and the second copy have been emptied (erased), and the table is not privately interrupted in the middle of the first-replica stylization. Even if the error is correctable, the first copy still contains invalid data. The following techniques are preferred because they utilize the existence of a duplicate replica. Read and compare two replicas. In this example, the states of the two replicas shown in Figure 47 can be used to ensure that Any error misdetection. In another embodiment, the controller reads only one copy, and in order to account for speed and simplicity, the replica read is preferably rotated between the two replicas. For example, reading at the controller When the data is controlled, it can be read as a copy, and the next control read (any control read) should come from the copy 2, then the copy jade, etc. In this way, the two copies can be read and periodically checked. Integrity (Ecc k check). It can reduce the following risks. · It can't detect in time errors caused by spoiled data retention. For example, if you usually only read the copy}, the copy 2 will gradually deteriorate to The error cannot be saved by the ECC and the second copy can no longer be used. Preemptive Data Reconfiguration As described in connection with Figure 20, the block management system maintains a set of control data in the flash memory during its operation. . This group of control data is stored in the same relay block as the host data. As a result, the control data itself is subject to block management and is therefore subject to updates and, therefore, to the waste collection operations.

It also describes the hierarchy of control data, where the control data in the lower level is updated more frequently than in the higher level. For example, assuming that each control block has N 98680.doc 116, 1272487 control segments to be written, the following sequence of control updates and control block reconfigurations typically occurs. Referring again to Figure 20, every N CBI updates can fill the CBI block and trigger CBI reconfiguration (rewrite) and MAP updates. If the chaotic block is closed, it will also trigger a GAT update. Each GAT update can trigger a MAP update. Each N GAT update fills the block and triggers the GAT block reconfiguration. In addition, when the MAP block becomes full, it also triggers the MAP block reconfiguration and the MAPA block (if it exists, otherwise the BOOT block points directly to the MAP). In addition, when the MAPA block becomes full, MAPA block reconfiguration, BOOT block update, and MAP update are also triggered. In addition, when the BOOT block becomes full, it will trigger the BOOT block reconfiguration in the action of another BOOT block. Since the formation of the hierarchy is: the top BOOT control data, followed by MAPA, MAP, and then GAT, therefore, in every N3 GAT updates, there will be "serial control update", in which all GAT, MAP, MAPA and BOOT The block will be reconfigured. In this case, there is also an obsolete item collection operation (ie, reconfiguration or rewriting) when the GAT update is caused by a chaotic or host update block closure due to host writes. In the case of a collection of obscure update blocks, the CBI is updated, which also triggers CBI block reconfiguration. Therefore, in this extreme case, it is necessary to collect a large number of discarded items of the relay block at the same time. As can be seen from the figure, each control data block of the hierarchy has its own periodicity in obtaining padding and accepting reconfiguration. If the control data blocks are normal, then the following situation will occur: the stages of a large number of blocks are reorganized, thus triggering a large number of reconfiguration wastes involving all of these blocks at the same time. 98680.doc 117- I272487 = Project collection. The reconfiguration of many control blocks will take time to report ... so it should be avoided because some hosts do not tolerate long delays due to extensive control. 4. According to another aspect of the present invention, in the non-volatile=memory with the block management system, the "control waste collection" of the memory block can be implemented. ^Preemptive reconfiguration" (4) A large number of updates are avoided. The blocks happen to be ^ and need to be reconfigured. This can happen, for example, when updating control data that is used to control the operation of the block management system. The hierarchy of control data types can coexist with varying degrees of update times, causing their associated update blocks to require collection or reconfiguration of obsolete items at different rates. There will be more than one specific number of simultaneous collections of waste items that control the type of feed. In extreme cases, the reconfiguration phase of all update blocks of the control data type is reorganized, causing all update blocks to be reconfigured at the same time. The present invention avoids this undesirable situation in which the current memory gymnastics can accommodate spontaneous collection of waste items at any time, and the preemptive reconfiguration of the update block can occur before the block is completely filled. In particular, the priority will be given to the block with the highest level data type of the slowest rate. In this way, after reconfiguring the slowest rate block, another relatively long-term collection of obsolete items is no longer needed. Also, there are not many reconfigurable concatenations that can be triggered by the more recent recovery rate blocks in the hierarchy. The method of the present invention can be considered to introduce a certain amount of jitter into the overall mixture of things in order to avoid phase alignment of the various blocks in question. Therefore, as soon as there is a chance, you can reconfigure some of the slightly-filled blocks that are not completely filled with the margins of 98680.doc -118- 1272487. In systems where the lower control data in the hierarchy becomes faster than the control data hierarchy of the higher control data in the hierarchy due to the concatenation effect, the priority is provided to the higher control data blocks in the hierarchy. An example of an opportunity to perform a spontaneous preemptive reconfiguration is when the host write itself cannot trigger a reconfiguration, so any remaining time in its wait time can be utilized for preemptive reconfiguration. In general, the margin before the block that must be reconfigured is the predetermined number of unwritten memory cells before the block is full. What is considered is a margin sufficient to accelerate the reconfiguration before the fully populated block, but not too early, to avoid wasting resources. In a preferred embodiment, a predetermined number of unwritten memory cells are between one and six memory cells. Figure 48 is a flow chart showing the memory block of the preemptive reconfiguration storage control data. Step 1202: The non-volatile memory is organized into blocks, and each block has been divided into memory units that can be erased together. Step 1204 · Maintain different types of data. Step 1206: Assign a hierarchy to different types of data. Step 1208 - Store updates to the different types of data in the plurality of blocks such that each block substantially stores the same type of data. Step 1210: In response to a block having less than a predetermined number of empty memory cells and having the highest hierarchical data type of the plurality of blocks, the current update of the data of the block is reconfigured to another block. If it is not interrupted, go to step 1208. 98680.doc -119- 1272487 范例 The example algorithm for the preemptive reconfiguration of the control data shown in Figure 0 is as follows: 士果(G has any collection of discarded items due to user data) or (MAP has 6 or y, everyone's 丄田 ^ port A 吏 less unwritten segment) or (GAT left 3 or less unwritten segments) then if (BOOT left one is not written Section) Reconfigure B00T (ie, reconfigure to block) Otherwise, if (ΜAPA has 1 unwritten segment) then reconfigure MAPA and update MAP otherwise (MAP has 1 unwritten segment) )

Then reconfigure] MAP No Bay J If (the last update or the largest GAT has 1 unwritten segment)

Then reconfigure GAT or if (CBI leaves 1 unwritten section)

Then reconfigure CBI or leave otherwise. Therefore, preemptive reconfiguration is usually done when no usage occurs. 98680.doc -120-1272487 When the data is discarded. Preemptive reconfiguration of a spontaneous reconfiguration of a block in the Trigger User Data Discard item. In the worst case, when each host writes the collection, but there is enough time to perform the day, one control block can be executed at a time. Since the user data is discarded and the control update may occur at the same time as the entity error, 'It is better to have a larger security margin, ^ by pre-emptive re-emptive if you have 2 or more unwritten memory files (such as 'segments) in the block beforehand. Collection or control of waste Xin project collection. While the various aspects of the invention have been described in terms of specific embodiments, it is understood that the invention is intended to be β [Simplified illustration of the drawings] Fig. 1 is a schematic view showing main hardware components suitable for implementing the memory system of the present invention. & Figure 2 shows a memory group managed by a memory manager of a controller in accordance with a preferred embodiment of the present invention, organized into zones or relay blocks. Figure 3(1)-3A(iii) illustrates a mapping between logical groups and relay blocks in accordance with a preferred embodiment of the present invention. Figure 3B is not intended to show the mapping between logical groups and relay blocks. Figure 4 shows the alignment of the structure in the relay block and the physical memory. Fig. 5A shows a relay block composed of a minimum erasing unit that connects different planes. 98680.doc -121 - 1272487 Figure 5B shows a particular embodiment in which a minimum erase unit (MEU) is selected from each plane to link to a relay block. Figure 5C shows another embodiment in which more than one meu is selected from each plane to link to a relay block. Figure 6 is a schematic block diagram of a relay block management system implemented in a controller and flash memory. Fig. 7A shows an example of writing a section of a sequential update block in a sequential order in a logical group. Figure 7B shows an example of a logical group in which a segment of a chaotic update block is written in a chaotic order. Figure 8 shows an example of writing a segment of a sequential update block in a logical group in sequential order due to two separate host write operations with interrupts at logical addresses. Figure 9 is a flow diagram of a program for updating the data of a logical group for displaying an update block manager, in accordance with a general embodiment of the present invention. Figure 10 is a flow diagram showing the flow of updating the data of a logical group by the update block manager in accordance with a preferred embodiment of the present invention. Fig. 11A is a flow chart showing in detail a summary procedure for closing the chaotic update block shown in Fig. 10. Figure 11B is a flow chart showing in detail the compression procedure for closing the chaotic update block shown in Figure 10. Figure 12A shows all possible states of a logical group, with possible transitions between various operations. Figure 12B is a table listing the possible states of a logical group. 98680.doc -122- 1272487 Figure 13A shows all possible states of the relay block and their possible transitions under various operations. A relay block is an entity group corresponding to a logical group. Figure 13B is a table listing the possible states of a relay block. 14(A)-14(J) are state diagrams showing various operational effects on the logical group state and on the physical relay block. Figure 15 shows a preferred embodiment of the configuration block list (ABL) structure for recording the open and closed update blocks and the configured erased blocks. Figure 16A shows the data block of the Chaotic Block Index (CBI) section. Figure 16] 3 shows an example of a chaotic block index (CBI) section recorded in a dedicated relay block. Figure 16C is a flow diagram showing the access to the logical section of a given logical group for a chaotic update. Figure 16D is a flow diagram of data for a logical section of a given logical group for which a display access is chaotically updated, based on an alternative embodiment in which the logical group has been partitioned into subgroups. Figure 16E shows an example of a chaotic block index (CBi) section and its functions in a specific embodiment in which each logical group is partitioned into a plurality of subgroups. Figure 17A shows the data block of the Group Address Table (GAT) section. Fig. 17B shows an example of a group address table (GAT) section recorded in a GAT block. Figure 18 is a schematic block diagram showing the distribution and flow of control and catalog information for the use and recycling of erased blocks. Figure 19 is a flow chart showing the physical address translation logic program. Figure 2 shows the level of operation performed on the control data structure 98680.doc -123- 1272487 during the memory management operation. Fig. 21 shows an array of memories composed of a plurality of memories. Figure 22A is a flow chart of a new method not in accordance with the present invention. An example of having a planar alignment Figure 22B shows a preferred embodiment of Figure 28. The step of storing the update step in the mind map = the example of the logical 7L of writing the sequential update block in the sequential order regardless of the plane alignment. Figure 23B shows. An example of writing a chaotic update area in a non-sequential order, regardless of plane alignment. Fig. 24A shows an example of a sequential update of Fig. 23A in accordance with the present invention, a rare earth, a yoke example having a plane and a fill. Figure 24B shows a chaotic update example of Figure 23B with planes & without any padding, in accordance with a specific embodiment of the present invention. Figure 24C shows an example of a chaotic update of Figure 23B with planar alignment and padding in accordance with another preferred embodiment of the present invention. Figure 25 shows an example memory organization in which each page contains two memory cells for storing two logical units (e.g., two logical segments). The memory of Fig. 26A and Fig. 21 has the same structure except that each page contains two sections instead of one. The figure shows the relay block shown in Fig. 26A with the memory arranged in a linear pattern. The alternative shown in Figure 27 is as follows: You can make a plane alignment in the update block without having to fill it from one location to another. 98680.doc -124- 1272487 Figure 28纟, the staff is not in the missing block in the summary operation a, the program will fail to repeat the summary operation on another block when the program fails. Figure 29 is a schematic diagram showing a host write operation with a timing or write latency that allows sufficient time to complete the write (update) operation and the summary operation. Figure 30 is a flow chart showing the failure of the program to be processed according to the general scheme of the present invention. Figure 31A shows a specific embodiment of the failure handling of the program, wherein the third (last reconfigured) block and the second (interrupted) block are different. . Figure 3B shows another embodiment of a program failure handling in which the third (last reconfiguration) block is the same as the second (interrupt) block. Figure 32A shows a flow chart for the initial update operation that caused the summary operation. Figure 32B shows a flow chart of a multi-stage summary operation in accordance with a preferred embodiment of the present invention. Figure 33 shows an example sequence of the first and final stages of a multi-stage rollup operation. Fig. 34A shows an example in which the interrupt summary block is not used as an update block but as a summary block whose summary operation has been interrupted. Figure 34B shows the third and final stages starting from the multi-stage summary of Figure 34A. Fig. 35A shows an example in which the interrupt summary block is maintained as a newer block written by the receiving host instead of the summary block. Figure 35B shows the third and final stages starting from the multi-stage summary of Figure 35A in the second example. Figure 3 6 A shows the set of program error handling methods used when the host write triggers the shutdown of the update block and the update block is sequential. 98680.doc -125- 1272487 Figure 3 6B shows the staged program error handling method applied to the (local block system) in the updated example of the update block. Figure 36C shows a staged program error handling a discarded item collection operation, or a cleanup in a memory block management system that does not support a logical group mapped to a relay block. Figure 37 shows an example of scheduling a cbi segment to write to an associated chaotic index sector block after writing the same logical group every N segments. Fig. 38A shows an update block in which a section is recorded until after a predetermined number of writes. Fig. 38B shows an update area in which the data pages 1, 2, and 4 are recorded further after the index section of Fig. 38A. Figure 3 8C shows the update block of Figure 3 8B with another write to trigger the logical segment of the next record of the index segment. Figure 3 9 A shows the header of each data segment stored in the chaotic update block. An intermediate index written in the middle. Figure 39B shows an example of storing an intermediate index of intermediate writes in each of the written sector headers. Figure 40 shows the confusion stored in the headers of each data section of the chaotic update block. Indexing information in the booth. Figure 41A shows the threshold voltage distribution of the array of memory cells when each memory unit stores two bits of data. Figure 41B shows the existing encoding process using Gray code (Gray(3)(4)) Stylized scheme. Figure 42 shows the side 98864.doc -126- 1272487: by means of storing the copied sections to protect the key data. The column can be stored in the complex: 3 = Γ Data corruption can read another one In the middle of the multi-state memory, the copy state is usually stored in the multi-state memory. Figure 44 shows a specific embodiment of storing the duplicated copy of the duplicated data in the multi-memory. Figure 4 4 B shows only the key Another embodiment of the copy of the data is stored in a logically upper page of the multi-memory. Figure 44C shows a further embodiment of storing a duplicate copy of the key material in a binary mode of multiple state memory. Another embodiment in which a copy of the key material is simultaneously stored to two different relay blocks. Figure 46A and Figure 41A show the limited voltage distribution of the 4-state memory array and are shown as a reference for Figure 46B. Figure 46B shows yet another embodiment of a copy of a duplicate of key data stored using a fault tolerant code. Figure 47 is a table showing the possible states of two data copies and the validity of the data. Figure 48 shows the preemptive reconfiguration storage. Flow chart of the memory block of the control data. [Main component symbol description] 1 Defective block 2 Interrupt block 3 Reconfigure block 98680 .doc -127 - 1272487 10 Host 20 Memory System 100 Controller 110 Interface 120 Processor 121 Selective Sub Processor 122 Read Only Memory (ROM) 124 Selective Programmable Nonvolatile Memory 130 Random Access Memory Body (RAM) 132 Cache Memory 134, 610 Configuration Block List (ABL) 136, 740 Clear Block List (CBL) 140 Logical Pair Physical Address Translation Module 150 Update Block Manager Module 152 Sequential Update 154 Chaos Update 160 Erase Block Manager Module 162 End Block Manager 170 Relay Block Link Manager 180 Control Data Exchange 200 Memory 210 Group Address Table (GAT) 220 Chaotic Block Index (CBI) 230 , 770 erased block list (EBL) 98680.doc -128- 1272487 240 MAP 612 erased ABL block list 614 open update block list 615 associated original block list 616 closed update block Listing 617 erased original block list 620 CBI block 700 logical group 702 original relay block 704 chaotic update block 750 MAP block 760 erase block Management (EBM) Section 772 Available Block Buffer (ABB) 774 Erased Block Buffer (EBB) 776 Cleared Block Buffer (CBB) 780 MAP Section 782 Source MAP Section 784 Purpose MAP segment 910 plane 912 read and program circuit 914 page 920 controller 922 buffer 930 data bus 98680.doc 129-

Claims (1)

1272487 X. Patent application scope: 1 · A method for storing more data in a non-volatile memory organized into a plurality of blocks, wherein each block is divided into a plurality of blocks that can be erased together a memory unit, each memory unit for storing data of a logical unit, the method comprising: arranging: the memory is organized into a series of pages, and all the memory units in each page are subjected to a set of sensing The circuit is parallel service; - the data is organized into a plurality of logical groups, each logical group is divided into multiple logical units of data; the first _# page-by-page - a plurality of logical groups A: The 帛 version of 70 is stored in the first block, so that each logic is stored in the page and the right ~ 八 八 has a memory unit for the 疋 displacement; Second, the logical second of the logical group, 'storing the subsequent version of 诘φ 礼 in a page-by-page manner in the second zone exemption' allows the subsequent versions of the parent to be stored::: displacement displacement The next one Memory 2::; 2 sense circuit group to access - all versions of the logic unit 2. If the method of requesting the item, further including ··, the version is rich in the subsequent version of the storage logic unit - one available The memory unit is true in each page, in the same way as the first order spleen: no, the memory unit is used. ,: The current version of the logical unit is copied 3. As in the method of claim 1, further including... 98680.doc 1272487 Using multiple memory planes to form a page into a tissue-connected page =:: Zhao' each The flats are all serviced in parallel by the group_circuit; (4) the units in the four (4) units are organized into a series of medium averages in the mountain-/M shells' parent relay page: solid plane A memory page is formed, so - relaying. 'All memory cells are served in parallel by a plurality of sensing circuits. 4. The method of claim 3, further comprising: in the subsequent storage of the subsequent version of the logic unit, the next available memory mask _, the gatekeeper Fill the parent-relay page' body unit, II I, any unused memory is early, the way is copied according to the first-order. In the current version of the series, each of the logical units stores one page per page, wherein each page stores one, /, and 5 hai non-volatile memory. 5. The method of any one of claims 1 to 4, Host data section. 6. The method of any one of claims 1 to 4, the data of the logical unit. 7. The method of any one of claims 1 to 4, the data of the above logical unit. 8. The method of any one of claims 1 to 4, comprising a plurality of floating gate memory cells. 9. The method of any one of claims 1 to 4, which is a flash EEPROM. /, Λ 记忆 memory 10. The method of any one of claims 1 to 4 is NROM. VIII. The non-volatile memory 98680.doc -2- 1272487 wherein the non-volatile memory 1 1 is a memory card as claimed in any one of claims 1 to 4. The method of any one of claims 1 to 4, wherein the non-volatile memory has a plurality of memory cells each capable of storing one bit of data. Ϊ́3·= The method of any one of clauses 1 to 4, wherein the non-volatile memory VIII has a plurality of memory cells each of which stores data of _bit or more. 14. A non-volatile memory comprising: - a memory organized into a plurality of blocks, each block being a plurality of memory cells that can be erased, each memory cell system being used (4) Store the data of the logical unit, and each block is used to set the logical group of the logical single to the number of pages, and each relay page is a memory in each plane. The controller is configured to control the operations of the blocks; the controller stores the first version of the data of the logical unit in the plurality of memory units of the -th block according to the first order Each first version of the logical unit is stored in one of the memory planes; and the controller stores the subsequent version of the logical list in a second block in a second order different from the first order Each subsequent version is stored in the next available memory bank m in the same memory plane as the first version so that all versions of a logical unit can be accessed from the same plane. 15. In the non-volatile memory of claim 14, the controller is in a subsequent version of the storage logic unit = simultaneously using the current version of the logical unit in accordance with the order of the brothers to relay the pages one by one 98680.doc 1272487 to fill any unused memory unit logic unit located in front of the next available memory unit; and wherein the next available memory unit has and the first version in its relay page The displacement is the same displacement. Wherein the non-volatile memory, wherein the non-volatile memory, wherein the non-volatile memory, such as the non-volatile memory of the claim 14, has a plurality of floating gate memories Unit 17· The non-volatile memory of claim 14 is a flash EEPROM. 1 8. For the non-volatile memory system NROM of item 14. 19. The non-volatile memory of claim 14 is a memory card. The non-volatile memory of any one of claims 14 to 19, wherein the volatile memory has a plurality of memory cells each of which stores the bit data. As requested in Item 14 to , 丨思遐, in the middle of || Volatile memory has the ability to store more than one yuan each: Recalling unit. 22. A non-volatile memory comprising: a memory organized into a plurality of blocks, each block being a plurality of memory cells that can be erased, each memory cell system Used for: storage-logical unit data, and each block is used to store the logical group of logical units in a plurality of relay pages, each of which is in each plane A memory page is constructed, ·, 98680.doc 1272487 storage component, stored in the first-two-order, in the memory unit of each m-th block of the logical unit data , the center and the version logic unit are stored in one of the storage units of the memory plane, and the slice 877 is logically listed in the first order of the order: the stored version of the later version is stored. And in the first version of the second block, among the next available memory cells of the parent = the next in the same memory plane so that all of the logical units can be accessed from the same plane. version. 23. The non-volatile memory of claim 22, further comprising: 乂 1 彳 彳 彳 彳 彳 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照Any unused memory unit memory soap memory cell logic unit in front of the memory unit; and wherein the next available memory unit has the first version in its relay page Displace the same displacement. 98680.doc