TWI287840B - Self-aligned trench power metal oxide semiconductor field effect transistor device and its manufacturing method - Google Patents

Abstract

The present invention is related to a kind of self-aligned trench power metal oxide semiconductor field effect transistor (MOSFET) device that contains a drain, an epitaxial layer, a trap layer, a source contact region, and two trench gates. The invented device is featured with having a plug. The trench gate is used as the mask and the photolithographic etching technique is used to etch part of the source contact region till the upper portion of the trap layer. By using the self-aligned manner, ion implantation is conducted onto the plug till the inside of the plug, so as to form the plug that is not located on the same level as the source contact region.

Description

1287840

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench-type power metal oxygen having a reduced on-resistance value and having a capability of reducing reverse-current leakage-snap and increasing avalanche breakdown current capability. a half-field effect transistor (Trench p〇wer MOSFET) device, a method of manufacturing the same, and more particularly, a power double-channel channel gate MOS field-effect transistor device with excellent quality and high reliability Reduce the on-resistance value and increase the avalanche collapse current. (ii) Prior art

Generally, in order to obtain a low on-resistance value (R_), a power MOS field-effect transistor (hereinafter referred to as a power MOSFET) device is mostly a trench-type process, especially for channel resistance (Rch), epitaxial. The layer resistance value (Repi) and the junction resistance value (heart) are reduced to obtain a lower on-resistance value. A double-ditch gate design is often used. However, the trench-type power Μ 0 SFET device often encounters the problem that the lateral clamping of the oxide implant on the sidewall of the trench cannot be precisely controlled, thus causing the oxide implant unevenness or even the lack of emulsion on the sidewall of the trench. A short circuit or a large amount of leakage current occurs. As in the conventional trench type M〇SFET device shown in Fig. 1, the corner portion at the bottom of the trench has a right-angled portion because the volume of 矽(si) converted to the dioxide (S i 〇2 ) is increased. The oxide formation is thinner resulting in an increase in high electric field density, thereby reducing the reliability of the MOSFET device.

Jongdae Kim et al., December 2004, IEEE ELECTRON DEVICE LETTER, Vol. 22, No. 12, discloses a high-reliability trench DM0SFET (A Highly using self-alignment technology and hydrogen annealing).

1287840 V. Description of invention (2)

Reliable Trench DMOSFET Employing Self-Align

Technique and Hygrogen Annealing)', which describes the use of heart annealing to round the bottom of the trench to overcome the above problem, as shown in <symbol A in Figure 2. However, although the device can self-align technology to reduce the process steps and use rounded corners to achieve leakage current improvement, the current in the stray layer is still concentrated directly below the double gate, so that the current channel below the well layer Narrow and uneven 'induction resistance values cannot be further reduced, especially in preventing reverse leakage current surges and avalanche collapse. Moreover, in the conventional power MOSFET device (taking N-channel as an example, not shown), in order to reduce the on-resistance value (RD_), a high-concentration doped P+ plug is often added in the source contact region (p 1 Ug ) to reduce the contact resistance (匕), but since the P+ plug is at the same level as the source N+ doped region, the reverse leakage current flows from the N-plated layer when the reverse leakage current is generated. The p-well and P+ are plugged to the source, and a voltage drop occurs between the P_well and the P+ plug. When the voltage drop is greater than 0.6 volts, the PN parasitic diode is turned on to generate a large amount of reverse leakage current, resulting in a large amount of reverse leakage current. A phenomenon in which the reverse leakage current rapidly changes, and the large amount of leakage current is generally concentrated at the interface between the P well and the N- epitaxial layer, causing a current of avalanche collapse, causing a high temperature at the interface, and the power MOSFET device is damaged. . Therefore, it is necessary to design a trench-type power MOSFET device that can be fabricated by self-alignment technology to reduce production steps, and must have a trench-type power MOSFET device that reduces reverse leakage current transients and improves avalanche collapse current capability. So that the quality and reliability of the device can be greatly improved', and the device can be adapted to various transient power supply voltages on the circuit.

Page 7 V. Changes in the invention (3). (II) SUMMARY OF THE INVENTION In order to solve the above-mentioned conventional problems, the ditch-type power MOS field-effect transistor device of the present invention has a resistance to sudden change of reverse leakage current in addition to having a resistance to snow 耑^ Increase the ability of 7 friends to break the current. I am in the ίίίΐ = ϊ: according to the present invention - providing a kind of self-汲 沟 ί 式-type emulsion half-field effect transistor device, the device comprises: Formation: ΐ:: 子: planted with a first-conductivity type of heavy doping The conductive type micro-::.f of the sundries of the sundries is longer than the top of the ruthenium substrate. The ion-implanted first---------------------------------------------------- Conductive type micro-pushing impurity ion cloth, doped I-Z source contact region, growing in the well layer trench type = : = type heavy dopant formed; and two £, the card layer, until Among the worm layers, the polar contact J forms oxides and the polycrystalline strontium is deposited in the trenches on the side of the ^2:---the plug contacts the source contact regions of the trenches to the well An upper portion of the layer, and a second conductive type heavy doping method in which ions are implanted on the upper portion of the layer of the etched portion, wherein the well is in the etched portion of the source contact region until the formation of the dam and the The plug and the source contact region are not in the same level of the well layer, and the ground is in accordance with one of the present invention. Rate 2:-Opinion, method, including the following steps···································································· Crystallizing an epitaxial layer on the germanium substrate to form a conductive micro-dopant; 3. forming a source contact region on the well layer, the source phase implanting a first conductive heavy dopant; And 4: reactively etching the lithography layer layer by using a lithography technique to form a sidewall of the two trench trenches to form oxides in the epitaxial layer and forming oxidation in sidewalls of the trenches in the trenches And forming a gate in the polycrystals, wherein one of the plugs is connected to the source mask by etching the portion of the source contact region, and a second conductive portion is formed on the upper portion of the well layer by self-alignment A type of heavily doped material is formed directly under the source contact region until the well layer, and the plug and the source contact region are not at the same level. (4) Embodiments As shown in Figs. 3a to 3g, a description will be given of an N-channel type as an example of the embodiment of the self-powered MOS field-effect transistor device according to the present invention, and the same components are illustrated. The same components. However, the present invention is not limited to the scope of the invention, and various equivalent changes and modifications are possible within the scope of the invention. 7 as shown in Fig. 3a, providing a first conductivity type germanium substrate as the ion implantation: contact region ion contact region, the channel, and deposition in the deposited polycrystalline shi gully The upper part of the layer of the orange layer is the part of the ion implant and the step of the plug is aligned with the ditch. The symbol will represent that 'Yu Fan Yi Ben' should be regarded as heavily doped Shi Xi 1287840. V. Description of invention (5)

The substrate 1 is used as a drain of the power MOSFET device, and a lower surface thereof can be plated with a conductive metal as a drain contact (not shown). First, the substrate 1 is grown on the substrate 1 a dope layer 2, then ion implanting a first conductivity type microdopant to form an N-plated layer 2. Then, a well layer 3 is grown on the N- twin layer, the well layer 3 The ion implants a second conductivity type micro-dopant (P-); in FIG. 3b, a source contact region 4 is shown, which grows on the solution layer 3 and the ion implants have a first conductivity Type heavy dopant (N+); then, in Figure 3c, the source contact region 4, the well layer 3 is etched by lithography using a photomask until the epitaxial layer 2 is Forming two trenches; then, in Figure 3d, removing the photoresist coated in the lithography technique, redepositing the gate oxide (such as dioxide dioxide) on the sidewalls of the trenches Insulating spacers are formed, and then polysilicon is deposited in the trenches to form gates 5. ^

Next, in Fig. 3e, a screening (boron-filled bismuth telluride glass) insulator is deposited over the gate 5, and a photoresist (pR) is applied there to etch the two gates using a lithography technique. Part of the source contact area 4 to the upper part of the taste layer 3' then removes the photoresist (PR); in Figure 3f, the gates are used as a mask, and the ion implantation is performed by self-alignment. a second conductive type heavily doped material is directly under the etched portion of the source contact region up to/within the well layer 3 to form a P+ plug 6, wherein the P+ plug 6 is in contact with the N+ source The level of zone 4 is different; then in the 3g diagram, a source metal 7 such as aluminum (A1) is plated over the device to form a source contact that contacts the P+ plug 6. As described above, according to the viewpoint of the present invention, the p+ plug is implanted in the N+ source contact region 4', and the source contact resistance value (Rc) can be effectively reduced to

Page 10 1287840 V. INSTRUCTION DESCRIPTION (6) 'The on-resistance value (Rdson) is lowered, and since the P + plug 6 is different from the level of the N+ source contact region 4 and the plug 6 is deep into the well layer 3 Therefore, it is difficult to cause the parasitic layer 3 and the parasitic diode between the plug 6 and the source contact region 4 to be turned on, so that the reverse leakage current can be prevented from rapidly changing, and since the plug 6 penetrates into the well layer 3, The on-resistance RDS0N is made smaller to increase the avalanche breakdown voltage. Although the above description is described in terms of an N-channel power M〇SFET device, the present invention is also applicable to a p-channel power M〇SFET device in which only p, N, and n are changed to p; It will be understood by those skilled in the art that the present invention is not limited to the above description, but may allow various modifications and modifications, among which different process methods and ion implantation techniques result in the same structure as the device. The method is within the scope of the invention, however, this month: the equivalent meaning and scope of the patent application scope of the appendix. "

1287840 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a schematic diagram of a conventional trench-type power MOSFET device; FIG. 2 is a schematic view showing a schematic diagram of a conventional dual-gate trench-type power MOSFET device; And a schematic diagram of Figures 3a through 3g depicting the process steps of a power MOSFET device in accordance with the present invention. Main representative component symbol description

1 substrate C corner 2 worm layer A rounded corner 3 well layer 4 source contact area 5 gate 6 plug 7 source PR photoresist BPSG borophosphonate glass

Page 12

Claims (1)

1287840 VI. Patent Application Scope 1. A self-aligned trench power all 4 includes: - immersed, formed by a transistor device, the mounted substrate; an epitaxial sound, a conductive heavy dopant: The first conductive type micro-dopant is implanted on the second layer; the second conductive material grows on the second crystal layer, and grows in the well sound of the Pu Puchun ρ xiangxiang 'one source contact well layer On the top, the hunting ion implants the first guide to create a tongue for the replacement of the object; and the two ditch-type between the four hybrid anti-depositive etched source; & hammer Ρ pole, with reticle using lithography夂 f 生 蚀刻 a a source contact area, the well layer, and formed, and in the gully of the gamma gentleman, " Μ day θ ^ ^ ^, and then the sidewall of the formation of oxide And depositing the cerium in the trenches, wherein the device is characterized by a plug, which is a photomask, and is contacted by the source of the etched portion; L is in a manner of 2 alignment, in the layer Upper portion: =: conductive heavy dopant' to form the plug in the second pole total HJ: and the plug and the source The contact area is not at the same level. 2: A method for self-aligning a trench-type power MOS field-effect transistor device, comprising the steps of: a. providing an ion-plated first-conducting type heavily doped germanium substrate as a drain; b·lei Forming an epitaxial layer on the germanium substrate and ion-conducting micro-extrusion; c. forming a well layer on the doped layer, the well layer ion-electric micro-dopant; d Forming a source contact region on the well layer, the source contact region ion 1287840 Depositing a first conductivity type heavy dopant; and e. reactively etching the source contact region and the well layer by a lithography technique using a photomask to form two trenches in the epitaxial layer, in the trenches Forming oxides on the sidewalls and depositing polysilicon in the trenches to form a gate, wherein a plug is substantially covered by the trench gate gate, and the source contact region of the portion is engraved to the upper portion of the well layer, and the self is utilized. Aligning the gas on the upper portion of the well layer, ion implanting the second conductive type heavy dopant, and ^ ^ is directly under the source contact region of the etched portion, and r is 1 to the well Within the layer And wherein the plug is not in the same contact area as the source _ ^