TW200411780A - Self-aligned trench power metal oxide semiconductor field effect transistor device and its manufacturing method - Google Patents

Abstract

The present invention is related to a kind of self-aligned trench power metal oxide semiconductor field effect transistor (MOSFET) device that contains a drain, an epitaxial layer, a trap layer, a source contact region, and two trench gates. The invented device is featured with having a plug. The trench gate is used as the mask and the photolithographic etching technique is used to etch part of the source contact region till the upper portion of the trap layer. By using the self-aligned manner, ion implantation is conducted onto the plug till the inside of the plug, so as to form the plug that is not located on the same level as the source contact region.

Description

200411780 V. Description of the invention α) (1) The technical field to which the invention belongs The present invention relates to a method having a reduced on-resistance value, a reduction in reverse leakage current (snap-back), and an increase in avalanche breakdown current Capable trench-type power metal-oxide-semiconductor field-effect transistor (Trench p0wer M0SFET) device and method of manufacturing the same, and more specifically, 'power metal-oxide-semiconductor half-field-effect transistor device with double trench-type gates' which has excellent quality and High reliability, which can reduce the on-resistance value and increase the avalanche breakdown current. (II) Prior technology

In general, power metal-oxide-semiconductor field-effect transistor (hereinafter referred to as power M0SFET) devices in order to obtain a low on-resistance value (RdsOn), are mostly manufactured by trench technology, especially to make the channel resistance value (L), The epitaxial layer resistance (Repi) and junction resistance (&) are reduced to obtain a lower on-resistance value. 'Double trench gate design is often used. However, trench type power M 0 SFET devices often encounter the problem that the lateral position of oxide implantation on the sidewall of the trench cannot be accurately controlled, resulting in uneven oxide implantation, and often due to lack of oxide on the trench sidewall. Short circuit or large leakage current. As shown in Fig. 1, in the conventional trench-type MOSFET device, the corner portion that is at a right angle at the bottom of the trench is converted to silicon dioxide (Si0) by the second (§ 丨), and the volume of the oxide is formed there. Thinner leads to an increase in high electric field density, thereby reducing the reliability of the MOSFET device.

In the December 2001 issue of Jongdae Kim et al., IEEE ELECTRON DEVICE LETTER, Vol. 22, No. 12, disclosed a "high-reliability trench DM0SFET (A Highly) using self-alignment technology and hydrogen annealing"

200411780

Reliable Trench DMOSFET Employing Self-Align

Technique and Hygrogen Annealing), in which the escape gas is annealed to round the bottom of the ditch to overcome the above problems, as described in [2]. It is shown by 氲 symbol A. However, although the device can reduce self-alignment technology to reduce the intermediate step and use the corners to improve the leakage current, the epitaxial layer < medium step flow is still concentrated directly under the double gate, making the card layer The electricity below 3 and 2 $ are not uniform, so the on-resistance value cannot be further reduced, especially there is no improvement in the sudden change of leakage current in ^ ^ direction and avalanche collapse. In addition, in the conventional power MOSFET device (taking N channel as an example, not shown), in order to reduce the on-resistance value (Rd_), the source contact is often increased by a concentration of doped P + plug (p 1 ug) to reduce the contact resistance (r), but because the P + plug system is at the same level as the source N + doped region, the reverse leakage current flows through the N- epitaxial layer when the reverse leakage current is generated. The well and P + are plugged to the source, and a voltage drop occurs between the p-well and p + plug. When this voltage drop is greater than 0.6 volts, the PN parasitic diode is turned on and a large amount of reverse leakage current is generated, so that The phenomenon of rapid reverse leakage current occurs, and the large amount of leakage current is generally concentrated at the interface between the p-well and the N-epitaxial layer, causing avalanche breakdown current, causing high temperature at the interface, and damaging the power MOSFET device. . Therefore, it is necessary to design a trench power MOSFET device. In addition to being able to use self-aligned technology to reduce production steps, it must also have trench power to reduce reverse leakage current surges and improve avalanche breakdown current capability. M0SFET device, so that the quality and reliability of Pei Zhi can be greatly improved, and then the device can adapt to various transient power supply voltage instability on the circuit

5. Description of Invention (3) Changes. (3) Contents of the invention: White pain: In order to solve the above-mentioned conventional problems, the purpose of the present invention is a low-conductance, power-supply metal-oxygen half-field-effect transistor device, which has the capability of resisting snow currents. Electricity: To achieve the above purpose, according to one aspect of the present invention, a groove: a type of power metal-oxygen half field effect electricity] body package; the formation of the second-conductance type heavy junction: conductive type Above the micro, ionic cloth 3; = micro-dopants;-source contact area, growing trench gate, formed by = two-type heavy dopants; wall shaped in the worm crystal layer and ⑥, Among these features are-detecting and depositing polycrystalline dreams in the ditch, where the source electrode ^ spreads the earth with the ditch gate mask, and a second conductive type is re-doped by etching == ^, The σ 卩 of the etching is directly below the source contact area 1 and: the plug and the source contact area are not at the same level: Access: Γί 'According to the present invention-viewpoint, another method of the present invention includes the following The step-type power golden-half field-effect transistor is in addition to a kind of self-contained. In addition to the change and increase, a self-contained device is included: a silicon substrate is planted first, and ions are distributed on the side of the device and two sources contacting the trench. Part of the engraving, within the well forming the plug layer, a viewpoint, the manufacturer 200411780

A conductive heavily doped silicon substrate

Provide an ion implantation with a first drain; 2 epitaxially grow an epitaxial layer on the silicon substrate with a conductive micro-dopant; 3 • form a source contact region on the delaminated layer and implant the first A conductive heavy dopant; and ion-implanted the source contact region ions 4. reactively etch the lithographic contact region and the well layer with a reticle using lithography technology until the epitaxial layer Two (four J channels ... form oxides and deposit in these trenches to form oxides on the side walls of these trenches and deposit gates in these trenches, of which-plugs are based on these trenches The photogate is a photomask, and the source contact area of the etching part to the upper part of the well layer is self-aligned on the upper part of the well layer, and the first V-type heavy dopant is ion-implanted to form The etched portion is directly below the source contact area up to the inside of the well layer, and wherein the plug and the source contact area are not at the same level. The embodiment is as shown in Figures 3a to 3g. In the half field effect transistor, the N-channel type is used as an example for the same device. However, the present invention explains The content completed is included within the scope of the present invention, and depicts the process steps of one embodiment of the self-aligning trench body device according to the present invention, which is illustrated, and the same component symbols will indicate that it is not limited to this embodiment. Various equivalent changes and amendments according to this book should be regarded as providing a N + first conductive type heavily doped stone as shown in Figure 3a. 200411780 V. Description of the invention (5) Substrate 1, the silicon substrate 1 As the drain of the power MOSFET device, a conductive metal can be plated on the lower surface as a drain contact (not shown). First, an epitaxial layer 2 is epitaxially grown on the substrate 1, and then, An N- epitaxial layer 2 is formed by ion implantation of a first conductivity type micro-dopant, and then a well layer 3 is grown on the N_ epitaxial layer. The well layer 3 is ion implanted by a second conductivity type. Micro-dopants (P-); in Figure 3b, a source contact region 4 is shown, which is grown on the well layer 3 and ion implanted with a first conductivity type heavy dopant (N +); Then, in FIG. 3c, a source mask is used to etch the source contact region 4, the Two wells are formed as shown in the well layer 3 until the epitaxial layer 2 is formed. Then, in FIG. 3D, the photoresist applied in the lithography technique is removed, and then a gate oxide is deposited ( (Such as silicon dioxide) to form insulating spacers on the sidewalls of these trenches, and then deposit polycrystalline silicon on the trenches to form gate 5. # In Figure 3e, deposit BPSG (delete phosphorus ^) on the gate 5 ^)) An insulator, and apply a photoresistor (PR) there, and use the micro-J technology to contact the source contact region 4 to the card layer ^: light Γ = resistance (PR); in the first In the 3f picture, a second conductivity type heavy doping is ion-implanted with the idler 5 when I align, and a p + plug is formed below 6 m until the level within the card layer 3 is different; ;, JJ6 and this: square = contact area 4 The source of aluminum (A1) is plated on the device with a source contact such as the above Γ Greek if formed to contact the 134 plug 6. From the point of view of the P + anchor X x Ming, a plug in 4 of the N + source contact area can effectively reduce the source contact resistance (Rc) and make 200411780

V. Description of the invention (6) The on-resistance value (Rdson) is reduced, and because the level of the P + plug 6 and the N + source contact region 4 is different and the plug 6 penetrates into the flavor layer 3, it is not easy to be far away. The continuity of the parasitic diodes between the patch layer 3, the plug 6 and the source contact region 4 can prevent the reverse leakage current from changing sharply, and because the plug 6 penetrates into the _ layer 3, the on-resistance RDS0N Becomes smaller while boosting avalanche crashes.

Although the above description is described with an N-channel power MOSFET device, the present invention can also be applied to a P-channel power MOSFET device, where only P must be changed to N 'and N to p; Those skilled in the art will understand that the present invention is not limited to the above description, but can allow various modifications and changes. Among them, different process methods and ion implantation techniques lead to methods that are compatible with the device structure of the present invention. Within the scope of the present invention, however, the present invention will be added with the equivalent meaning and scope of the appended patent application scope.

200411780 Brief description of the drawings The first diagram is a schematic diagram depicting the structure of a trench power M0SFET device of the conventional technology; the second diagram is a schematic diagram depicting the structure of a dual gate trench power M0SFET device of the conventional technology; And Figures 3a to 3g are schematic diagrams depicting process steps of a power MOSFET device according to the present invention. Symbols of the main components

C A Corner Fillet

Page 12

Claims (1)

200411780 VI. The scope of the patent application is L Fan, ^ I aim at the trench power metal-oxygen half field effect transistor device. The mounting plate: ΞΪ: by: Ϊ 子 is planted with the first conductive heavy dopant Yangde Ergu. V forms a ray layer, grows on the silicon substrate, and separates a conductive micro-dopant; a card layer, grows on the stupid crystal, and is implanted with a second conductive micro-dopant;-source contact : And = on the layer, the first conductive type doped and two trench-type interpoles are implanted by ion implantation, and the source contact area and the patch layer are etched by the photolithographic reaction using a photomask until the insect An oxide is formed on the sidewalls of the trenches in the crystal layer, and the device is characterized by a plug in the trenches. The trench gates are photomasks, and the source contact area of the etched part is used to the well and Using a self-alignment method, a first conductive heavy dopant is ion-implanted on the upper part of the samarium layer to form the plug in the etched ==; square side layer, and the plug and the: pole The contact areas are not at the same level. 2. A method for manufacturing a self-aligned trench-type metal-oxide-semiconductor field-effect transistor device, including the following steps: a. Providing a heavily doped silicon substrate ion-implanted as a drain; b. A crystal epitaxial layer is grown on the silicon substrate and a first conductive micro-dopant is implanted on the silicon substrate; c. A well layer is formed on the epitaxial layer, and the ion-type micro-dopant on the well layer is formed. Ψ d. Forming a source contact region on the well layer, the source contact region ions page 13 200411780 6. Application of patents for the implantation of the first conductive heavy dopant; Shadow technology reactively etches the source contact area, the fat layer 'up to the epitaxial layer to form two trenches, forms oxides on the sidewalls of the trenches, and deposits polycrystalline silicon in the trenches to form gates, One of the plugs is a photomask with these trench gates, and the second conductive type is ion-implanted on the upper part of the well layer by using the source contact area of the etched part to the upper part of the well layer. Dopant, and formed directly under the etched portion of the source contact area until the sound of the well, and wherein the plug and the source contact area are not at the same level: