TWI287709B - Method and apparatus for virtual direct memory access - Google Patents

Method and apparatus for virtual direct memory access Download PDF

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Publication number
TWI287709B
TWI287709B TW092104203A TW92104203A TWI287709B TW I287709 B TWI287709 B TW I287709B TW 092104203 A TW092104203 A TW 092104203A TW 92104203 A TW92104203 A TW 92104203A TW I287709 B TWI287709 B TW I287709B
Authority
TW
Taiwan
Prior art keywords
processor
callback function
interrupt
direct memory
memory access
Prior art date
Application number
TW092104203A
Other languages
English (en)
Chinese (zh)
Other versions
TW200400437A (en
Inventor
Jean Casteres
Frederic Risacher
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200400437A publication Critical patent/TW200400437A/zh
Application granted granted Critical
Publication of TWI287709B publication Critical patent/TWI287709B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Telephone Function (AREA)
TW092104203A 2002-03-01 2003-02-27 Method and apparatus for virtual direct memory access TWI287709B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02290502A EP1341092A1 (en) 2002-03-01 2002-03-01 Method and arrangement for virtual direct memory access

Publications (2)

Publication Number Publication Date
TW200400437A TW200400437A (en) 2004-01-01
TWI287709B true TWI287709B (en) 2007-10-01

Family

ID=27675778

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092104203A TWI287709B (en) 2002-03-01 2003-02-27 Method and apparatus for virtual direct memory access

Country Status (7)

Country Link
EP (1) EP1341092A1 (https=)
JP (1) JP2005519393A (https=)
KR (1) KR20040101260A (https=)
CN (1) CN100367255C (https=)
AU (1) AU2003218666A1 (https=)
TW (1) TWI287709B (https=)
WO (1) WO2003075167A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100891508B1 (ko) 2007-03-16 2009-04-06 삼성전자주식회사 가상 디엠에이를 포함하는 시스템
CN101303651B (zh) * 2007-05-10 2011-08-24 联芯科技有限公司 业务处理方法及采用该方法的用户设备
CN101937407B (zh) * 2009-06-30 2012-09-05 联想(北京)有限公司 一种被动硬件设备访问装置及方法
CN107193767B (zh) * 2017-05-25 2020-05-19 北京计算机技术及应用研究所 一种双控制器存储系统缓存镜像的数据传输系统
US12162146B2 (en) 2020-01-20 2024-12-10 Siemens Industry Software Ltd. Method and system for facilitating a concurrent simulation of multiple robotic tasks

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475860A (en) * 1992-06-15 1995-12-12 Stratus Computer, Inc. Input/output control system and method for direct memory transfer according to location addresses provided by the source unit and destination addresses provided by the destination unit
US5875352A (en) * 1995-11-03 1999-02-23 Sun Microsystems, Inc. Method and apparatus for multiple channel direct memory access control
US6260081B1 (en) * 1998-11-24 2001-07-10 Advanced Micro Devices, Inc. Direct memory access engine for supporting multiple virtual direct memory access channels
US7089344B1 (en) * 2000-06-09 2006-08-08 Motorola, Inc. Integrated processor platform supporting wireless handheld multi-media devices

Also Published As

Publication number Publication date
EP1341092A1 (en) 2003-09-03
TW200400437A (en) 2004-01-01
CN100367255C (zh) 2008-02-06
WO2003075167A1 (en) 2003-09-12
AU2003218666A1 (en) 2003-09-16
CN1647055A (zh) 2005-07-27
JP2005519393A (ja) 2005-06-30
KR20040101260A (ko) 2004-12-02

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