TWI283909B - Bitline process - Google Patents

Abstract

A bitline process. The bitline process comprises the steps of providing a semiconductor substrate with a plurality of transistor formed thereon and sequentially forming an interlayer dielectric layer and a mask layer over the semiconductor substrate. Next, a contact opening is formed in the mask layer and the interlayer dielectric layer. Next, a first sacrificial layer is partly formed in the contact opening and a second sacrificial layer is then formed over the mask layer and also fills the contact opening with a planarized surface thereof. Next, the mask layer and the second sacrificial layer adjacent to the contact opening is the patterned to form a bitline trench for connecting the contact opening. Next, a metal layer is then form in the bitline and the contact opening.

Description

1283909 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor process, and more particularly to a bit line process. [Prior Art] In recent years, with the increase in the degree of integration of integrated circuits, semiconductor process design has also been developed in the direction of reducing the size of semiconductor components to increase density, in order to witness the widely used dynamic random access memory (Dynamic R). And 〇m Access Memory, DRAM) For example, the 64M DRAM process has been converted from 0 · 35 //m to below 0·3 //m, while 128M DRAM or 256M DRAM is more oriented towards 〇. 2 /zm. In the dynamic random access memory system, a stack of boro-phosphosilicate glass (BPSG) and a yttrium oxide layer (hereinafter referred to as TEOS) deposited using tetraethoxysilane (TEOS) is used. The layer is overlaid on the transistor as an inner dielectric layer (ILD). While TE0S/BPSG has good cooking selectivity for polysilicon, it is common to use a polysilicon as a hard mask to etch the TE0S/BPSG insulating layer to form a bit line contact window. Then, a polycrystalline stone plug (P 1 u g ) is filled in the contact line of the bit line, and a bit line is formed from the metal material. However, the polysilicon plug used in the conventional method retains the contact resistance ^(10)·^^ resistance of the metal material even after being electrically doped, due to the characteristics of the dielectric material.

Rc). Therefore, in order to reduce the feature size to the design rule of the DR AM device below 〇·η, especially the deep trench (deep)

0548-A50048TWf(4.5) ; 92176 ; shawn.ptd Page 6 1283909 V. Invention Description (2) _ ΙΓ/Γ11, DT) DRAM device as a storage node, which needs to be used in the contact window Such as the lower resistance of metal materials 'to reduce the contact resistance of the plug. Thus, a bit line process is required to form a bit line structure having a lower contact resistance plug. -# ^ [Summary of the Invention] In view of the fact that the resistive material is inserted into the bit line contact plug and the bit is up to the above-mentioned steps, including: 'The connection between the bit line of the plug of the present invention and the contact plug element line, The main purpose of the present invention is to provide a low-power process that is only by one metal deposition, which simplifies the bit line process and improves the contact resistance. An interconnecting process is provided, the step of providing a semiconductor substrate having a plurality of dielectric layers disposed thereon on a plurality of substrates and an electrical layer covering the plurality of transistors; forming at least one contact between the conductor substrates The window opening is less than the window opening contact window crystal; the cover layer and the wire trench layer are respectively formed in order to make the one bit become one gold; forming a cover and a second sacrifice, wherein the first a second sacrificial; and the lining layer constituting the one-dimensional invention to expose a first sacrificial layer therein, the sac layer having a layer on the sacrificial layer of the mask layer, and a bit line and a Contact plugs and other purposes, specially formed bonding trenches and the epitaxial mask layer and the semiconductor portion of the layer are filled and the contact contact window plug is planarized. The half, wherein the dielectric layer substrate and the contact are filled in the surface; the opening of the opening of the window opening has the advantage of being more 0548-A50048TWf(4.5) 92176 i shawn.ptd page 7 1283909

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The bit line process of the present invention will be described in detail below in conjunction with FIGS. 1 to 4 as follows. Referring to the W, first, a semiconductor substrate (10), such as a germanium substrate, is provided with a transistor 1〇2. An interlevel dielectric layer 104 is then formed over the semiconductor substrate 100 and overlies the transistor 102 of the semiconductor substrate 101. Here, the interlayer dielectric layer 1〇4 may be composed of a single layer of a blank material, for example, a common ceria material, or a BPSG layer sequentially formed on the semiconductor substrate 1 in the prior art ( Stacked insulation consisting of 7) and 3 layers (not shown). Here, each transistor 丨〇2 includes a source terminal 108, a drain electrode 11 〇, and a gate structure 11 2 , respectively. The gate structure 1丨2 includes a gate insulating layer 114, a polysilicon layer 116, a metal telluride layer 118, and a mask layer 120. The gate electrode is composed of a polysilicon layer 6 and a metal germanide layer. 'And it is covered by an insulating material, for example, a nitriding mask layer 120 of the nitrite, a sidewall such as a barrier 丨 2 2 of tantalum nitride, and a source 1 0 8 and a drain 11 〇 Then it is a doped region. A shroud layer 124 is then formed over the interlayer dielectric layer 1 〇 6 . The village layer of the mask layer 124 is, for example, a polycrystalline layer having a thickness of about 6,000 to 990 angstroms. Using a self-aligned contact process, a photoresist layer 126 having a contact opening pattern is formed on the mask layer 124 and then a photoresist mask 126 is used as an etching mask to perform a self-aligned contact process. #刻加工程 (not shown) to facilitate the formation of the mask layer 1 2 4 and the interlayer dielectric layer 1 〇6

1283909 V. DESCRIPTION OF THE INVENTION (4) The contact opening 128 is exposed to expose the semiconductor substrate 10, the drain 10 0 and the adjacent two transistors 1 〇 2 therein. Here, the contact opening 1 28 is illustrated by the bit line in contact (CB) illustrated in FIG. 1, but is not intended to limit the practical application of the process of the present invention. When the transistor feature size in the DRAM design criteria is reduced to about . ii /zm, the opening width of the contact opening 128 as a bit line in contact (CB) is about 〇· ι8 Between ~ 21 μm (am), the lamination depth of the interlayer dielectric layer 1 〇 6 and the mask layer 1 24 is about 5000 to 7000 angstroms, so the contact opening 128 usually has a size of 3:1 or more. Aspect ratio. Referring to Figure 2, a characteristic step of the present invention is shown. After the photoresist layer 126 is removed, a first sacrificial layer 130 is formed in the contact opening. Here, the first sacrificial layer 130 is only partially filled in the contact opening 128, which is a first distance d1 of about 800 to 1500 angstroms from the surface of the mask layer 124. In the present embodiment, the first sacrificial layer 130 is formed by a spin coating method, and the first sacrificial layer 130 is an anti-reflective coating (ARC) including a carbon-containing compound. For example, it is AR3 (manufactured by Shipley Chemical), AR7 (manufactured by Shipley Chemical), and DUV30 (manufactured by Nisson Chemical). In the present embodiment, the anti-reflection layer comprising the carbon-containing polymer constituting the first sacrificial layer 1 3 must have a dynamic viscosity of 1 〇 13 centipoise (cP), so that it can be spin coated. The cloth is only partially filled in the contact window opening 1 28 in a single process step and does not remain on the surface of the mask layer 124, so that it can be omitted to control the partial filling of the contact window opening i 28 . Additional etching step

0548-A50048TWf(4.5)92176 i shawn.ptd Page 9 1283909 V. INSTRUCTIONS (5) : — ---— The rotational speed of the above spin coating method is about 12 〇〇 to 3 〇〇〇 RpM (revolution per minute) ‘preferably 1 50,000 to 2 0 0 RPM (revolution per minute). Referring to Figure 3, another feature step of the present invention is shown, followed by forming a second sacrificial layer 132 over the mask layer 124 and overlying the first sacrificial layer 13 in the contact window 128. Here, the second sacrificial layer 132 has a plane thickness of about 5 〇〇 a 〇 to 600 Å. The method for forming the second sacrificial layer 132 is, for example, a spin coating method, which is formed at a rotation speed of about 1300 to 300 rpm (revolution per minute), and is subjected to spin coating. The second sacrificial layer 132 continues to be filled into the contact opening 128 to cover the previous first sacrificial layer 130, and finally forms a planarized surface on the semiconductor substrate 1A. Here, the sacrificial layer 133 is an anti-reflective coating (ARC) including a carbon-containing polymer, for example, AR3 (manufactured by ShiWe Chemical), AR7 (manufactured by Shiple Chemical), and Y DUV30 (Nisson). Chemical manufacturing). In this embodiment, the anti-reflection layer comprising the carbon-containing polymer constituting the second sacrificial layer 32 has a dynamic viscosity of 7 to 1 centipoise (cp), so that the spin coating method can be used. The filling is continued in the contact opening 丨 2s, thereby being flatly covered on the mask layer 124. Here, the first sacrificial layer 130 and the second sacrificial layer ι32 may be formed in situ by a single spin coating machine (not shown), which has the advantage of simplifying the process steps. Referring to FIG. 4, a subsequent bit line lithography/etching process (not shown) is used to form a bit line trench connecting the bit line opening 1 28 to the previous mask layer 124 (not shown). a groove (not shown), thereby exposing the interlayer between them

1283909 V. Description of invention (6) Electrical layer 1 0 6. Here, the second sacrificial layer i 3 2 also exhibits an appropriate etch stop in the process:: free: shadow / surname _ and the first - sacrificial foot over-synchronization = avoiding the interlayer dielectric layer after the removal contact The residual in the window opening 128 and the first sacrificial layer i 3 0 'and then the sacrificial layer in the contact window opening i 2 8: a barrier layer 134 and a metal layer 136 are sequentially formed on the electrical layer 1〇6. . "The 兀 line trench and the contact opening 128 leave a metal layer 136 and a barrier layer 134 as a bitline and a bit contact plug (1) (1) μ曰 contact plug. Here, the barrier layer 134 The material can be; the degree of dryness is 5"2. The material of the metal layer 136 is as follows: :/, genus, which effectively improves the contact resistance of the bit line contact plug. The advantage of the present invention is that (1): by the application of two spin coating processes to form a preferred surface flattening layer 130' in the contact opening/into the sacrificial layer 124, and because of the present invention Both sacrificial layers are: dry, s material, with improved lithography effect of subsequent bit line lithography process, = suitable for flattening contact window openings with a depth ratio of more than 3:1 and lithography source wavelength of 193 nm The bit line lithography process below m (ηπ)) is described by (j L is formed on the mask layer 1 2 & the second sacrificial layer provides a partial etch stop effect to improve etching in the subsequent etching process The effect, so as to avoid the bit line lithography/etching process as shown in Fig. 5, due to the etch Engraving stop ^ Deformation of the contact window opening caused by the inconsistency between the contact window opening and the corner line 138 of the bit line intersection.

1283909

(3) The bit line process of the present invention can avoid an undesired situation such as a step of the bit line difference of 1 0 0 due to the formation of a subsequent metal layer such that the metal layer formed at the opening of the contact window is recessed. In this way, the short circuit between adjacent contact plugs can be avoided and the overall film flatness can be improved, which is beneficial to the subsequent film layer and its lithography/synthesis process. (4) Comparing with the interlayer, the foregoing process can be mentioned, although the two sacrificial layer material electrical layers 106 and the mask layer 124 used in the process of the present invention are limited. There is a great etch S to choose the opportunity of easy i: = :(:W〇rk) by general ashing or wet etching and to remedy process loss and product loss by redoing at the appropriate time.本^ The present invention has been disclosed in the preferred embodiments as above, and it is to be understood that any skilled person skilled in the art will not be dismissed; the invention:::, when various modifications and turbations can be made '; therefore:; The definition is final. Beta protection

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4 is a series of cross-sectional views for explaining a bit line process according to a preferred embodiment of the present invention; FIG. 5 is a cross-sectional view for explaining a profile deformation of a contact window opening and a bit The bit line structure of the height difference of the step line of the element line. [Description] 100~ semiconductor substrate; 1 0 2~ transistor; 1 0 6~ interlayer dielectric layer; I 0 8~ source; II 0~ drain; 11 2~ gate structure; 11 4~ gate Insulating layer; 11 6~ polycrystalline germanium layer; 11 8~ metal germanide layer; 120, 124~ mask layer; 1 2 2~ spacer; 1 2 6~ photoresist layer; 1 2 8~ contact window opening; 130~ a first sacrificial layer; 13 2 to a second sacrificial layer; 1 3 4 to a barrier layer; 1 3 6 to a metal layer; 138 to a corner;

0548-A50048TWf(4.5) ; 92176 ; shawn.ptd Page 13 1283909 Schematic description of the 1 4 0~ step height difference; dl ~ the distance of the first sacrificial layer from the surface of the mask layer. Page 14 0548-A50048TWf (4.5); 92176 ; shawn.ptd

Claims (1)

1283909 Sixth, the scope of application for patents 1 · A bit line process, including the following steps: Provide a semiconductor substrate on which a plurality of transistors are disposed; Forming on the semiconductor substrate sequentially, an interlayer dielectric layer and a mask layer, wherein the interlayer dielectric layer covers the plurality of transistors; and at least one contact window opening is formed in the mask layer and the interlayer dielectric layer, And exposing one of the semiconductor substrate and the germanium transistor; forming a first sacrificial layer, partially filling the contact window opening; covering a second sacrificial layer on the mask layer and filling in the Within the contact window opening, wherein the second sacrificial layer has/planarized surface; Defining the mask layer and a portion of the second sacrificial layer ' to form a bit line trench connecting the contact window opening; and forming a metal layer in the bit line trench and the contact window opening to form a A bit line and a contact plug. 2. The bit line process of claim 1, wherein the contact opening is 7000 angstroms from the semiconductor substrate. 3. The bit line process as described in claim 1, wherein the sacrificial layer is 8 qq to 丨500 Å from the surface of the mask layer. 4 · The bit line process as described in item 1 of the scope of the patent application, wherein The first sacrificial layer and the second sacrificial layer are formed in the spin coater and are sequentially formed. [5] The bit line process as described in claim 1, wherein the method of forming the first sacrificial layer is a spin coating method, and the forming speed is between 1 20 0 and 300 rpm. minute. 6 · The bit line process as described in item j of the patent scope, wherein Page 15 1283909 VI. Scope of Application The first sacrificial layer is an anti-reflective layer comprising a carbon-containing polymer. Signature _ 7 · The bit line process as described in claim 6 of the claim, wherein the sacrificial layer has a dynamic viscosity of 10 to 13 centipoise (cP). (8) The bit line process as described in claim 1 of the scope of the patent application, wherein the curtain layer is only partially filled in the opening of each contact window without leaving any residue in the cover. The bit line process described in the first item, wherein the method of forming the sacrificial layer of U 1 ω η η is a spin coating method, and the forming speed is between “00~3 0 0 rpm/min. 1 0 · The bit line process described in claim 1, wherein the sacrificial layer is an anti-reflection layer comprising a carbon-containing polymer. 兮Μ 11 : a bit line process as described in claim 10 Wherein the sacrificial layer has a dynamic viscosity of between 7 and 10 centipoise (CP). Contact: a bit line process as described in claim 1 of the patent application, wherein the aspect ratio of the contact* opening More than 3:1. All belong to the bit line process described in item 1 of the second patent scope, wherein the i-genus layer is a crane metal layer. The bit line process, wherein the contact interposer is a tungsten metal contact plug. The bit line process described in the first item of the L2 The step of forming a barrier is wider than the trench of the bit line and the opening of each contact window. 16. The bit line process of claim 5, wherein the barrier layer is titanium nitride. Floor. 0548-A50048TWf(4.5) ; 92176 ; shawn.ptd Page 16