TWI281219B - Connecting module with passive components and manufacturing process thereof - Google Patents

Connecting module with passive components and manufacturing process thereof Download PDF

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Publication number
TWI281219B
TWI281219B TW095101211A TW95101211A TWI281219B TW I281219 B TWI281219 B TW I281219B TW 095101211 A TW095101211 A TW 095101211A TW 95101211 A TW95101211 A TW 95101211A TW I281219 B TWI281219 B TW I281219B
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Taiwan
Prior art keywords
layout
connection
module
wafer
connection line
Prior art date
Application number
TW095101211A
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English (en)
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TW200727377A (en
Inventor
Yuan-Chin Hsu
Chen-Hsiung Yang
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Touch Micro System Tech
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Application filed by Touch Micro System Tech filed Critical Touch Micro System Tech
Priority to TW095101211A priority Critical patent/TWI281219B/zh
Priority to US11/434,733 priority patent/US20070158829A1/en
Application granted granted Critical
Publication of TWI281219B publication Critical patent/TWI281219B/zh
Publication of TW200727377A publication Critical patent/TW200727377A/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

^281219 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種多晶片栽板 接模組製造方法及i社構，尤於封衣（Package)以及連 將利用曰PI /、、、， 尤心―種整合被動元件製程並 析利用晶囫基板空間置入晶片， 其結構。 Μ卩牛低封聚難度的方法及 【先前技術】 市二 短、小及高功能發展，封裝
訊產品朝高頻化、㉟1/0數及小型化的 ，進。隨著IC製程技術的進步，Ic内部的元件越做 越士，資料處理的速度越來越快’所需的頻率越來越高， 且貪料對外溝通的需求也越來越大，也就是IC的接腳需求 越來越多’於是能提供高腳位、高頻的載板封裝漸成主流。 目前載板封裝又可依晶片的多寡分為單一晶片與多晶
片封裝二種，單一晶片封裝主要有球狀閘陣列封裝（Bal 1 Gi^dArray; BGA)、覆晶封裝（FUpChip; %)、晶片尺寸 封 I (Chip Scale Package ; CSP)、陣列腳位排列封裝（pin Grid Array Package ; PGA)、柱栅陣列封裝（c〇lumn Grid Array; CGA)等，而多晶片封裝則是以堆疊式封裝（stack IC
Package)、多晶片模組封裝（.lti Chip Module; MCM)、 夕重日日片封Ιό己 fe體（multichip package memory; MCP) 等複合式封裝（System on Package ; SOP)為主。 SOP是指將兩顆以上的晶粒（di e)透過封裝的方式整合 在一起’亦有人稱之為 SiP(system-in-package)。SOP 可 分成三個主要的類型一MCP(multichip package)、 MCM(nuiltichip modules)與 IP(integrated packaging)， 其中 MCP 包含兩種主要的形式：i. 並排式 (side-by-side) ; 2.堆疊式（stacked chip)。 I28l2l9 其封裝方式與特性敘述如下：
1 ·請見第1圖所示，為並排式多曰H 並排式結構100成本較低，^ 構100,該 腳數和個別封裝差不多。仁口曰曰片間沒有連結導致， 2 _請見第2圖所示，為堆疊式容曰κ 堆疊式結構2〇〇所需之面積縮曰曰jy ^结構2⑽，該 些元件到同-個製程上，二=疋，否能成功的整合這 Φ a u 且縱使整合到相同的晶圓萝裎 ，曰曰片的效能是否會降低、良率 多少、4 At U久你θ X人 午疋否此、准持、成本增加 Μ題Γ影響產品的績效(如咖㈣）’這 複 ==!。此外’為了不讓封裝過程變得太過 制’且當越多的晶粒被封裝在 m的限 (Held)會隨之降低。 （也表不封叙的良率 及义’本=供一種具有被動元件的連接模組構造 一1私，以解决I知封裝方法的問題。 【發明内容】 ☆本發明的主要目的為提供一具有被動元件的連接模 含至少一元件置放區以及至少一被動元件，其中該 :破動元件之尺寸可進行調整以產生該連接模組所需之阻 ::該等元件置放區之連接電路、數量以及分佈位置可依 品求動態調整，使得該模組之尺寸得以縮小。 本Is明的另一目的為提供一具有被動元件的連接模 Λ，包含至少一兀件置放區以及至少一被動元件，該具有 被動元件的連接模組之結構膜厚度以及導線尺寸可以依不 同元件阻值之需求進行調整。 本發明的另一目的為提供一具有被動元件的連接模 組，包含至少一兀件置放區以及至少一被動元件，其中該 等元件置放區之連接電路係建於該電連接模組内’得以減 1281219 低封裝腳數以增加該連接模組信賴性。 本發明的另一目的為提供一且 組，包含至少-元件置放被動凡件的連接模 等兀件置放區係為一凹型梓， — 口〆 嵌入元#又描4 + 土 9 了甘入入至V 一元件使得該等 甘入入兀件不增加该電連接模組之高度， ^ 導體製程時得以降低製程難度。 &進灯堆豐式半 本發明的另一目的為提供一 裝製程連接模組，包含至少1元#有=/力「凡件的晶圓級封 元件，該連接模组可於6成扭壯、，文區以及至少一被動 本發明的另一目的Γί衣亚進行測試後方進行分割。 執一此、、 的為提供一半導體製程以形成具有被 70的連接模組，該具有被動元件的連接模组之表面# 少-元件置放區。以應材枓進仃杈組保護並定義至 组，本:人明另一目的為提供-具有被動元件的晶片模 =2少一元件置放區、至少-被動元件以及至少-中该等被動元件之尺寸可進行調整以產生咳連接 態調整，使得該模組=寸= ^ ’、入忒等元件置放區内，以增加該半導俨 核組之信賴性。 曰刀成千V體 為達成上述目的，本發明提供 模組，包含： Μ績仏種具有被動兀件的連接 一基板； 一連接線佈局，向合$ Φ —、击k A 描徂兮S μ » 匕3至^ 連接線，形成於該基板上， 耠i、忒aa片杈組運作所需之電性連接； 佈月上被動iJVV布局’包含至少一被動元件形成於該連接線 值 佈局電連接，提供該連接模組運作所 至〆日日片置放區’該等晶片置放區係触刻該基板產 1281219 ί域與3接線佈局以及該被動元件佈局形成該基板不同 =人_片置放區中，與該連接線佈局電連接。 形成旦VI動Λ，本觸提供-種半導μ 心成具有破動凡件的晶片模組，包含下列步驟： a)於一基板上形成一連接線佈局，該 3至(:2 ί 1接t提：該晶片模組運作所需之電性連:; 元件佈=;=:成:;:元件佈局，該被動 提供該晶片模組運作；=值與錢接線佈局電連接’ (C ) |虫刻該基板產斗—曰 局位於該基板上不同區置放槽與該連接線佈 ^ dj置入至少一外加晶片於該等晶片置放槽； ^ ) σ電連接該等外加晶片與該連接線佈局。 =由單純示範最適於實施本發明的模式中之一，熟 之-、式It t 士將可自以下說明瞭解本發明的特點及優勢中 且”施二或九部’其中該說明顯示及描述本發明的較佳 〆、ϋ貝方也例。如應可睁角栗丨 廿曰i奴^ , “」笊解到，本發明能有不同具體實施例， 離太j節係能在各種明顯方面中修改，且全部不脫 限制^。因此，附圖及說明書基本上可視為範例性而非 【實施方式】 一綠Iΐ ΐ =圖所不，為本發明之一較佳實施例所揭露之 择m t製程’用以形成具有被動元件的連接模組。本 貝也二百先於一晶圓（wafer)上形成一連接線佈局。 μ見第3A圖、第3B圖、第3C圖、第3D圖以及第 回所不，係為本發明之一較佳實施例之連接線佈局製程。 1281219 321，隨後沈積一Ί晶人圓310上形成-第-氧化梦層 化石夕層如上。本1=中合於該第一氧 熱擴散法於晶圓上形成， # π 1 ^層321係利用 理沈積法形成，但亦Ϊ以:Si銘銅合金層322係利用物 賴;Π:Γ第圖一第32:，ί金層奶上進行 =係透，光顯影製程對該第一銘銅二：：以 ：義’ Ik後蝕刻未被定義為導線之該“ 订二 區域以形成該第一導線佈戶i 則化鋁層322 士主見笛^同佈局323，取後移除光感應材料。 明見弟3C圖，於該第—導線佈局上形成一第二 層324，隨後利用曝光顯影製 卜中差、一资 ^ ^ p衣狂 π 口系弟一乳化石夕層324 連接開口佈局325,敍刻被定義為連接開 μ弟二虱化矽層324區域，使得該第一導線佈局323 料^進」丁電連接的區域得以暴露’最後移除光感應材 以弟一電連接開口佈局324Α所暴露之該第一導線佈局 ，域323’係為該第一導線佈局323之電性連接點，為該 弟一導線佈局323進行電連接之接觸區域。 二斤请見第3D圖，沈積一第二鋁銅合金（AlCu)層325於 =第二氧化矽層324上，並透過該電連接開口佈局與該第 ‘線佈局3 2 3結合以實現與該第一導線佈局3 2 3的電連 接三隨後於該第二鋁銅合金層325上進行蝕刻製程以形成 第一導線佈局3 2 6，本實施例中，該蝕刻製程係透過曝 光顯影製程對該第二鋁銅合金層3 2 5進行導線定義，隨後 餘刻未被疋義為導線之该弟二铭銅合金層3 2 5區域以形成 該第二導線佈局3 2 6，最後移除光感應材料。 請參考第3E圖所示，於該第二導線佈局326上形成一 第三氧化矽層327，隨後利用曝光顯影製程，於該第三氧 化石夕層3 2 7上定義一第二連接開口佈局3 2 8，蝕刻被定義 1281219 j連接開口之該第三氧化矽層32 佈局326上用以進行電連接的區域 感應。該第二電連接開口佈局3 露==光 ^26區域，係為該第二導線佈局: 该弟二導線佈局326進行電連接之接觸區域。’…，為 上述之製程係用以於一指定基底上 局，其中該連接線佈局之連 成連接線佈 完成該模組電線連接繞佑為兩層’但不以此為限， 均應視為已為本;=所需之層數、齡 口月參考苐3F圖’第3G圖以及第岡在势 實施例之-被動元件製程。請參考第3F;係佳 與-成長底層332 (seed :r'層一r 一） 佈局328與該第二導線佈局奶結 :土長底層332形成於該擴散阻絕層331上。 该擴散阻絕層331係為該第二 底層332之間的緩衝層，弊、、、局25與该成長 根源於銅的高擴散係；以“ 331的使用， 問題，均可獲得解見介電層的低附著性 -5J- ^ ^ r w X ㊉見用於該擴散阻絕層331的材料 了為鎢（W)、鈦鎢合金（Tiw)、钽 何才十 氮化鈦（Ti/TiN)等材料及盆έ人Λ ，.- ( a/TaN)、鈦/ 成長底層332用以提=二但亦不以此為限。該 過大所發生之脫二屬4 =成長所需且避免應力 而調整，常見為銅（Cu) 底f 332可視金屬層材料 為限。 及孟（Au )材料，但亦不以此 請見第3G圖，於該成長底 333，該第一光阻層;上形成一弟一先阻層 形定義之光感應材：中為可藉由曝光顯影完成圖 1十本貝訑例中，該第一光阻層333可 ίο 1281219 :用光感應苯環丁烯（photosensitive BCB)或聚亞醯胺 P〇lyiimde)等材料實施，但亦不以此為限，如還氧樹指 光或UV膠等，亦為常見之接合材料。隨後利用曝 ，...、員：製程，於該第一光阻層333上定義一 ，口佈局334’钱刻被定義為被動元件 ！ 2請區域。該被動元件連接開口佈“ 该成長底層332區域，係A兮*旦广威〇〇〇 坏*路之 為誃点真广感成長底層332之電性連接點， …、/成長氐層332進行電連接之接觸區域。 之，，於該被動元件連接開口佈局334所暴露 =成長底層332區域上形成進行電鍍 :動：件350’例如電感、電阻以及電容元件等成至 ，件之特性可藉由該被動元件連接開口佈局開口之大 形=厚度以及表面狀態等參數變化加以控制。 接著利用光阻去除劑去除該第一 、， 對該等被動元件、兮忐真广既0 先阻層333，亚分別 *別進二使;;==該擴散阻絕謂 值，未被該等被動元件覆蓋口而 阻絕層331均去“ 成長底I 332以及該擴散 … J玄陈以暴路忒弟二氧化矽層327。 上述製程係用以於該連接綠社 件，任何基於上述製程，而對事順形成至少一被動元 程材料進行變化之實施方式，均;11序、钱刻方式以及製 請見第31圖、第3j圖以/；：為為本發明所揭露。 佳實施例之晶片置放區製；4:=，係為本發明-較 塗佈（sPin-c〇ating)方法塗佈1 圖’百先利用旋轉 利用曝光顯影製程，於該第二光阻層川’隨後 開口佈局342以及一晶片放置曰Ο上疋義一連接墊 義為連接墊開口以及晶片放置區：：：，3’韻刻被定 區域’並對該第二光阻層34二=弟二光阻請 使得該第二光阻層341 更：-lng)處理， 又吻連接杈組之效果。 1281219 請參考第3 J圖，隨後對嗲楚一 使得該等被動元件350上用^進弟且層341進行餘刻， 露，並且利用反應離子敍刻連接的區域得以暴 形成至少一晶片放置區344_该連接結構進行餘刻，以 請見第3K圖所示，將至少_ 置放區344巾，本實施例中，晶片345置於該等晶片 黏附於該等晶片置放區344 _利=樹脂將該等晶片345 用接合（Wlreb〇nding)^二:隨後將該等晶片345利 接區域進行電連接，但亦不二此二之ff被動元件電連 換實施。 電連接的方式，均可被替 本發明係為製作一連接模组 ，部分印刷電路板之電連接=透=圓封裝結 了先藉由晶圓封裝與被動元件；人“-連：模組’ ¥間與複雜度，減少封穿時門* 縮減製程所需 衰減與。桑訊對系統造輪;”塑元件的信號 使晶圓以及被動元件之良率護層的運用， 之回度使得封裝結構厚度不肖，增加後二 *因晶片 度。再者透過被動元件與晶片之a = ®式製程的難 雜接線所造成之信賴信降低。同用硬=兩者間複 該封裝結構之強度。 更化之光阻層增加 目的本=士:前述說明係用於示範及說明 之範例性且或：切明限於該精確形式或已揭示 限制性。頻先前說明應視為示範性而非 报明顯的。具體實施例之士將是 <疋馬了更佳解釋本發 12 1281219 明的原理及其實際應用之 術人士理解用於久Mί杈式攸而允許熟習此項技 特定使用或所涵芸實作之久插& ^ 且具有適合於 ,^ 孤作之各種修改。本發明意於使复筋田备 由在此所附之申請專利範圍及其等 甘士/ 有說明1則所有請求項均包含中除非另 瞭解到，蝴習此項技術；；；：二 =範圍。應 者，本揭露查所義之本發明鴨。再 # # - 中有何兀件及組件係意以用於公甲，又 ::70太或組件是否在以下申請專利範圍中明確地；及。 Ϊ二書的摘要係提供用以順應摘要規則之要求，
者迅速地確定從此揭露書發布的任何專利L 圍的料或意涵。 _心解釋或限”請專利範 【圖式簡單說明】 第1圖為並排式多晶片封裝結構1 00。 第2圖為堆疊式多晶片封裝結構200。 參 第3Α圖、第3Β圖、第3C圖、第3])圖 係為本發明之一較佳實施例之連接線佈局製程弟3E圖 /弟3F圖、帛3G®以及帛3H圖係為本發明 例之一被動元件製程 季乂锃貝施 第31目、第3Jffl以及帛㈣係為本 轭例之晶片置放區製程。 車又仏貝 【主要元件符號說明】 1 0 0並排式多晶片封裝結構 2 0 0堆疊式多晶片封裝結構 310晶圓 321第_斤 322第一銅化鋁層 —虱化矽層 324第二氧化矽層 325繁 弟一導線佈局 325弟一電連接開口佈局 13 1281219 326第二導線佈局 328第二連接開口佈局 3 3 2成長底層 334被動元件連接開口佈局 342連接墊開口 343佈局晶片放置區開口佈局 3 4 5晶片 350被動元件 327 331 333 341 344 第三氧化矽層 一擴散阻絕層 第一光阻層 第二光阻層 晶片置放區
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Claims (1)

1281219 7,如申請專利範圍第3項所述 # ^ ^ ^ 元件係利用下㈣數之—^ Γ ^組，其中該等被動 .,Λ/ ^ /數之一者加以控制：該等被動元件之 大小、形&、厚度以及表面狀態。 m 專利範圍第6項所述之晶片模組，其中該等連接 9.如申言主糞剎r円结〇者力以控制.線覓、結構層厚度。 係利用月 6 項所述之晶片模組，其中該保護層 烯 下列电性隔絕材料之一種形成：光感應苯環丁 烯、聚亞醯胺、還氧樹指以及UV膠。 10二申請專利範圍第1項所述之晶片模組，其中該等被動 =以及該等晶片置放區之位置以及數量可依需要改變動 θϋ置。 11. 一種具有被動元件的連接模組，包含： 一基板； 1連接線佈局，包含至少一連接線，形成於該基板 ，提供該晶片模組運作所需之電性連接； im被動70件佈局’包含至少—被動元件形成於該連 j佈局上，與該連接線佈局電連接，提供該連接模組 運作所需之阻值； …Λ少一外加元件置放區，料外力口元件置放區係蝕 '二土板產生，與該連接線佈局以及該被動元件佈局形 成該基板不同區域。 12·如申請專利範圍第u項所述之連接模組，更包含一擴 散阻絕層以及一成長底層，其中該擴散阻絕層與該連接 線佈局電連接’該成長底層形成於該擴散阻絕層上，與 該被動元件佈局電連接。 〃 13·如申請專利範圍第12項所述之連接模組，更包含一保 護層，該保護層覆蓋於該被動元件佈局以及該連接線佈 局上，用以增加該晶片模組可靠性。 14·如申請專利範圍第丨丨項所述之連接模組，其中該等被 16 1281219 係利用下列參數之—者加以控制： 之，小、形狀、厚度以及表面狀態。 .二範圍第u項所述之連接模組，其中 ΐ線係利用下列參數之—者加以控制：線寬、結構層厚 之項所:之連接模組，其中該等連 度。]用下列參數之一者加以控制：線寬、結構層厚 範圍第13項所述之連接模組，其中該等被 之女’、1用下列參數之一者加以控制：該等被動元件 之大小、形狀、厚度以及表面狀態。 專利範圍第16項所述之連接模組，其中該等連 I次係利用下列參數之一者加以控制：線寬、結構層厚 it如申請專利範圍第13項所述之連接模組，其中該保 下列電性隔絕材料之_種形成：光感應苯環丁 締、聚亞酿胺、還氧樹指以及UV膠。 20.如申請專利範圍第u項所述之連接模組， 動元件以及該等晶片置放區之位置以及數量可中依需等被 改變配置。 而 21·如申請專利範圍第18項所述之連接模组，其中該基底 係為一砍晶圓。 一 22.一種半導體製程，用以形成具有被動元件的晶片模组， 包含下列步驟： 、 (a )於一基板上形成一連接線佈局，該連接線佈局 匕含至少一連接線，係提供該晶片模組運作所需之電性 連接； (b )於該連接線佈局上形成一被動元件佈局，該被 動元件佈局包含至少一被動元件，與該連接線佈局電連 17 1281219 接，提供該晶片模組運作所需之阻值； 佈乂Ci蝕刻該基板產生一晶片置放佈局，該晶片置放 师局包含至少_曰Η A力又 & 日日片置放槽，該寺晶片置放槽與該連接 線佈局位於該基板上不同區域； 建接 ^ d )置入至少一外加晶片於該等晶片置放槽； Μ ^ 電連接該等外加晶片與該連接線佈局。 申請專利範圍帛22項所述之半導體製程，該 更包含下列步驟： v d J
於忒連接線佈局上形成一擴散阻絕層，其中該 阻絕層與該連接線佈局電連接； 〃月 於該擴散阻絕層上形成一成長底層，與該擴散阻 層電連接。 24,如申請專利範圍第22項所述之半導體製程，該步驟。 更包含下列步驟： ^ 於該連接線佈局以及該被動元件佈局上形成一保護 層’用以增加該晶片模組之可靠性。 25·如申請專利範圍第23項所述之半導體製程，該步驟（㈠ 更包含下列步驟： 於該連接線佈局以及該被動元件佈局上形成一保護 層’用以增加該晶片模組之可靠性。 26.如申請專利範圍第24項所述之半導體製程，其中該保 護層係利用下列電性隔絕材料之一種形成：光感應苯環 丁烯、聚亞醯胺、還氧樹指以及UV膠。 2 7 ·如申請專利範圍第2 5項所述之半導體製程，其中該保 護層係利用下列電性隔絕材料之一種形成：光感應苯環N 丁烯、聚亞醯胺、還氧樹指以及UV膠。 2 8 ·如申清專利範圍弟2 2項所述之半導體製程，盆中該等 被動元件以及該等晶片置放槽之位置以及數量可依需要 改變配置。 18
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