1279781 九、發明說明： 【發明所屬之技術領域】 本發明係相關於光碟機，尤指一種用於光碟機中以產生尋軌誤 差訊號的裝置與相關方法。 【先前技術】 光碟片（optical disc)是現今一種極為普遍的儲存媒體，資料 可以藉由光碟片之執道（track)上的坑洞（pit)記錄於光碟片上。 而要將所圮錄的資料I買取出來時，光碟機必須藉由伺服控制系統 (servo control system)的輔助，將雷射二極體所輸出之雷射光正 確地聚焦於光碟片的執道上，以藉由感測反射光的方式讀出光碟 片所儲存的資料。 一般而言’讀取頭上的光感測器會感測自光碟片所反射出的光 訊號來產生A、B、C、D四個電訊號。依據A、B、c、D訊號產 生出尋執誤差訊號（trackingerrorSignai，TE)之後，伺服控制系 統即可藉由檢視尋執誤差訊號TE的變化，來判斷雷射二極體所輸 出之雷射光的聚焦點是否偏離光碟片上之執道。 在產生尋軌誤差訊號TE的過程中，習知技術的裝置係以相位 檢測器所輸出之訊號的脈波寬度來判斷A+C訊號與β+D訊號之 間的相位差異狀況，因此會面臨一個問題，就是在需要提供精確 、+轨吳差σ扎就TE日$，必需使用局的取樣頻率（sampiing rate) 1279781 來將類比訊號轉換成數位訊號 具有較高頻率的時脈訊號中。 且後端的數位電路亦必須操作在 【發明内容】 因此目的之―’在於提供—種使聰低之取樣頻率即 可生較局崎度之雜縣峨缝置與糊方法。、 、本發明係揭露了-種產生一尋執誤差訊號之裝置，包含：一光 感測，組’絲依據―雷射光照射至-光則所反射出之光束產 生第-舰喊與H比喊；—舰紐轉換模組，轉 接於該光感戦組’时分別將該第滅及該第二類比訊 號轉換為-第-數位訊號以及一第二數位訊號；一延遲模組，龢 接於該類比數_減組，絲分觀_第-錄峨及該第 二數位訊號以產生-第—延遲訊號以及—第二延遲訊號；以及一 訊號產生模組，耦接於該類比數位轉換模組與該延遲模組，依據 依據該第一、第二數位訊號與該第一、第二延遲訊號產生該尋軌 誤差訊號。 本發明另揭露了一種產生一尋轨誤差訊號之方法，包含：依據 一反射光產生一第一類比訊號與一第二類比訊號；將該第一類比 訊號轉換為一第一數位訊號，以及將該第二類比訊號轉換為一第 "一數位虎，延遲該弟一數位訊號以產生^赛'一延遲訊號’以及 延遲該第二數位訊號以產生一第二延遲訊號；以及依據該第一、 1279781 第二數位訊號與該第一、第二延遲訊號，產生該尋執誤差訊號。 【實施方式】 第1圖為本發明用於光碟機中以產生尋軌誤差訊號TE之裝置 的一實施例示意圖。光感測模組21 〇係用以產生一第一類比訊號 A+C以及一第二類比訊號β+D。交流耦合電容（ACcoupling capacitor) 222、224以及低通濾波器232、234係用以消除該些類 比訊號A+C、Β+D中的直流成分以及雜訊成分。數位類比轉換器 242、244係用來以近似於通道位元率ι/t (χ]^ηη6ι bit rate)的取 樣頻率1/Ts (l/Ts与1/T)分別地將第一類比訊號A+c及第二類比 訊號Β+D轉換成一第一數位訊號s丨及一第二數位訊號幻(其中， 訊號S1與S2皆為單一位元的數位訊號)。延遲單元252、254係 分別地將訊號SI、S2延遲2Ts的時間以產生一第一延遲訊號01 以及一第二延遲訊號D2 (請注意，此處所使用的延遲時間2Ts僅 用作舉例說明，設計者亦可以自行決定延遲單元252、254所應延 遲的時間長度）。訊號產生模組255則可依據訊號SI、S2、D1、 D2輸出一尋軌誤差訊號。 在本貫施例中，訊號產生模組255包括一數位邏輯模組260 及一充電泵270。數位邏輯模組260係用來依據訊號S1、S2、D1、 D2來產生一第一控制訊號up以及一第二控制訊號D〇WN。充電 泵270則可在訊號UP處於致能狀態時提升尋軌誤差訊號TE的電 位’或是在訊號DOWN處於致能狀態時降低訊號见的電位。 1279781 幻產生變化，亦即第—類比訊號A+c的相位係領先於第二類比訊 #U B+D的相位’此時數位賴模組26〇 t致能w訊號，以透過 充電泵270提升尋軌誤差訊號的電位：相似地，在訊號％的值不 同於訊號SI、Dl、D2的值時，或是在訊號m的值不同於訊號 第2圖所示係為對應於數位邏輯模組260運作情形之真值表 的-實施例。在本實關巾，在職S1的财騎減s2、m、 D2的值時’或是在訊號D2的值不同於訊號8卜幻、的值時， 數位邏輯· 26G可判_第—編罐si先於第二數位訊號BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk drive, and more particularly to an apparatus and related method for use in an optical disk drive to generate a tracking error signal. [Prior Art] An optical disc is an extremely popular storage medium today, and data can be recorded on a disc by a pit on a track of a disc. When the recorded data I is to be taken out, the optical disk drive must correctly focus the laser light output by the laser diode on the obstruction of the optical disk by the aid of a servo control system. The data stored in the optical disc is read by sensing the reflected light. In general, the light sensor on the read head senses the light signal reflected from the optical disc to generate four electrical signals A, B, C, and D. After the tracking error signal (TE) is generated according to the A, B, c, and D signals, the servo control system can determine the laser light output by the laser diode by examining the change of the seek error signal TE. Whether the focus point deviates from the obstinacy on the disc. In the process of generating the tracking error signal TE, the device of the prior art judges the phase difference between the A+C signal and the β+D signal by the pulse width of the signal output by the phase detector, and thus faces One problem is that in order to provide accurate, +-track sigma, it is necessary to use the local sampling frequency (sampiing rate) 1279781 to convert the analog signal into a clock signal with a higher frequency of the digital signal. Moreover, the digital circuit of the back end must also operate in the [Summary of the Invention] Therefore, the purpose of the present invention is to provide a method for squeezing and pasting a miscellaneous county that can make the sampling frequency of Cong low. The present invention discloses a device for generating a search error signal, comprising: a light sensing, the group 'silver according to the laser light irradiated to the light, the reflected light beam produces the first-ship shouting and the H-screaming ;------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- In the analogy_subtraction group, the first and second digit signals are used to generate a -first delay signal and a second delay signal; and a signal generation module coupled to the analog digital conversion The module and the delay module generate the tracking error signal according to the first and second digital signals and the first and second delay signals. The invention further discloses a method for generating a tracking error signal, comprising: generating a first analog signal and a second analog signal according to a reflected light; converting the first analog signal into a first digital signal, and Converting the second analog signal to a first bit, delaying the digital signal to generate a 'send delay signal' and delaying the second digital signal to generate a second delay signal; and according to the first The 1279781 second digit signal and the first and second delay signals generate the seek error signal. [Embodiment] Fig. 1 is a view showing an embodiment of an apparatus for generating a tracking error signal TE in an optical disk drive of the present invention. The light sensing module 21 is configured to generate a first analog signal A+C and a second analog signal β+D. ACcoupling capacitors 222, 224 and low pass filters 232, 234 are used to eliminate DC components and noise components in the analog signals A+C, Β+D. The digital analog converters 242, 244 are used to respectively respectively classify the first analog signal at a sampling frequency of 1/Ts (l/Ts and 1/T) which is approximately equal to the channel bit rate ι/t (χ]^ηη6ι bit rate). The A+c and the second analog signal Β+D are converted into a first digital signal s丨 and a second digital signal illusion (where the signals S1 and S2 are single bit digital signals). The delay units 252, 254 respectively delay the signals SI, S2 by 2Ts to generate a first delay signal 01 and a second delay signal D2 (note that the delay time 2Ts used herein is only used as an example, design The delay time of the delay units 252, 254 can also be determined by themselves. The signal generation module 255 can output a tracking error signal according to the signals SI, S2, D1, and D2. In the present embodiment, the signal generation module 255 includes a digital logic module 260 and a charge pump 270. The digital logic module 260 is configured to generate a first control signal up and a second control signal D〇WN according to the signals S1, S2, D1, and D2. The charge pump 270 can raise the potential of the tracking error signal TE when the signal UP is enabled or decrease the potential seen when the signal DOWN is enabled. 1279781 The illusion changes, that is, the phase of the first analog signal A+c is ahead of the phase of the second analog signal #U B+D. At this time, the digital module 26 〇t enables the w signal to pass through the charging pump 270. Raise the potential of the tracking error signal: similarly, when the value of the signal % is different from the value of the signal SI, D1, D2, or the value of the signal m is different from the signal shown in the second figure, it corresponds to the digital logic mode. An example of a truth table for the operation of group 260. In this real customs towel, when the value of the S1's financial riding minus s2, m, D2' or when the value of the signal D2 is different from the value of the signal 8, the digital logic 26G can be judged _ the first - can Si precedes the second digit signal
Sb S2、D2的值時’數位邏輯模組26〇可判斷出第二數位訊號 S2先於第-數位訊號S1產生變化，亦即第二類比訊號b+d的相 位係領先於第-類比訊號A+c的相位，此時數位邏輯模組26〇則 會致能DOWN訊號’以透過充電泵27()降低尋執誤差訊號的電位。 由於本實施例中的數位類比轉換器242以近似於通道位元率 ι/t的取樣頻_ i/Ts進行取樣，假設第一類比訊號a+c領先於第 二類比訊號B+D共的時間，則當此抓時，訊號up處 於致能狀態的齡大約會正比於^ (脚喊现憎會包含有 更夕的1 )因此*第—類比訊號A+c與第二類比訊號B+D之間 的相位差距越大，充電栗27〇就會受訊號w的控制將尋軌誤差訊 ，TE充電至較高的準位；相同的原理，假設第—類比訊號a+c 洛後於第二類比訊號B+D共―的時間，則當β Ts時，訊 就DOWN處於致能狀態的機率大財正比於△〖（亦即訊號 1279781 D0WN中將會包含有更多的，Τ，），因此若第一類比訊號Α+C與第 二類比訊號B+D之間的相位差距越大，充電泵27〇就會受訊號 DOWN的控制將尋執誤差訊號旺放電至較低的準位。故很明顯 的’藉由檢視本實施例之裝置所產生的尋轨誤差訊號丁£的變化狀 況’祠服控制系統即可得知第一類比訊號A+c與第二類比訊號 B+D之間的相位差異狀況，並據此對讀取頭進行適當的伺服控制。 而為了要讓本實施例裝置中的數位電路部分235 (包含有類比 數位轉換模組240、延遲模組25〇、以及數位邏輯模組施）以近 似於通道位元率1/T的鮮1/Ts進行，本發明的裝置還可以 包含有額外賴率轉換模組跡用來將與真實通道㈣咖喊 同步的時脈訊號CLK (頻率為1/τ)經過刪的頻率調整後，產 德員如/ts的咖规CLK，（射，ν#μ歸，且眶 二，本實施例裝置中的數位電路部分235作為運作的依據。 本貫施職置亦可喊_外的_元件來產生頻率為· 2_峨CLK，，輸卩是可行的作法。在—實補巾、，^率轉 換模組280可包括一鎖相迴路電路。 第3圖為本發明所提出之方法的 述各個步驟。 一實施例流程圖 以下將詳 步驟410 : 步驟420 : —光碟⑽反射出之光束產生- tr 與1二類比訊號㈣。 S1，以 將弟一類比訊號A+c轉換為-第-數位訊號 1279781 及將第二類比訊號B+D轉換為一第二數位訊號S2。 在一貫施例中，第一與第二數位訊號S1、S2皆為具 有單一位元的數位訊號。 步驟430 :延遲第一數位訊號S1以產生一第一延遲訊號D卜延 遲第二數位訊號S2以產生一第二延遲訊號D2。此處 延遲的時間可由系統設計者自行決定。 步驟440 :依據第一、第二數位訊號S1、S2與第一、第二延遲 訊號D卜D2，產生一第一控制訊號up與一第二控制 訊號DOWN。舉例來說，第2圖所示的真值表即為第 一、第二數位訊號SI、S2，第一、第二延遲訊號D1、 D2與第一控制訊號up及第二控制訊號D〇WN間之 關係的一個例子。 步驟450 :依據第一控制訊號up與第二控制訊號D〇WN產生一 哥軌决差訊5虎TE。在一貫施例中，可於第，訊號UP 處於致能狀態時提升尋執誤差訊號TE之準位，以及 於弟一訊?虎DOWN處於致能狀態時，降低尋執誤差 訊號TE之準位。 雖然在前述各實施例中皆以訊號A+C作為第一類比訊號、以 afl7虎B+D作為弟二類比虎’貫際上’分別使用a訊號、b訊號 來作為第一、第二類比訊號，或是分別使用C訊號、1)訊號來作 為第一、第二類比訊號亦是可行的作法。本發明所揭露的裝置所 使用的數位電路並不複雜，因此在設計上會相當地簡易，而且數 1279781 位電路操作的頻率也不用太高。此外本實施例之裝置可以有較寬 的相位偵測範圍（〜±2T)。 乂見 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式簡單說明】 第1圖為本發明之產生尋執誤差訊號之裝置的一實施例示意圖。 第2圖為第1圖之數位邏輯模組運作情形之真值表的一實施例。鲁 第3圖為本發明所提出之方法的一實施例流程圖。 【主要元件符號說明】 212 、 214 210 222 、 224 232 、 234 235 240 242 、 244 250 252、254 255 260 加法器 光感測模組 交流耦合電容 低通渡波器 _ 數位電路部分 數位類比轉換模組 1-bit數位類比轉換器 延遲模組 延遲單元 訊號產生模組 數位邏輯模組 11 1279781 270 280 充電泵 頻率轉換模組The value of Sb S2 and D2 can be determined by the digital logic module 26 to determine that the second digital signal S2 changes before the first digital signal S1, that is, the phase of the second analog signal b+d is ahead of the first analog signal. The phase of A+c, at this time, the digital logic module 26〇 enables the DOWN signal 'to reduce the potential of the seek error signal through the charge pump 27(). Since the digital analog converter 242 in the present embodiment samples at a sampling frequency _ i/Ts close to the channel bit rate ι/t, it is assumed that the first analog signal a+c is ahead of the second analog signal B+D. Time, when this is caught, the age of the signal up is about proportional to ^ (the foot will now contain 1 more) So the * analog signal A+c and the second analog signal B+ The greater the phase difference between D, the charging pump 27〇 will be controlled by the signal w to track the error, TE is charged to a higher level; the same principle, assuming the first analog signal a+c The second type of time is the same as the signal B+D. When β Ts, the probability that the DOWN is in the enabled state is greater than △ 〖 (that is, the signal 1279781 D0WN will contain more, oh, Therefore, if the phase difference between the first analog signal Α+C and the second analog signal B+D is larger, the charge pump 27〇 is controlled by the signal DOWN to discharge the seek error signal to a lower level. Bit. Therefore, it is obvious that the first analog signal A+c and the second analog signal B+D can be known by examining the change of the tracking error signal generated by the device of the embodiment. The phase difference between the two, and accordingly, the servo head is properly controlled. In order to make the digital circuit portion 235 (including the analog digital conversion module 240, the delay module 25A, and the digital logic module) in the device of the embodiment, the channel bit rate is 1/T. /Ts, the device of the present invention may further comprise an additional rate conversion module trace for adjusting the frequency of the clock signal CLK (frequency 1/τ) synchronized with the real channel (4) screaming, For example, the ts of CLK, CLK, ν#μ, and ,, the digital circuit part 235 in the device of this embodiment serves as the basis for the operation. The local application can also call the _ external component. The generation frequency is · 2_峨 CLK, and the transmission is feasible. The actual package, the conversion rate module 280 can include a phase-locked loop circuit. Figure 3 is a description of the method proposed by the present invention. Steps 420: The optical beam reflected by the optical disc (10) generates a -tr and 1 analog signal (4). S1, to convert the analog signal A+c into a -first- The digital signal 1279871 and the second analog signal B+D are converted into a second digital signal S2. In the embodiment, the first and second digit signals S1 and S2 are digital signals having a single bit. Step 430: delaying the first digit signal S1 to generate a first delay signal D and delaying the second digit signal S2. A second delay signal D2 is generated. The delay time can be determined by the system designer. Step 440: generating a first according to the first and second digital signals S1 and S2 and the first and second delay signals D and D2. The control signal up and a second control signal DOWN. For example, the truth table shown in FIG. 2 is the first and second digit signals SI, S2, and the first and second delay signals D1, D2 and the first An example of the relationship between the control signal up and the second control signal D 〇 WN. Step 450: Generate a trajectory 5 tiger TE according to the first control signal up and the second control signal D 〇 WN. In the first step, when the signal UP is in the enabled state, the level of the seek error signal TE is raised, and when the brother DOWN is enabled, the level of the seek error signal TE is lowered. In each of the embodiments, the signal A+C is used as the first analog signal. Use afl7 tiger B+D as the second class to use the a signal and b signal as the first and second analog signals respectively, or use the C signal and 1) signal as the first and second respectively. Analog signals are also a viable practice. The digital circuit used in the device disclosed by the present invention is not complicated, and therefore is relatively simple in design, and the frequency of the 1279781 bit circuit operation is not too high. Furthermore, the apparatus of this embodiment can have a wide phase detection range (~ ± 2T). The above description is only the preferred embodiment of the present invention, and all changes and modifications made by the scope of the present invention should be covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing an embodiment of an apparatus for generating a seek error signal according to the present invention. Figure 2 is an embodiment of the truth table of the operation of the digital logic module of Figure 1. Lu Figure 3 is a flow chart of an embodiment of the method proposed by the present invention. [Main component symbol description] 212, 214 210 222, 224 232, 234 235 240 242, 244 250 252, 254 255 260 Adder light sensing module AC coupling capacitor low-pass waver _ Digital circuit part digital analog conversion module 1-bit digital analog converter delay module delay unit signal generation module digital logic module 11 1279781 270 280 charge pump frequency conversion module
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