KR950003172B1 - Error detecting circuit for optical disk - Google Patents

Abstract

The circuit comprises a photo pickup section(1) for detecting optic signal from an optic disk, an EFM(Eight to Fourteen Modulation) signal generator(3) for converting voice signals into EFM signals for processing digital signals, an amplifier for amplifying voice signals to detect a defect signal, a comparator(5) for converting voice signals into logic signals to eliminate voice signal included within defect signal block, and a defect signal detection logic means(6) which separates a defect signal from a mixed signal(voice and defect signal) to generate a defect detecting signal.

Description

Digital detection circuit of optical disc defect

1 is a block diagram of a conventional analog defect detection circuit,

2 is an output waveform diagram showing output nodes of respective parts in a conventional analog defect detection circuit.

3 is a block diagram of a digital circuit of a reproducing apparatus for detecting a defect of an optical disc according to one embodiment of the present invention;

4 is a detailed circuit diagram of a defect signal detection logic means that is part of the digital circuit configuration diagram of the present invention.

The present invention relates to an optical disc reproducing apparatus, and more particularly to a circuit for detecting a defect in an optical disc in a digital manner.

An optical disc reproducing apparatus uses an optical disc as a recording medium, and is classified into a compact disc reproducing apparatus (hereinafter referred to as "CDP") and a laser disc reproducing apparatus (hereinafter referred to as "LDP") according to the size of the disc. In the optical disc, various frequency signals are sampled every 44.1 kHz, and each sample value is converted into a digital signal quantized into 16 bits and recorded. Specifically, nine types of pits are recorded as spiral tracks.

As such, the digital information recorded on the pit of the optical disc is reproduced as a radio frequency signal through a playback device, and then an amplifier and a speaker are connected through a D / converter and a low pass filter. It is driven to recognize the information of the original signal.

However, in the process of reproducing the original signal, waveforms of shapes different from the original signal may be reproduced due to defects or error data of the optical disc. The main reasons for this are as follows. The carelessness of the user is caused by defects on the surface of the optical disc that are beyond the allowable range.

Until now, the detection of the above-described defects has been implemented using an analog detection circuit. Referring to FIG. 1, the conventional analog detection circuit will be described and its problem will be described.

The conventional analog defect detection circuit has an optical pickup means (1) for detecting an optical signal from an optical disc, an audio signal generating means (2) for converting an optical signal detected by the optical pickup means into a voice (RF) signal, Audio signal amplification means 4, defect signal detection means 8, defect signal lower hold means 7, buffer means 9, differential means 10, and comparison means 11.

Hereinafter, referring to FIG. 2, which shows the connection relationship between the means and the output waveform diagram at each node of the analog type defect detection circuit shown in FIG.

In general, a reproducing apparatus includes optical pickup means for condensing light on a signal surface of an optical disc to detect light reflected from the optical disc. Thus, light picked up differently depending on the presence or absence of a pit is input to an audio signal generating means and electrically The output waveform of A is converted into a voice (RF) signal and outputted to the node A, and a defect signal is mixed in FIG. Subsequently, the output signal of the node A is amplified twice by the voice signal amplifying means 4, outputted to the node B, and the output waveform amplified twice in FIG. 2 (b).

Subsequently, the amplified waveform output to the audio signal amplifying means 4 is input to the defect detecting means 8 and the defect signal lower holding means 7, respectively, and in the defect signal detecting means 8, the audio signal has a short time constant. The defect signal included in the signal is separated and output to the node C through the amplifying stage of the buffer means 9, and the defect signal lower holding means 7 holds a signal level immediately before the occurrence of the defect signal with a long time constant. Is outputted to the node D through the amplifying stage of the buffer means 9. The output waveforms output to the nodes C and D are shown in Figs. 2 (c) and 2 (d), respectively.

Subsequently, each output waveform of the nodes C and D passes through the differential means 10 and the comparison means 11, and the final defect detection signal is output through the output terminal of the comparison means 11, and the output waveform thereof is the second waveform. (e) It consists of a pulse train as shown in FIG.

As described above, large and small time constants are required for the defect detection and defect holding of the conventional analog system, and passive elements (resistors and capacitors) having large effective values are required to obtain the large time constant. However, in the integrated semiconductor device, when a large value of the passive devices are integrated on a chip, a large area is occupied and the chip area becomes large, making it difficult to integrate the passive devices. It is used on the printed circuit board. As a result, an increase in the number of lead-pins of a semiconductor device package is inevitable, which increases the manufacturing cost of the semiconductor device and also increases the complexity of the printed circuit board of the printed circuit board of the regeneration device. It may also reduce the reliability of the assembly process and the regeneration apparatus.

Accordingly, an object of the present invention is to provide a digital defect detection circuit and to solve the problems of the conventional analog method.

Digital defect detection circuit for achieving the above object of the present invention includes an optical pickup means for detecting an optical signal from an optical disk, an audio signal generating means for converting an optical pickup signal to a voice signal, and an EFM for digital signal processing. (Eight to Fourteen Modulation) EFM signal generation means for converting to a signal, voice signal amplification means for amplifying a voice signal for detecting a defect signal, comparison of converting a voice signal into a logic signal and removing the voice signal included in the defect signal section And a defect signal detection logic means for separating the defect signal from the mixed signal of the audio signal and the defect signal to generate a defect detection signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of a defect detection circuit according to the digital method of the present invention.

The construction and connection of the amplifying means 4 is the same as in the conventional method, and further description thereof will be omitted. The EFM signal generating means 3 into which the voice output signal of the voice signal generating means 2 is inputted is an integrator that integrates the EFM signal in order to prevent the error of the EFM signal from being generated by the asymmetry of the optical disk in the manufacturing process of the optical disk. 32) and a comparator 31 for eliminating error signal generation due to asymmetry of the optical disc by using the signal integrated as a reference voltage. That is, the present invention uses the output voltage having the characteristic that the reference voltage of the comparator 31 follows the DC voltage of the EFM logic signal through the integrator 32 to the reference voltage input terminal of the comparison means 5. And a defect signal are tuned to the reference voltage to facilitate the conversion into an accurate logic signal, and to prevent the noisy voice signal contained in the defect section from being converted to a logic level.

Subsequently, a logic signal (hereinafter referred to as an RFO signal) converted from the comparison means 5 to a logic level is applied to the defect signal detection logic means 6, so that an accurate defect signal is detected. 4 is a circuit diagram of a defect signal detection logic means. The operation principle of the circuit diagram is as follows.

The defect signal detection logic means 6 is composed of an input portion 61, an output waveform shaping portion 62, a synchronous counter portion 63, and a divider portion 64 of the system clock signal CK. In the circuit diagram, the reset signal and the clock signal CK are signals generated by the system.

The RFO signal converted to the logic level in the comparison means 6 is applied to the D input of the delay flip-flop (hereinafter referred to as DRN) constituting the input unit 61, and the DRN has a reset stage and a system clock signal. It is a feature that is triggered by a negative trigger. If the input signal is at the "high" level, the synchronous counter unit 63 configured by combining nine trigger flip-flops (hereinafter referred to as TRN) and logic gates performs up-counting. Like the DRN, the TRN has a reset stage and is booted by a clock signal. If the RFO signal goes to the "low" level while the sync counter is up-counting, the QB output is booted from the DRN and the Q _B output becomes the "high" level. Therefore, the Q _B output to the reset terminal of the TRN in the sync counter 63 is performed. This reset signal is applied to reset the synchronous counter. The count clock signal input to the clock CK terminal of the TRN is a clock signal of 200 kHz frequency generated by dividing a system clock signal of 17 MHz by 1/85 by the frequency divider 64. The frequency divider 64 Is composed of a combination of seven TRNs, one DRN, and a logic gate. When the divided clock signal of the 200 kHz frequency divided as described above is input to the TRN of the synchronization counter unit 63 and the RFO signal input to the DRN of the input unit 61 becomes the "high" level, the counter is booted to the count clock. When the RFO signal cycle is 50μsec or more through up-counting, the defect detection signal (hereinafter referred to as DFCT) is output at the "high" level, and when the RFO signal cycle is 1.4msec or more, the DFCT signal becomes "low" level. The output waveform shaping section 62 is configured with the up-counting output of the counter as an input.

The output waveform shaping unit 62 includes two logic sum gates that sequentially combine the up-counting outputs and two flip-flops (hereinafter, referred to as CSH) for sampling and holding the up-counting output signal by a divided count clock signal. And the Q ₁ output of the input unit DRN and the two CSHs together to finally output the DFCT signal. As described above, the output waveform shaping unit 62 outputs the DFCT signal at the “high” level to the output terminal when the RFO signal is “high” level when the period is 50 μsec by up-counting. When changing from the "high" level to the "low" level, the synchronous counter unit 63 is reset so that the DFCT signal output is also set to the "low" level. Therefore, when the RFO signal cycle is within 50 μsec to 1.4 msec, depending on the period of the defect signal. Even the magnitude of the defect signal can be detected accurately. Signals having a defect size of 1.4 msec or more do not need to be detected because the digital signal processor is out of the defect compensation capability range.

The DFCT signal detected in this way is finally input to the servo unit to hold the focus and the loop of tracking to prevent the playback device from malfunctioning. Therefore, according to the present invention, by configuring the defect detection circuit in a digital manner, the large effective value passive elements (resistors and capacitors) conventionally required for defect signal detection and lower hold are unnecessary, so that it is easy to integrate into a semiconductor chip. In addition, since the lead pin of the semiconductor device package is reduced, the manufacturing cost of the semiconductor device package can be reduced, and the printed circuit of the printed circuit board becomes less complicated. Therefore, the overall manufacturing cost can be greatly reduced and the reliability can be improved. There is a number.

Claims (7)

In detecting a defect of an optical disc from an optical disc reproducing apparatus, optical pickup means for detecting an optical signal from the optical disc, voice signal generating means for converting the optical pickup signal to a voice signal, and converting the voice signal into an EFM signal for digital signal processing EFM signal generating means, voice signal amplifying means for amplifying a voice signal for detecting a defect signal, comparing means for converting the voice signal into a logic signal and removing the voice signal included in the defect signal section, mixed signal of the voice signal and the defect signal And a defect signal detection logic means for separating the defect signal from the defect signal and generating a defect detection signal. 2. The digital defect detection circuit according to claim 1, wherein the output waveform of the audio signal generating means is input to the comparator of the EFM signal generating means and the amplifier of the audio signal amplifying means, respectively. The EFM signal generating means is composed of a comparator and an integrator, the EFM signal output from the comparator is output in an integrating waveform at the integrator, and the integrated output signal is configured to logic the comparator and the voice signal. A digital defect detection circuit, characterized in that it is inputted as a reference voltage of a comparison means for converting a signal and removing a sound signal in a defect signal section. The input unit to which the RFO signal outputted from the comparison unit is input by the defect signal detection logic means, the division unit for generating a counting clock signal by dividing the CK signal by 1/85, and the counting clock signal synchronizes the TRN to increase the period of the RFO signal. And an output waveform shaping part configured to output a defect detection signal through a process of demultiplexing and holding the period of the signal counted up by the synchronization count part and the period of the divided clock clock signal. Digital defect detection circuit. 5. The frequency converter of claim 4, wherein the input unit is configured with one DRN to form an RFO signal as a D input, and the divider is combined with one DRN to divide and synchronize the input CK signal frequency by combining seven TRNs and logic gates. And a clock counter and a logic gate of the TRN of the counter unit, wherein the synchronous counter unit is formed by combining nine TRNs and logic gates. 6. The digital defect detection circuit according to claim 5, wherein the DRN and the TRN have a reset terminal and are booted by a clock signal. 5. The digital defect detection circuit according to claim 4, wherein a period of the defect signal detectable by the defect signal detection logic means has a period of 50 µsec to 1.4 msec.