TWI279090B - Serial input digital-to-analog converting device - Google Patents

Abstract

A serial input digital-to-analog converting device suitable for converting an n-bit digital signal to an analog signal is disclosed, wherein the digital signal is early divided into m bytes and the converting device comprises m digital-to-analog converters for independently receiving the m bytes before converting the m bytes into corresponding analog voltages, a voltage divider capable of providing two voltages to each digital-to-analog converter so that each digital-to-analog converter can use the difference between the two received voltages as a dynamic voltage variation range for converting the m bytes and the difference between the two received voltages provided by the voltage divider to the kth digital-to-analog converter is (delta V)/(2<n(m-k)/m>}, and an adder for adding the analog voltages to generate the analog signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a digital analog conversion device, and more particularly to a serial input digital analog conversion device. [Prior Art] Referring to FIG. 1, a digital analog converter 9 is similar to that proposed in US Pat. No. 622,593,1 B1, and includes a voltage selection unit 91, a first capacitor 92, a second capacitor 93, and a capacitor. The first switch 94, the second switch 95 and a third switch 96. The voltage selection unit 91 includes an inverter 911, a first switching switch 912 and a second switching switch 913. The first switch 912 can receive a maximum voltage Vh, and the second switch 913 can receive a minimum voltage λ Π ' and the value of the highest voltage vh is greater than the value of the lowest voltage vi, and the two voltages Vh, The difference Δν (= Vh - Vl) of the VI is the dynamic voltage range of the digital analog converter 9. In addition, the first switch 912 is a p-channel metal-oxide semiconductor (PM0S), and the second switch 913 is an N-channel metallized semiconductor (Negative_channei Metal-Oxide)

Semiconductor, referred to as NM0S). The inverter 911 can sequentially receive an n-bit serial digital signal, and is the least bit of the serial bit signal (Least)

The Significant Bit (LSB) dJ4 starts to receive and then receives the larger bit ' in sequence' until the maximum bit (M〇si: gignificant Bit, MSB) dw is received. 1279090 The output of the inverter 911, the gates of the first and second switch 912 913 of the on μ are electrically connected, and the output of the first switch is 912, and the output switch 912 can be used to control the first and first switch 912. The switching of 913, g〆^ θ, that is, the input signal to the inverter 911 is “1, the output signal of the reverse #0a state 911 will turn on the first switch 912 and the The first-cut 广+广, 弟一-switch 913 is not turned on, and at this time, the %-pressure selection unit 91 generates a difference ΔV between the sacred sacred voltage Vh and the lowest voltage VI, and The highest voltage Vh 1 vn is sent to the first switch 94 through the first switch 912, and the apricot enters the Shidouguang

The digital signal input to the inverter 911 is that the first switch 912 will not conduct and the second switch 913 will be turned on, so the voltage difference generated by the voltage selection unit 91 will be zero 'and The low power 1 V! is sent to the first switch 94 through the second switch 913. The first, second, and third switches 94, 95, 96 φ are connected to each other and located in the voltage selection list; ^ Q Between the first switch 912 of β &amp; . _ and the lowest voltage V1. The first end of the first capacitor 92 is electrically connected between the first switch 94 and the second switch 95, and the other end is electrically connected to the lowest voltage and the second capacitor 93 is electrically connected. Between the second switch 95 and the first switch 96, and the other end is electrically connected to the lowest voltage. And the capacitance values of the first capacitor 92 and the second capacitor 93 are the same. When the first switch 94 is turned on, and the second and third switches 95 are not turned on, the first capacitor 92 is charged, and when the second switch 95 is turned on and the first and third switches 94, 96 are both When not conducting, the amount of power on the first capacitor 92 is evenly distributed on the first and second capacitors 92, 93. If it is assumed that the serial digital signal to be processed is 4 bits, that is, 1279090 [AH d〇], the process of converting the digital signal into an analog signal by the conventional digital analog converter 9 includes the following steps: Step S1 is In a first clock cycle, the digital signal d〇 is input to the inverter 911 in a state where the first and third switches 94 and 96 are turned on and the second switch 95 is not turned on. The first capacitor 92 will be charged until the voltage across the first capacitor 92 reaches AVxd, and the second capacitor 93 will be reset. In the next clock cycle, that is, the second clock cycle, the second switch 95 is turned on, and the second switch 95 is turned on and the first and third switches 94 and 96 are not turned on. The charge on the capacitor 92 is evenly distributed across the first and second capacitors 92, 93, and the voltage value on the second capacitor 93 will become (Δν χ (1 ()) / 2. Step S3 is in the third clock cycle And when the first switch 94 is turned on and the second and third switches 95, 96 are not turned on, the digital signal mountain is input to the inverter 911, so the first capacitor 92 is charged until the first The voltage across a capacitor 92 reaches Δν χΐ. Step S4 is to turn on the second switch 95 during the fourth clock cycle, and the second switch 95 is turned on and the first and third switches 94 and 96 are not turned on. The charge on the first valley 92 is evenly distributed to the first and second capacitors 92, 93, and the voltage value on the second capacitor 93 becomes (((Δvxd〇)/2) + (厶¥\山)) / 2. Step S5 is in the fifth clock cycle, and is in a state where the first switch 94 is turned on and the first and second switches 95, 96 are not turned on. The digital signal i is input to the inverter 911, so the first capacitor 92 is charged until the voltage across the first valley 92 of 1279090 reaches a ν χ d2. Step S6 is in the sixth clock cycle, And the second switch 95 is turned on, and the second switch 95 is turned on and the first and third switches 94, 96 are not turned on, and the electric charge on the first capacitor 92 is evenly distributed to the first and second capacitors 92, The voltage value on the '93' and the second capacitor 93 will become ((((((( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( (

Step S7 is in the seventh clock cycle, and in a state where the first switch 94 is turned on and the second and third switches 95, 90 are not turned on, the digital signal hair is input to the inverter 911, so the first A capacitor 92 will be charged until the voltage across the first capacitor 92 reaches AVxd3. Step S8 is that during the eighth clock cycle, the second switch 95 is turned on, the second switch 95 is turned on, and the first and third switches 94 and % are not turned on, and the charge on the first capacitor 92 is It will be evenly distributed to the first and second capacitors 92, 93, and the voltage value on the second capacitor 93 will become (((((( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( (4/4)+(^/8)+((10/16)) X AV. Therefore, when inputting a bit signal of one bit, a step of charging the first capacitor 92 is required, and another a step of evenly distributing the charges of the first and second capacitors 92, 93, so inputting one bit requires time of = clock cycle to be processed, so in the case of rounding in digital information bits, Then you need 8 (= 4x2) clock cycles to ^ 70 integer bit signal 'so when the input digital signal has N bits, NX2 clock cycles, and when the number of # N becomes larger, the gate: in multiples [Department] Accordingly, it is an object of the present invention to provide a serial input digital analog conversion device that can speed up processing performance. In the present invention, the serial input digital analog conversion device of the present invention is suitable for converting a serial digital signal having 11 bits into an analog signal, and the n bits of the serial digital signal are sequentially divided into m bytes, and m is an integer greater than or equal to 2, and the bits are sequentially ordered from a lower to a higher caller to a first byte to a first bit. The serial input digital analog conversion device includes m digital analog converters, a voltage divider and an adder. The digital analog converters are respectively a first digital analog converter to an mth digital analog converter, and The q-th digital analog conversion H is to receive the q-th byte, and respectively convert the byte into a corresponding analog electric dust, where q is an integer between j and m and contains (5). The voltage converter is electrically coupled to the digital analog converters and is capable of providing two voltages for each of the |bit analog converters such that the digital analog converters can respectively perform dynamics based on the difference t of the received two The range of eMule changes to convert the bits, and the device provides The voltage difference of the second power of the k-th digital analog converter is (2), ❿k is an integer between 1 and melon and contains 1 and m. The adder is to process the digital analog converter The above-mentioned classes are added to the analog signal to generate the analog signal. [Embodiment] The above-mentioned and other technical contents, features and effects of the present invention are preferably implemented in conjunction with the reference pattern below: 279〇9〇^ The detailed description of the example will be clearly shown. Referring to Figures 2 and 3, a preferred embodiment of the serial input digital analog conversion device of the present invention comprises m (m is an integer greater than or equal to 2) digit analogy The converter DACfDACm, a voltage divider 2 and an adder 3 〇 the digital analog converters DAC1 to DACm are a first digital analog converter DAC!, a second digital analog converter DAc2 to an mth number, respectively. Bit analog converter DACm. A tandem digital signal [dnidn2.did〇] which is an n-bit can be equally divided into m bytes D丨~Dm, and the bits Di~Dm are ^i = [d(n /m).,...d〇] - ^ . The Dj byte is input to the j-th digital analog converter DACj, and j is a positive integer between 1 and m and containing 1 and m. The voltage divider 2 includes m resistors Ri~Rm, and the resistors Ri~Rm are a first resistor core, a second resistor &amp; to a mth resistor, and the resistors R1 Rmm are mutually The relationship between the resistance values is as listed in equation (1)

a _R, formula (1) 10 l2?9〇9〇 R,

R 2--1 2m -2_ (m-l)n, 2--1

An R m-2 -Rw - Rm_2

The resistors R^Rm are connected in series, and the electrical connection sequence is sequentially the first resistor core, the second resistor R2, the third resistor core to the mth resistor Rm, and the read first resistor I is electrically connected to a minimum voltage V1. The mth resistor is electrically connected to a highest voltage Vh, and the resistors Ri~Rm divide the highest voltage and the lowest voltage VI to generate a plurality of different reference voltages Vfi~Vfm1, each digital analog converter DAC1 ~ DACm receives the lowest voltage VI, in addition, the ith digital analog converter DACI also receives the reference voltage Vfi, and 1 is between 1 and (111-1) and contains an integer of 1 and (111_1), and the The 111 digital analog converter DACm receives the highest voltage Vh. Therefore, the voltage divider 2 is provided. The voltage difference ( ) of the two voltages to the k-th digital analog converter, and AV is Vh and k is an integer between 1 and m and containing i and m. The first digital analog converter DAC1 is similar to the digital analog converter 9 mentioned in the prior art, and includes a voltage selection unit u, a first capacitor 12, a second capacitor 13, a first switch 14, and a second The switch 15 and a third switch 16. The voltage selection unit U includes an inverter m, a first switching switch 112, and a second switching switch 113. And the first and second capacitors 12, 11 1279090 13 and the first to third switches 14 to 16 and the components included in the voltage selection unit u (ie, the inverter m, the first and second switch li2) The operation of ii3) is the same as the prior art, so it will not be repeated here. The first-to-digital analog converter is different from the conventional one in that the first changeover switch 112 receives the reference voltage Vfi. And the inverter m, 接收 sequentially receives the serial digit signal of the first byte D1=[d(n/m)丨· is], and starts from the smallest bit d〇 of the serial bit signal Receive, and then receive the larger bit in sequence until the maximum bit d(n/m)-l in the byte Di is received. When the digital signal input to the inverter 111 is i, the voltage difference generated by the voltage selection unit u of the first digital analog converter DAC1 is VfrV1. When the digital signal input to the inverter lu is 〇, the voltage difference generated by the voltage selection unit 11 will be zero. The second to mth digital analog converters DAC2 to DACm are similar to the digital analog conversion |§ D AC 1, and include a voltage selection unit η, a first capacitor 12, a second capacitor 13, and a first The switch 14, the second switch 15 and a third switch 16. However, the second to mth digital analog converters DAC2 to DACm are different from the first digital analog converter DAC!, and the second to fifth digital analog converters DAC2 to DACm further include a fourth switch 17 The fifth switch 18. The fourth switch 17 is electrically connected between the lowest voltage vi and one end of the first capacitor 12, and the fifth switch 18 is connected in series with the fourth switch 17, and is connected to one end of the first capacitor 12 and the second capacitor 13 one end is electrically connected. And the pth (p is a positive integer of 2 to m) digital analog converter DACP 12 1279090 reverser 111 is a serial digital signal respectively receiving the Dp byte, and the least bit of the byte Dp Start receiving and then receive larger bits in sequence. And the qth (q is a positive integer of 2 to (m-1)) the first switching switch 112 of the digital analog converter D ACq receives the reference voltage vfq, when the digital signal input to the inverter 111 is At 1 o'clock, the voltage difference generated by the voltage selection unit ij is Vfq-VI. When the digital signal input to the inverter in is 0, the voltage difference generated by the voltage selecting unit u will be zero. And the first switching switch 112 of the m-th digital analog converter is, receives the highest voltage Vh, and when the digital signal input to the inverter ln is 丨, then the voltage difference generated by the voltage selecting unit 11 The value is Vh-VI. The 逡 adder 3 includes (m-1) control switches 31, and the control switches 31 are electrically connected between the second capacitors 13 of the adjacent digital analog converters DAC1 to DACm, respectively, and when the adder 3 When the control switch 31 is in a non-conducting state, the fourth and fifth switches 17, 18 located in the second to fifth (five) digital analog converters DAc2 to DACm will be turned on. At this time, each digital analog converter DAG~DACm These control switches 31 will be turned on when they are operating normally and until all of the digital analog converters DACpDACm have processed the digital signals in the bits Di~Dm. And when the control switches 31 are turned on, the fourth and fifth switches 17, 18 located on the second to the m-th digital analog converters DAG~DACm will be non-conducting. The voltage across the second capacitor 13 of each digital analog converter DAC^DACm will be added to obtain the final converted complete analog signal, and the analog signal is output from the mth digital class 13 1279090 than the converter DACm . As shown in FIG. 4, a simple example is given to illustrate the operation of the embodiment, and for convenience of explanation, the melon is described as 2, 4, and at this time, the digital analog converters are respectively The first digital analog converter DAC1 and the second digital analog converter dac2, m the voltage divider 2 includes only the first resistor Ri and the second resistor R2. And the tandem digital signal is [d3d2d is]...bit and can be divided into two tuples, which are the first byte Dr1^do] and the second byte D2=[d3d2]. According to the formula (1), the relationship between the first resistor R2 and the first resistor &amp; is: (2η η \ f 2x4 4 \ r2 = 2 m - 2m - heart = 2, 2-^1 y 4 -Rj = 4-Rj and in this case 'the resistance of the first-resistance Ri is 1 ohm, then the second resistor R2 is 3 (=4)) ohm. Therefore, the first resistor &amp; The reference voltage Vfi outputted between the second resistor R2 is equal to νι + Δν / 4, and ΔV = Vh - V1. The input voltage of the first-digital analog converter DAC1 is the lowest voltage V1 and the reference voltage Vfl The voltage difference between the two voltages is Δν/4, and the input voltage of the second digital analog converter is the lowest voltage vi and the highest voltage Vh, and the voltage difference between the two voltages % and vh is Δν Therefore, the voltage difference of the input of the second digital analog converter is the first digital analog converter £) gossip: 4 (= 22) times of 1. In this case, the adder 3 includes only one control switch 31 between the second capacitor 13 of the first digital analog converter DAC! and the second capacitor 13 of the second digital analog converter dac2. And the first and the second number 14 12790900 bit analog converter DAC, DAC2 converts the digital signal into a parallel ratio signal flow comprising the following steps: Step S1 is in a first clock cycle, in the addition The control switch 31 of the device 3 is not turned on, and the first and second switches 14, 16 of the first digital analog converter DACI are turned on and the second switch 15 is not turned on, and the digital signal d is input to the first Digital analog converter DACI&lt;inverter 111. And at the same time, in the second digital analog converter DA. First, first

2. The fourth and fifth open _ 14, 16, 17, 18 are turned on and the second switch 15 is not turned on, and the digital signal d2 is input to the inverter 111 of the second digital analog converter DAC2. At this time, the first capacitor 12 of the first digital analog converter DAC1 is charged until its voltage across the voltage reaches Λν/4Χ (1., and the second capacitor 13 is combined. The second digital analog converter Cap DAC2 - Capacitor 12: The charge is charged until its voltage across the voltage reaches ΛνΧ (ΐ2, and the second capacitor 13 will be clamped and step S2 is at the next clock cycle', ie the second clock, causing the adder 3 The control_31 is not turned on, and the first and third switches Μ and Μ of the DAC and the second digital analog conversion are not turned on.

'But the second switch of the first-digital analog converter DACI turns on, and turns on the first digital analog converters DAC !5, 17, and i8. The first, fourth, and fifth switches convert the charges on the first and second digital analog converters DaCi, d to the first and second capacitors ί22, 13: electricity, so the first-to-digital analog conversion The value 152 1279090 on the second capacitor 丨3 of the device (4) 1 will become (the coffee frequency, and the second digital analogy converts the stomach μ. The voltage value on the second capacitor 13 will become (Δνχ(ΐ2)/2. Step S3 is: when the third clock cycle is 'on the first and second digital analog converters DAC 丨, the first switch 14 of the DAC 2 is turned on and the second and third switches 15, 16 are not turned on, and the second digit Analog converter dac2;: The switch 17 and the fifth switch 18 are also turned on, and the digital signal mountain and the 信号 are simultaneously input to the inverter ill of the first and second digital analog converters DAq, DAC2, respectively. When the first digital analog converter DA is used, the first capacitor 12 is charged until its voltage across the voltage reaches Δν/4χ (1, and the second capacitor of the second digital analog converter DAC2 is also charged until its cross The voltage reaches AVxd3. Step S4 is to make the control switch 31 of the adder 3 during the fourth clock cycle. Not conducting, and respectively turning on the first and second digital analog converter DAC!, the second switch 15 of the DAG, so that the second switch 15 is turned on and the first and third switches 14 and 16 are not turned on, and at the same time, The fourth switch 17 and the fifth switch 18 of the second digital analog converter DAC2 are turned on. The charges on the first capacitor 12 of the first and second digital analog converters DACI, DAG are evenly distributed to the first and the first On the two capacitors 12, 13, the voltage value on the second capacitor 13 of the first digital analog converter DACI will become (((ΔV/4 X d〇)/2) + (A v / 4 X mountain) /2 can be organized as ((di/8)+(d〇/16))xAV, and the voltage value on the second capacitor 13 of the second digital analog converter DAC2 will become (((ΔνΧ(ΐ2)) /2) +(AVxd3))/2, which can be sorted into ((d3/2)+(d2/4)) XAV. Step S5 is to turn on the control switch 31 of the adder 3, and the 16th 1279090 The first digits of the second digital analog converters DAC1, DAC2, 1 4, 1 A, and the second switches are non-conducting, and the fourth and fifth switches 17, 18 of the second digital analog converter DA are not turned on. , the second digit analogy 2 p output - ((d3/2) + (d2 / 4) + (di / 8) + (d 〇 / 16)) XAv analog number. ^ So the same is a 4-bit input digit The signal is converted into the analog signal. The conventional signal requires 8 clock cycles, and this example only requires 5 clock cycles ^ and here there are two digital analog converters DAC!, DAC2, when the input digital signal has In the case of n bits, only 2 _&gt;&lt;2 small n+1 clock cycles are required, which is a lot more than the conventional clock cycle = 2 and when the number m of the digital analog converters increases The speed of the invention of the present invention is greatly increased, and only (n/m) x 2 + i clock cycles are required. It is worth noting that if the number of bits η input to the digital signal of the present invention is not If the multiple of m is used, the front of the digital signal can be inserted into zero, and the number t of zeros can be inserted, so that t plus n can be multiplied by m. In addition, it should be noted that the voltage selection unit 11 of each of the digital analog converters DAC1 to DAC2 may also be as shown in FIG. 5 and differ from the above in that the first switching switch 112 is 0S, and the NMOS is The gate receives the byte Dj instead of being electrically connected to the inverter (1). However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention, All still 17 ^79090 is covered by the patent of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a conventional digital analog converter; FIG. 2 is a system architecture diagram of a preferred embodiment of the serial input digital analog conversion device of the present invention; ·, a n \7' \wv Electrically fixed, Fig. 4 is a circuit diagram when the claw of the preferred embodiment is 2. Fig. 5 is a connection of a voltage selecting unit of the preferred embodiment. Electrical connection

18 1279090 [Description of main component symbols] 11 _·····... Voltage selection unit 111 ··· •...Inverter 112...•...First changeover switch 113...•...Second switcher 12··.·. •...first capacitor 13·····•...second capacitor 14••... •...first switch 15······...second switch 16·.··_•...third switch 17·· ·.. •...fourth switch 18••...•...fifth switch 2.........divider 3.........•...adder 31... •...control switch〇!......... Bytes D2...·...bits Dj...·...bits Dm_i...bytes

Dm........bytes DACI •...first digital analog converter DAC2 ····second digital analog converter DAC.! •• (m-1) digital analog converter DACm·... Mth analog analog converter

Ri.........the first resistor R2.........the second resistor

Rm-i ... the (m-1) resistor

Rm ........mth resistance

Vh........the highest voltage VI.........the lowest voltage

Vfl .......reference voltage

Vfm.! ••...reference voltage 19

Claims (1)

1279090 X. Patent application scope: 1 · A serial input digital analog conversion device, which is suitable for converting a serial digital signal with n bits into an analog signal, and the serial number is η5 or η bit The element may be firstly divided into m bytes, and m is an integer greater than or equal to 2, and the bits are sequentially ranked from the lower to the higher bits by a first byte according to the order of the bits. a second byte to an mth byte, the serial input digital analog conversion device comprises: · m digital analog converters, respectively a first digital analog conversion state to a first digital analog converter And the q-th digital analog converter receives the q-th byte and converts the q-th byte into a corresponding analog voltage, and q is an integer between 1 and m and containing 1 and m; a voltage divider electrically coupled to the digital analog converters and capable of providing two voltages to each digital analog converter such that the digital analog conversions can respectively be based on the difference between the received two voltages Dynamic voltage k range to convert the bits, and the voltage divider The voltage difference between the two voltages supplied to the second digital to analog converter ladle is of, and k is 1 to! Between 1 and an integer of 1 and 111; and an adder that adds the analog voltages processed by the analog to the converter to produce the analog signal. 2. According to the serial input digital analog conversion device described in the scope of the patent application, the voltage generated by the voltage divider includes a maximum voltage, a minimum voltage and (m-1) voltage values. a reference electric dust located between the highest voltage and the lowest voltage, and each digital analog converter is connected to: the lowest voltage, in addition, the ith digital analog converter also receives the reference 20 1279090 5 · According to the scope of application The serial input digital analog conversion device of claim 2, wherein the first digital analog converter comprises a voltage selection unit, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, the voltage selection unit is electrically connected to one end of the first switch, and sequentially receives the first byte, and receives the minimum bit of the first byte, and then sequentially receives a large bit, and when the digital signal input to the voltage selection strict element is i, the voltage selection unit will generate a dynamic electric dust range of Δν/(2; Χ(Π1-1)) and output the reference voltage to The first switch When the digital signal input to the voltage selection unit is 0, the dynamic voltage range generated by the voltage selection unit will be zero, and the minimum voltage is output to the first switch, and the first, second, and third switches are contending Connected together and between the voltage selection unit and the lowest voltage, and one end of the first capacitor is electrically connected between the first switch and the second switch, and the other end is electrically connected to the lowest voltage, and One end of the second capacitor is electrically connected between the second switch and the third switch, and the other end is electrically connected to the lowest voltage, when the first switch is turned on and the second and third switches are not When the current is turned on, the first capacitor is charged, and when the second switch is turned on and the first and third switches are not turned on, the power on the first capacitor is evenly distributed on the first and second capacitors. 6. According to the serial input digital analogy described in item 5 of the scope of the patent application, the analog digital converter comprises a voltage selection unit, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch and a fifth switch, and X is between 22 1279090 2 and Π1 and includes an integer of 2 and m, the voltage selection unit and the first One end of the switch is electrically connected, and sequentially receives the third byte, and starts receiving by the smallest bit of the β-X-th byte, and then sequentially receives the larger bit, and when input to the voltage selection When the digital signal of the unit is 丨, the voltage selection unit will generate a dynamic voltage range of ΔV/(2i(-)) and output a &quot;hai reference voltage or the southmost voltage to the first switch, and when input to the When the digital signal of the voltage selection unit is 〇, the dynamic voltage range generated by the voltage selection unit will be zero, and the minimum voltage is output to the first switch, the first, first, and third switches are connected in series and the first One end of the switch is electrically connected to the voltage selection unit, The fourth switch is electrically connected to the lowest voltage and the terminal of the first capacitor, and the other end of the first capacitor is electrically connected between the first switch and the second switch, and the fifth switch is connected in series with the fourth switch And electrically connected to one end of the first capacitor and one end of the second capacitor, and the other end of the second capacitor is electrically connected between the second and third switches, when the first, fourth, and When the five switches are turned on, and the second and third switches are not turned on, the first capacitor is charged, and when the second, fourth, and fifth switches are turned on and the first and third switches are not turned on, The amount of electricity on the first capacitor is evenly distributed over the first and second capacitors. The serial input digital analog conversion device according to the sixth aspect of the invention, wherein the voltage selection unit comprises an inverter, a first switch and a second switch, the first switch is a The p-channel metal oxide semiconductor, and the second switch is a germanium channel metal oxide semiconductor, and the turn-in end of the inverter receives the byte 23 The digital signal of the inverter is the Japanese car, 兮楚^ 疋 呀. The first switch will not be turned on and the δ hai brother--the switch will guide the donkey + Tian Hao Guan liver conduction, then the lower The voltage is sent to the first switch through the second switch. 1279090, and the output end is electrically connected to the gates of the first and second switchers, and the switch is controlled by the first and second switchers, and when the digital signal input to the X inverter is 1 The output signal of the inverter will turn on the first switch and the second switch will not be turned on, and the reference voltage or the highest voltage is sent to the first switch through the first switch, and When the digital signal input to the inverter is ,, the first switch will not conduct and the second switch will be turned on, and the lowest voltage is sent to the first switch through the second switch. 8. The serial input-type digital analog conversion device according to the sixth item, wherein the voltage selection unit includes an inverter, a first switch, and a second switch. The first and second switchers are N-type channel metal oxide semiconductors, and the gate of the first switch and the input of the inverter receive the byte, and the output of the inverter is The second switch is electrically connected. When the digit (4) input to the reverse H is 1, then the first switch will be turned on and the d switch will not be turned on and the reference voltage or the highest The voltage is sent to the first switch through the first switch, and is input to the 9. according to the patent application range changing device, wherein the serial input digital analogy of the sixth item is converted to a capacitor and the The capacitance value of the second capacitor is the same. 10. The serial input digital analogy according to the sixth aspect of the patent application refers to the 24 1279090 changing device, wherein the 兮~force σ method includes a plurality of control switches, and the control switches respectively Electrically connected to the brother (Ρ+1) between the second capacitance of the digital analog converter, and ρ von 1 to (m-ι) and containing an integer of 1 and (m_l)' and "when the control switch is turned on, the second to The fourth and fifth switches on the 帛m digital analog conversion switch will be in a non-conducting state. At this time, the voltage across the second capacitance of each digital analog converter will be added to obtain the final conversion. The analog signal. 25