TWI330003B - - Google Patents

Description

1330003 IX. The invention relates to a capacitive digital analog conversion circuit and an image device and an audio device including the same, which are more capable of time division. A capacitive digital analog conversion circuit for a capacitive device and a video device and an audio device including the capacitive digital analog conversion circuit. [Prior Art] Referring to FIG. 1, a conventional digital analog converter 9 is similar to that proposed in U.S. Patent No. 6,225,931 B1, and includes a voltage selecting unit 91, a first capacitor 92, a second capacitor 93, and a capacitor. The first switch 94, the second switch 95 and a third switch 96. The voltage selection unit 91 includes an inverter 913, a first switching switch 911 and a second switching switch 912. The first switch 91A can receive a minimum voltage VI' and the second switch 912 can receive a highest voltage vh»the value of the highest voltage Vh is greater than the value of the lowest voltage V1, and the two voltages Vh and VI The difference Δν (= ν ΐ ι ν ΐ) is the dynamic voltage range of the conventional conventional digital analog converter 9. In addition, the first switch 9A is an N-channel metal oxide semiconductor Metai_〇xide Semiconductor (NM〇s), and the second switch 912 is a channel metal oxide semiconductor (p〇sitivechannel) Metai_〇xi(Je

Semiconductor ’ pm〇s). The inverter 913 can sequentially receive an N-bit serial digital signal [aN_iaN_2~aia<)], and is the least significant bit of the _ column digital signal 5 1330003 (Least Significant Bit' LSB) a. The reception starts, and then the higher bit is received in order until the most significant bit (MSB) aN_丨 is received. The output of the inverter 913 is electrically connected to the gates of the first and second switches 911, 912, and the output signal of the inverter 913 can be used to control the first and second switches 911, 912. Switching. When the digital signal input to the inverter 913 is 1, the output signal of the inverter 913 will make the first switch 911 non-conductive and the second switch 912 be turned on. At this time, the output value of one of the voltage selection units 91 is equal to the highest voltage Vh, and a voltage difference Δγ is formed between the voltage and the minimum voltage V1, and the highest voltage Vh is sent to the first through the second switch 912. - Switch 94. § When the digital signal input to the inverter 913 is 〇, the output signal of the inverter 913 will turn on the first switch 911 and the second switch 912 will not be turned on. At this time, the voltage selection unit 91 The output value of the output terminal is equal to the minimum voltage VI, and a voltage difference of zero value is formed between the minimum voltage V1, and the minimum voltage V1 is sent to the first switch 94 through the first switch 911. The first, second and third switches 94, 95, 96 are connected in series in sequence and are located between the second switch 912 of the dust selection unit 91 and the lowest power vi. The _ terminal of the _ capacitor 92 is electrically connected between the first P system 94 and the second switch 95, and the other end is electrically connected to the lowest voltage V and the other end of the second capacitor 93 is electrically Connected between the second switch 95 and the third switch 96, and the other end is electrically connected to the lowest voltage VI. The capacitance values of the first capacitor 92 and the second capacitor 93 are the same. The first capacitor 94 is turned on, and when the second and third switches 95, 96 are not turned on, the first capacitor 92 is charged. When the second switch 95 is turned on and the first and third switches 94, 96 are not turned on, the charges on the first and second capacitors 92, 93 are evenly distributed. If it is assumed that the serial digital signal to be processed is *bit, the conventional digital analog to analog converter 9 converts the digital signal into an analog signal. The following steps are included: Step S1 is in a first clock cycle. (Clock Cycle), the digital signal a is input to the inverter 913 in a state where the second and second switches 94, 96 are turned on and the second switch 95 is not turned on, and the first capacitor 92 is charged until the The voltage across the valley 92 reaches AVxa(), and the second capacitor 93 will be reset. And step S2 is in the next clock cycle, that is, in the second clock cycle, » the first opening 0 95 is turned on and the first and third opening %, % are non-conducting the charge on the first capacitor 92 It will be evenly distributed to the first and second electrical commands 92, 93, and the voltage across the second capacitance % will become. Step S3 is that, in the third clock cycle, the first switch % is turned on and the second and third switches 95, 96 are not turned on to input the digital signal to the inverter 913, so the first capacitor 92 will It is charged until the voltage across the first capacitor % reaches AVxaj. Step S4 is that during the fourth clock cycle, the second open μ is turned on and the first and second switches 94 and 96 are not turned on, and the charges on the first and second capacitors % 93 are evenly distributed, and The voltage across the second capacitance % will become (((ΔVxa〇)/2) + (AVxai))/2. 1330003 Step S5 is that during the fifth clock cycle, the first switch 94 is turned on and the second and third switches 95, 96 are not turned on, and the digital signal a2 is input to the inverter 913, and the first capacitor 92 is It is charged until the voltage across the first capacitor 92 reaches AVxa2. Step S6 is that, in the sixth clock cycle, the second switch 95 is turned on and the first and third switches 94, 96 are not turned on, and the charges on the first and second capacitors %, 93 are evenly distributed, and The voltage across the second capacitor 93 will become (((((x()))).

Step S7 is that, in the seventh clock cycle, the first switch 94 is turned on and the second and third switches 95, 96 are not turned on, and the digital signal is input to the inverter 913, and the first capacitor 92 is Charging until the voltage across the first capacitor 92 reaches ΔVX a3. Step S8 is that, in the eighth clock cycle, the second switch % is turned on and the first and third switches 94, 96 are not turned on, and the first and second capacitors are %.

The charge on 93 will be evenly distributed, and the voltage across the second capacitor 93 will become (((((((((((((((((((((((((((((((((((((((( (ai/8)+(aG/ 丨6)) χ △ v. Therefore, every input-bit to the conventional digital analog converter 9 requires a charge of the first capacitor 92 And the step of equally distributing the charge of the first and second capacitors 92, 93, that is, the input - one bit takes two clock cycles to complete processing. In the foregoing example, the digit position signal is input. If there are 4 bits, then 8 (= 4 χ 2) clock cycles are needed to process. Therefore, when the input digit signal has a clamp ^, the processing time needs ΝΧ 2 clock cycles, and when the number of Ν becomes larger ,needed

8 Time will grow in multiples. SUMMARY OF THE INVENTION An object of the present invention is to provide a digital analog conversion circuit capable of improving efficiency and an image reading and audio device including the capacitive digital analog conversion circuit. The capacitive digital analog conversion circuit of the present invention is suitable for converting a digital signal having a complex number of 7L into an analog signal, including a voltage selection unit, a first-ray, an electric I, a second capacitor, and a third Capacitor and a switching unit. D. The voltage selection unit sequentially receives the bit 7L of the digital signal with the clock cycle and generates a corresponding voltage according to the value of the received bit. The first capacitor disk 筮-f+ 0 /, a voltage valley according to the clock cycle, is alternately charged by the voltage selected by the voltage 7L earlier and the difference between the reference voltages. The third capacitor is capable of performing charge distribution according to the clock period ' and the first capacitor or = first valley that is not in the state of charge. When the conversion program is completed, the voltage across the third capacitor is the analog signal. During the clock cycle, the switching unit charges the first capacitor by the voltage generated by the voltage k and the difference between the reference voltages, and the third capacitor is not electrically connected to the first capacitor. The switching unit charges the second capacitor by a voltage generated by the voltage selecting unit and a difference between the reference voltages during a second clock cycle. And electrically connecting the first capacitor to the third capacitor in parallel, thereby redistributing the charge on the first capacitor and the third capacitor. During a third clock cycle, the switching unit charges the first capacitor by the voltage generated by the 1330003 voltage selection unit and the difference between the reference voltages. And electrically connecting the second capacitor in parallel with the third capacitor, thereby redistributing the charge on the second capacitor and the third capacitor. The image device of the present invention is adapted to receive image data in a digital form and includes a driving unit and a signal output unit.

The drive unit includes the above-described capacitive digital analog conversion circuit. The capacitive digital analog conversion circuit receives the digital image data and converts it into an analog image signal. The signal output unit is electrically connected to the driving unit and can receive and transmit the analog image signal. The audio device of the present invention is suitable for receiving sound data in a digital form and includes a signal processing unit and a sound output unit. The signal processing unit includes the above-described capacitive digital analog conversion circuit, and the electric valley digital analog conversion circuit receives the sound data of the digital form and converts it into an analog sound signal.

The sound output unit is electrically coupled to the signal processing unit to receive and play the analog form of the sound signal. The monthly digital analog analog conversion circuit and the image device and audio device have caused three capacitors to take turns to receive data and charge sharing processing. When standing: When a capacitor is used as a data input, the other two capacitors are equally distributed at the same time. Therefore, it is possible to improve the efficiency and achieve the efficacy [embodiment], features and effects of the present invention, and in the detailed description of the two preferred embodiments of the present invention with reference to the above-mentioned and other technical contents 10 1330003 of the present invention. Can be clearly presented. Referring to FIG. 2, the capacitive digital analog conversion circuit of the present invention is suitable for converting a serial digital signal [dN of .2. d丨d〇] having N bits into an analog signal, and the serial digital signal is The least significant bit dQ begins to receive 'and then sequentially receives the higher bit until the most significant bit is received'. The first preferred embodiment of the capacitive digital analog conversion circuit of the present invention comprises a voltage selecting unit i, a switching unit 3, a first capacitor 21, a second capacitor 22 and a third capacitor 23. The voltage selection unit i includes a reverse Μ 13, a first path switch 14, a second path switch 15, a first selector u and a second selector 12. In the first preferred embodiment, the inverter 13 is a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor), and can receive the digital signal and generate an inverted output. The first and second selectors 11, 12 are. The two ends of the first path switch 14 are electrically connected to the inverter 13 and the first selector 11 respectively, and the two ends of the second path switch 15 are electrically connected to the inverter 13 and the second selector 12, respectively. . The first and second path switches 14, 15 respectively determine whether or not to cause the output signal of the inverter 13 to enter the first and second selectors 11, 12. The first selector 11 receives a minimum voltage VI and a highest voltage Vh. When the first path switch 14 is turned on, when inputting to the reverse

11 1330003 The digital signal of the device 13 is! The output signal of the inverter i3 will cause the first selector 11 to generate an output value equal to the highest voltage Vh, and the difference of the lowest voltage V1 is the input to the opposite When the digital signal to the thief 13 is 〇, the output signal of the reverse _ 13 will cause the first selector U to generate an output value equal to the lowest voltage νι, and its difference from the lowest voltage VI is zero. . The operation of the second selector 12 is the same as that of the first selector u, and therefore will not be described herein. The switch unit 3 includes a first charging switch 31, a second charging switch 32, a first voltage equalizing switch 33, a second voltage equalizing switch 34, and a reset switch 35. The first charging switch 3 i , the first equalizing switch 33 , the second equalizing switch 34 and the second charging switch 32 are serially connected in series, and are located at the first and second selectors u of the voltage selecting unit 1 , Between 12. One end of the reset switch 35 is electrically connected between the first equalizing switch 33 and the second equalizing switch 34, and the other end is electrically connected to the lowest voltage v1. • It is also worth noting that the reset switch 35 is only turned on during the first clock cycle at which data reception begins, and then is in a non-conducting state. The first path switch 14, the first charging switch 3 and the second equalizing switch 34 are turned on together, and the second path switch 15, the second charging switch 32 and the first equalizing switch 33 are together Turn on. Wherein, when the first charging switch 31 is turned on, the second charging switch 32 is not turned on. One end of the first capacitor 21 is electrically connected between the first charging switch 31 and the first voltage equalizing switch 33, and the other end is electrically connected to the lowest voltage VI». One end of the second capacitor 22 is electrically connected to The second charging switch 32

12 1330003 and the second equalization switch 34, and the other end is electrically connected to the minimum voltage VI. The second valley 23 is electrically connected in parallel with the reset switch 35, and the voltage across the second capacitor 23 is the generated analog signal. In the first preferred embodiment, the capacitance values of the first, second, and third capacitors 21, 22, and 23 are the same. When the first charging switch 31 is turned on and the first equalizing voltage 33 switch is not turned on, the first capacitor 21 is charged by the voltage difference between the output of the first selector u and the lowest voltage vi. When the first charging switch 31, the second equalizing switch 34 and the reset switch 35 are not conducting, and the first equalizing switch 33 is turned on, the first and third capacitors 21, 23 are electrically connected in parallel, and thus the The charges on the first and third capacitors 21, 23 are evenly distributed. When the second charging switch 32 is turned on and the second voltage equalizing switch 34 is not turned on, the second capacitor 22 is charged by the voltage difference between the output of the second selector 12 and the lowest voltage V1. When the second charging switch 32, the first equalizing switch 33 and the reset switch 35 are not conducting, and the second equalizing switch 34 is turned on, the second and third capacitors 22, 23 are electrically connected in parallel, and thus the The charges on the second and third capacitors 22, 23 are evenly distributed. If it is assumed that the serial digital signal to be processed is 4 bits, it is [c^cbdido] 'The program of converting the digital signal into an analog signal by the capacitive digital analog conversion circuit of the present invention comprises the following steps: Refer to FIG. 2 and FIG. 3, step S1 is a first clock cycle, the first path switch 14, the first charging switch 3 1 , the second equalizing switch 34 and the reset switch 35 are all turned on, and the second path switch 15. When the first equalizing switch 33 and the first charging switch 32 are both non-conducting, the digital signal d〇 is input to the inverter 13', and the first capacitor 21 is charged until the

13 1330003 The voltage across the first capacitor 21 reaches Δγχ d〇, and the second and third capacitors 22, 23 are reset. Referring to FIG. 2 and FIG. 4, step S2 is a non-conduction of the first path switch 14, the first charging switch 31, the second equalizing switch 34, and the reset switch 35 during a second clock cycle. When the second path switch 15, the first equalizing switch 33, and the second charging switch 32 are both turned on, the digital signal mountain is input to the inverter 13, and the second capacitor 22 is charged until the second electric valley 22 cross pressure reached av xd〗. At the same time, the charges on the first and third capacitors 21, 23 are evenly distributed, and the voltage across the third capacitor 23 will become (ΔVxd 〇)/2. Referring to FIG. 2 and FIG. 5, step S3 is a third clock cycle, in which the first path switch 14, the first charging switch 31 and the second equalizing switch 34 are both turned on, and the second path switch 15, When the first equalizing switch 33, the second charging switch 32, and the reset switch 35 are both non-conducting, the digital signal i is input to the inverter 13, and the first capacitor 21 is charged until the first capacitor 21 The cross pressure reaches AVxd2. At the same time, the charges on the second and third capacitors 22, 23 are evenly distributed, and the voltage across the third capacitor 23 will become ((AVxd〇) / 2+ (AVx mountain))/2. Referring to FIG. 2 and FIG. 4, step S4 is that during the fourth clock cycle, the first path switch 14, the first charging switch 31, the second equalizing switch 34, and the reset switch 35 are not turned on, and When the second path switch 15, the first equalizing switch 33, and the second charging switch 32 are both turned on, the digital signal d3 is input to the inverter 13, and the second capacitor 22 is charged until the second capacitor 22 The cross pressure reaches AVxd3. At the same time, the charges on the first and third capacitors 21, 14 1330003 23 are evenly distributed, and the voltage across the third capacitor 23 will become (((Δ VX d〇) / 2 + ( AVX Mountain)) / 2 +( ΔV X d2))/2.

Referring to FIG. 2 and FIG. 5, step S5 is that during the fifth clock cycle, the first path switch 14, the first charging switch 3 1 and the second equalizing switch 34 are both turned on, and the second path switch is turned on. 15. When the first equalizing switch 33, the second charging switch 32, and the reset switch 35 are both non-conducting, the charges on the second and third capacitors 22, 23 are evenly distributed, and the third capacitor 2; The upper cross pressure will become (((ΔVxdM+MVxdWQ+MVxdaa+MVxd)))/, and this formula can be organized into ((1/2)+((12/4)+((^/8)) +((10/16)0 Δν. Therefore, the first preferred embodiment uses three capacitors in turn for receiving data and charge sharing processing. When one of the capacitors is used as data input, the other two electric valleys are simultaneously performed. The charge distribution is evenly distributed, and the circuit resource 0 can be fully utilized. It takes 5 clock cycles, which can be in the first preferred embodiment.

The input digits signal with 4 digits and 7 turns is converted into the analog signal. Similarly, when the field input digit apostrophe has a Ν bit, it only needs ν+ι clock cycles to process. In contrast, the conventional digital analog converter 9 requires 2XN clock cycles to be completed, which is quite time-inefficient. It should be noted that in the embodiment of the flute __ _ 苐 杈 杈, the first, the first way switch 14 , 15 , a 士 α * can be omitted and the output signal of the inverter 13 is directly sent In the preferred embodiment of the first and second selectors 11, 12 〇 second tr, the reset switch 35 can be omitted. And the switches u, 15, 31, 32, 33, 34, 35 of the first preferred embodiment

15 1330003 can use a complementary switch that wakes OS, PMOS or NM〇s combined with pM〇s, and is not limited to the above. Referring to FIG. 6 , a second preferred embodiment of the electric valley type digital analog conversion circuit of the present invention includes a voltage selecting unit 44, a switching unit 45, a first electric valley 41, a second capacitor 42 and a third capacitor. 43. The voltage selection unit 44 includes an inverter 441 and a selector material 2. The switch unit 45 includes a changeover switch 453, a -th voltage equalization switch 451, a second voltage equalization switch 452, and a reset switch 454. The end of the switch 453 is electrically connected to the output of the selector 442, and the other end is switchably electrically connected to the first capacitor 41 or the second capacitor 42. Therefore, when the 4-bit serial digital signal is input The switching of the switching unit 45 and the operation of the capacitors 41, 42, and U are as follows: During the first clock cycle, the switching switch 453 electrically connects the selector 442 and the first capacitor 41, and The two-way switch 452 and the reset switch • 454 are all turned on. The first-level equalization switch 451 is not turned on. Therefore, the first capacitor 41 is charged, and the second and third capacitors 42, 43 are reset. During the first clock cycle, the switch 453 electrically connects the selector 442 and the first valley 42 and the second voltage equalization switch 452 and the reset switch 454 are not conducting, and the first voltage equalization switch 451 is on. Therefore, the second capacitor 42 is charged' and the charge on the first and third capacitors is evenly distributed. During the second clock cycle, the switch 453 will electrically connect the selector 442 and the first valley 41 and the first voltage equalization switch 451 and the reset switch 16 1330003 454 will not be turned on, and the 41 will be charged. , assigned. • , a capacitor and the charge on the second and third capacitors 42, 43 will average over the fourth clock cycle, repeating the steps in the second clock cycle and during the fifth clock cycle' Repeating the steps in the third clock cycle, the process of converting the digital signal into an analog signal can be completed. which is

Referring to Fig. 7, the image data of the digital device of the present invention includes a unit 52' and a display unit 53. A preferred embodiment is applicable to the receiving driving unit 51, and a signal output. The driving unit 51 includes a capacitive digital analog converting power 27W according to the above-described embodiment, and the capacitive digital analog converting circuit 511 can receive The digital form of the image data is converted into an analog image signal.

The signal output unit 52 is electrically connected to the driving unit 51, and can receive the analog image signal and transmit it to the display unit brother. The display unit 53 is electrically coupled to the signal output unit 52 and displays the analog image signal. The image device of the present invention can be a display, and is not limited thereto. In addition, the display device 53 of the present invention can omit the display unit 53 and can be a display card or a digital video disc (DVD) player, and is not limited thereto. Referring to Figure 8, a preferred embodiment of the audio device of the present invention is adapted to receive a digital form of sound data, including a signal processing unit 61 and a sound output unit 62.

17 l33〇〇03 The signal processing unit 6A includes a capacitive digital analog conversion circuit 611 according to one of the above embodiments, and the capacitive digital analog conversion circuit 611 can receive the sound data in the digital form and Converted into an analog-like form of sound signal. The sound output unit 62 is electrically coupled to the signal processing unit 61 and is capable of receiving and playing the analog form of the sound signal. The audio device of the present invention can be an audio, an animation compression standard _ 丨 standard audio layer 3 (M〇ti〇n Picture Experts ~ Qing] Audi 〇 [ah 3, # MP3) player, a compact disc (Compact Disc, referred to as CD) player, a digital video disc player and a keyboard are not limited to this. In summary, the capacitive digital analog conversion circuit, the image device and the audio device of the present invention can make the capacitor process data in a time-sharing and multi-work manner, and do not have an idle problem, thereby achieving an efficient (four) lag signal, so it is possible to achieve this. The purpose of the invention. However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent change of the patent application scope and the description of the invention is Modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a conventional conventional digital analog converter; FIG. 2 is a circuit diagram of a first preferred embodiment of a capacitive digital analog conversion circuit of the present invention; FIG. 3 is a preferred embodiment of the present invention. A partial circuit diagram 'describes the first capacitor charging, and resets a second capacitor and a third capacitor; 18 1330003. FIG. 4 is a partial circuit diagram of the preferred embodiment, illustrating charging the second capacitor, and the The first and third capacitors perform charge sharing; FIG. 5 is a partial circuit diagram of the preferred embodiment, illustrating the capacitor charging and the second and third capacitors for charge sharing; FIG. 6 is a capacitive digital bit of the present invention; Analog conversion circuit _

Figure 7 is a block diagram of a preferred embodiment of an image device of the present invention; and Figure 8 is a block diagram of a preferred embodiment of the audio device of the present invention.

19 1330003

[Description of main component symbols] 1...... ..... voltage selection unit 441 .... reverser 11 ..... ... first selector 442 .... selector 12 ... Two selectors 45......... Switching unit 13...···...inverter 451 ....... first equalizing switch 14··...•...first path switch 452 ....... Second equalizing switch 15•.... •...Second path switch 453 ....... Switching switch 21 ••... •..., capacitor 454 ....... Set switch 22.........second capacitor 51......... Drive unit 23•....•...third capacitor 511 ....... Capacitive digital analogy 3... •...switch unit Conversion circuit 31.........first charging switch 52.........signal output unit 32.....the second charging switch 53.........display unit 33· ···· •...1st voltage equalizing switch 61......... Signal processing unit 34.....•...Second voltage equalizing switch 611 .... Capacitive digital analogy 35 ......•...Reset switch conversion circuit 41 ·..··•...first capacitor 62......sound output unit 42·..··•...second capacitor VDD ..... External voltage 43 ...·. •... Third capacitor Vh........ Maximum voltage 44••... •...Voltage selection unit VI......... Lowest voltage < 5 ^ 20

Claims (1)

1330003 X. Patent application scope: Applicable to converting a capacitive digital analog conversion circuit with a complex digital position. The digital digital signal is converted into an analog signal. The circuit includes: a first capacitor, a second capacitor, the voltage generated by the voltage selection unit and a clock cycle according to the difference between the reference voltages - the second capacitor 'according to the clock cycle, and not in the state of charge The first capacitor or the second capacitor performs charge distribution. When the conversion process is completed, the crossover on the third capacitor is the analog signal; and when the switching unit is in the -first-clock cycle, the switching unit makes The first capacitor is charged by the voltage generated by the voltage selection unit and the difference between the reference voltages _§_ such that the third capacitor is not electrically connected to the first capacitor; during a second clock cycle, the switch The unit causes the second capacitor to be charged by the voltage generated by the voltage and the reference voltage, and the first capacitor is electrically connected in parallel with the third capacitor, thereby making the first capacitor and the third Recharging the charge on the capacitor; during a third clock cycle, the switching unit charges the first capacitor by the voltage generated by the voltage selecting unit and the difference between the reference voltages and causes the second Receiving the third capacitor is connected electrically in parallel, so that the second capacitor 211,330,003 and the third capacitor charge redistribution. 2. According to the patent application scope flute, TS ^ ^ The capacitive digital analog conversion circuit described in item 1, the operation performed when the second and third clock cycles are repeated with the clock cycle change Until all bits of the digital signal are received. 3. According to the towel, please turn the capacitance type analog conversion circuit of the first item in the range of 'the', the capacitance values of the first, second and third capacitors are the same. The capacitive digital analog conversion circuit according to the first aspect of the invention, wherein the switch unit comprises a first equalizing switch and a second equalizing switch 'the first equalizing switch and the second The voltage equalizing switch is sequentially connected in series between the end of the first capacitor and the end of the second capacitor, and the first capacitor and the other end of the capacitor are electrically connected to the reference voltage, respectively. One end of the three capacitors is electrically connected between the first voltage equalizing switch and the second voltage equalizing switch, and the other end is electrically connected to the reference voltage. 5. The capacitive digital analog conversion circuit according to claim 4, wherein the switch unit further comprises a first charging switch and a second charging switch, the one end of the first charging switch and the voltage selecting unit Connected, and the other end is electrically connected between the first capacitor and the first voltage equalizing switch, one end of the second charging switch is electrically connected to the voltage selecting unit and the other end is electrically connected to the second capacitor and the second Between the equalizing switches 〇6. According to the patent application scope 帛5 (4), the capacitive digital analog conversion circuit, wherein the first charging switch and the second equalizing switch are turned on together, and the second charging switch and the second charging switch A voltage equalization switch will be turned on together, :S 22 1330003 and the second charging switch will not conduct when the first charging switch is turned on. 7. The capacitive digital analog conversion circuit according to claim 4, wherein the switch unit further comprises a switch, one end of the switch is electrically connected to the voltage selection unit, and the other end is switchable to ground. Connected to either of the first capacitor and the second capacitor. 8. The capacitive digital analog conversion circuit of claim 7, wherein the second voltage equalization switch is in a conducting state when the switching switch electrically connects the voltage selection unit to the first capacitor. When the switch makes the voltage selection unit electrically connected to the second capacitor, the first voltage equalization switch is in an on state. 9. The capacitive digital analog conversion circuit of claim 4, wherein the switching unit comprises a reset switch in parallel with the third capacitance. 10. The capacitive digital analog conversion circuit of the application of claim 9 wherein the reset switch is turned on only at the beginning of the first clock period in which the data is received, and the third capacitor can be reset. 11. The capacitive digital analog conversion circuit of claim 1, wherein the voltage selection unit is received by a minimum bit of the digital signal. 12. According to the scope of patent application! The capacitive digital analog conversion circuit of the present invention, wherein the voltage selection unit generates a voltage value identical to the reference voltage when the bit value of the digit signal input is 0, and when the bit value is 1 'Generate a voltage higher than the reference voltage. 13. Capacitive digital analog conversion conversion according to the scope of patent application 23 丄330003 路' wherein the voltage selection unit includes an inverter for receiving the digital signal, and a first selector for receiving an output signal of the inverter and generating an output voltage. The capacitive digital analog conversion circuit of claim 13, wherein the voltage selection unit further comprises a second selector that receives the output signal of the inverter and generates an output voltage. 15. An image device adapted to receive image data in a digital form, comprising: a drive unit comprising a capacitive digital number as claimed in any one of claims 1 to 14 An analog conversion circuit, the capacitive digital analog conversion circuit receives the digital image data and converts it into an analog image signal; and a signal output unit electrically connected to the driving unit to receive and transmit the analog form Image signal. The image device according to claim 15 further comprising: the display unit being electrically connected to the signal output unit and displaying the analog image signal. 17. The image device of claim 15 wherein the image device is a display card. 18. The image device of claim 15, wherein the image device is a digital video disc player. 19. The device of claim 16, wherein the image device is a display. 20. An audio device suitable for receiving a digital form of sound data, including 24 丄 03 03 Included: A signal processing unit 'The signal processing unit includes a capacitive digital analog conversion circuit as claimed in any one of claims 1 to 14 of the present invention, the capacitive digital analog conversion circuit Receiving the digital form of the sound data and converting it into an analog sound signal; and a sound output unit electrically connected to the signal processing unit to receive and play the analog sound signal. 21. The audio device of claim 2, wherein the audio device is an audio device. 22. The audio device of claim 2, wherein the audio device is an animation compression standard _ 丨 standard audio layer 3 player. 23. The audio device of claim 2, wherein the audio device is a compact disc player. 24. The audio device of claim 2, wherein the audio device is a digital video disc player. 25. The audio device of claim 20, wherein the audio device is a keyboard. 25