TWI278092B - Electrostatic discharge protection device and method of fabrication thereof - Google Patents

Abstract

An ESD protection device includes a first gate and a second gate formed on a first-type substrate. A plurality of second-type heavily doped regions is formed on the substrate between and on the outer sides of the first and second gates, respectively. A second-type lightly doped region is formed on the substrate between the first and second gates and includes an opening directly connect the second-type heavily doped region formed between the first and second gates to the first-type substrate.

Description

1278092 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor process, and particularly relates to a low input impedance, low junction parasitic capacitance, and high electrostatic discharge withstand capability. A deep-sub-micron CMOS process with a characteristic electrostatic discharge (ESD) protection circuit. [Prior Art] Electrostatic discharge (ESD) is a relatively large amount of potential difference or charge generated by friction between different materials, and discharges in a few to hundreds of nano-seconds according to different discharge modes. Caused. However, the most common causes of ESD stress are the following three models: human body model (HBM), machine model (MM), and charged device model (CDM). The general integrated circuit product specifications are ± 2k volts for the ESD in the HBM mode, ± 200 volts for the MM mode, and ± 1 耐受 for the CDM mode. 〇伏特. The components of the integrated circuit (1C) that first encounter the electrostatic discharge pulse are typically input and output circuits (I / 0 b u f f e ) that are directly coupled to the bonding pads or terminals of the wafer. Fig. 1A is a circuit diagram showing a conventional wheeled circuit, and Fig. 1B is a sectional view showing a semiconductor corresponding to Fig. 1A. 1/〇 bonding pad (PAD) 10 is coupled to the junction of the nm〇S transistor 1 2 A and the NM0S transistor 1 2B source/drain, and the source/drain of the NM0S transistor 12A is coupled to the power supply.

〇702-9558twf(nl) ; 91P77 ; Robeit.ptd Page 5 1278092

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The source/drain of the NMOS transistor 12B is coupled to the power supply v "TV 1^1 Μ Λ * _ _ SS v NM0S transistor 12 Α and the gate of the NM0S transistor 12 皆 are coupled to the ground ^ NM0S electricity The crystal 12A and the NMOS transistor 12B are in operation during normal circuit operation. Closed. Therefore, the NM0S transistor 12A and the NMOS transistor 12b are in the ESD protection circuit 14 nickname. When the I/〇 pad 1 〇 receives the ESD pulse, a large amount of Esβ current will pass through the NMOS transistor 12A and the NMOS transistor 12B. Released by the current path. If the integrated circuit does not have a good electrostatic discharge protection circuit, the above-mentioned large amount of ESD current can easily cause damage to the oxide layer of the 0S transistor 12A and the problem (10) transistor 12β, or the ESD current concentrates on the NM〇s transistor. The drain region with the NM0S transistor 12B is near the surface of the most fragile channel region and burns out a specific region of the channel region. When the gate is damaged or a certain area of the channel area burns out, the integrated circuit will not operate smoothly. With the advancement of semiconductor process technology, the tolerance of ESD has become one of the main considerations for the reliability of integrated circuits. Especially when semiconductor process technology enters the sub-quarter-mi cron, scaled-down transistors, shallow doped junction depth, thin gate oxide, light doping The 汲 结构 structure (1 ight ly-d〇 ped dra in, LDD), the shallow trench isolation (STI) process, and the metal salide process are all compared for ESD tolerance. Fragile. Therefore, the output input circuit of I C must specifically design the ESD protection circuit to protect the components in 1C from ESD damage.

1278092 V. Description of invention (3) ESD protection circuit 1 Φ 夕#丘,处w, )俜 used to capture 1 λ Hungarian clothing (NM〇S transistor 1 2Α, 1 2Β) is used to protect the interior Circuit] 6 is free from esd. The source of the NM0S transistor 12A is coupled to the 1/〇 pad, the weight 八' is connected to the V potential and the 7 fen 〇塾 1 0 ', and its light is not connected to the % potential and the gate is coupled to the ground. The drain is coupled to the [/〇 bond pad 1〇, the electric day body is 12Β 3L i U and the source is connected to the $丨丨V Φ bit. The 0S transistor coupled to the 1s/〇 bond pad 1〇W is coupled to the Vss transistor. The transistor can be electrically connected to the gate oxide layer, and the ESD current flow point is avoided to avoid internal Integrated circuit; [6 is affected by ESD, ^ ^ Η, I phase is bad. Since the ESD protection capability is mainly determined by the ESD tolerance of the clamping device, it is traditionally advantageous to clamp the 布 mass near the 胄i to improve the e-capability of the clamping device. Also, Fig. 2A shows a cross-sectional view of a conventional ES]) protective device having an ESD planting area, and Fig. 2B shows a conventional process flow chart for forming a "protective device" shown in Fig. 2A. 2A and 2B, first, gate oxide layers 214 and 216 (S1) are formed on p-type region 20, and then lightly doped regions 22A and 22B and sidewall insulating spacers 23A and 23B are sequentially formed. And the source/drain region 24Λ~24C (S2~S4). Then, the ESD photoresist mask is formed, and the screen is formed at the bottom of the source/> and the polar region 2 4 A~2 4 C and its surroundings. £ g ρ is implanted with £25A~25C (S5). Finally, the relevant subsequent process (sg) is performed, for example, metal telluride is formed on the surface of source/drain regions 24A to 24C. Self-aligned metal telluride process can be utilized. (sa 1 ici de) depositing a metal layer to form a metal telluride, wherein the metal layer is generally composed of a refractory material, for example

IBS 0702-9558twf(nl) ; 91P77 ; Robert.ptd Page 7 1278092 V. INSTRUCTIONS (4) Platinum (P t ), beginning (C 〇) and titanium (T i) 'Take metal titanium as an example, which can Forming by physical vapor deposition (PVD) or chemical vapor deposition (CVD), for example, depositing a layer of a metal (Ti) layer by means of a magnetic mine, such as magnetron DC sputtering. 'Anneaing is then performed, such as Rapid Thermal Processing, to form a metallic lithium interface. U.S. Patent No. N0·5 5 5 9 3 5 2, Hsue discloses a method of forming an esD guard device that performs a high energy implant through a contact window of a dipole and a source to form a P-type ESD implant region' and The pole constitutes a base inductor to reduce the junction voltage of the junction. Therefore, by reducing the triggering of the ink, the Egd protection 丨_ circuit can be turned on quickly to prevent the thin gate oxide layer from being damaged by the ESD current and improving the ESD withstand capability.

U.S. Patent No. N. 5 9 5 36 0 1. Shiue proposes a method for reducing the breakdown voltage of the extreme junction of the ES protection device, which is turned on before the voltage of the gate oxide ruin collapses. This conventional method is performed by performing a deuteration reaction: a deep ion implantation region having |^ impurity (P type) is formed directly under the source/drain n of the ESD protection device to reduce the back pressure of the drain junction. Furthermore, it avoids the problem of increased resistance of the self-aligned metal deuterated layer caused by ion transfer when performing high-energy ESD implantation. 1 Ding Wang also entertained a form of ESD protection US patent number NO · 6 1 1 42 26, Chang proposed

1278092, invention description (5) ° < method, using a photoresist mask to cover the internal circuit and part of ESD defense, Zhuang®

々The metal enamel layer of the thin clothes. The metal deuterated layer is not covered by the photoresist mask, and will be peeled off by performing a dry etching process to expose the conductive layer and the portion: the non-polar region. Next, an ion implantation process (Gina junction) is performed through the photoresist mask without covering the photoresist mask to form a concentrated P-type doping (4). Next, an additional ESD photoresist mask is used to implant and limit the range of lightly d〇Ped drain (LDD) structures. In this technique, a concentrated P-type ESD planting zone formed by high energy is located below the knives, = and the drains to form a Zener diode, thereby reducing the junction voltage. Correspondingly, by lowering the trigger voltage, it is possible to prevent the thin-gate oxide layer from being damaged and improve the ESD tolerance. However, the shortcomings of various implementations of the ESD implantation process disclosed by the conventional techniques mentioned above are that the leakage current of the Zener diode formed by the direct % :, 甘 ^ ^, ... will be greater than that without the ESD implantation. The leakage of the junction, the six and ^ ^ ^ back moxibustion leakage motor, the sub-hay has a lower noise tolerance. The empty area of the Jina diode is thinner than that of the empty area of the implanted junction, and therefore has a large parasitic capacitance. In addition, 'use 焉 low pressure hill cross-ci_ M ^ use lower level of fall;; road, its core logic system> ^ #一+ ^ ” 乍 power supply and output wheel input area is generally compared to the power supply The voltage level of 咼. F SD p can be reduced to about 5 hearts: The voltage of the Kina junction collapses by 4 inches. However, in the use of high and low voltage, the total volume of electricity is 电 ί ^ Ση' is not expected to be a noise or overshooting. *The ESD protection device is turned on during normal normal operation, thus causing

Page 9 1278092 V. Description of invention (6) Function failure. In addition, since the value of the parasitic capacitance is proportional, the width of the depletion region where the junction of the Kina is thin is connected to the parasitic capacitance of iiii. * The circuit operates at high speed τ, and the esd guard connected to the ι/〇 = Cannes junction will extend the rise of the signal. Therefore, the ESD protection device disclosed in the conventional art is not suitable for the circuit of the south speed operation. [Summary of the Invention]

In view of the above, in order to solve the above problems, the main object of the present invention is to provide an electrostatic discharge protection structure and a manufacturing method thereof, which can form a low power=electricity: a relief voltage drop, good noise tolerance, and high ESD talent. ESD protection device for high speed operation and high and low voltage common structure. In order to achieve the above object, the present invention proposes a deep micron (deep-sub-micr〇n) cm〇s binary that significantly enhances the ESD tolerance of the CMOS product. According to the method disclosed by the present invention, the distribution area of the ESD implantation area is 糸, and the entire area except the drain contact area in the entire drain region is different from the conventional structure. Further, the method of chromium according to the embodiment of the present invention is not the same as the conventional operation flow shown in Fig. 2. First, prior to forming the sidewall insulating spacers, the ESD implant mask is defined by the ESD photoresist mask, and then the N-type ions are implanted in the lower region of the entire drain region except for the drain contact region. To form a cover

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Page 10 1278092 V. Description of invention (7)

ESI) implant area of lightly doped drain (LDD) structure. When the ESI) guard has a larger discharge area, it has a higher ESD tolerance. Therefore, the ESD protection device provided by the invention has the advantage of reducing the area of the ESD in the drain region near the surface of the weak channel and forcing the ESD to be discharged via the region at the bottom plane of the drain. again

The ESD protection devices provided by Ming are compatible with deep sub-micron (de S) CMOS processes, while in the E formed at the same time: the circuit can significantly reduce the process cost. In addition, although the above-mentioned skirting and inner pole area are exposed, various types (4) are implanted in the protective device to reduce the breakdown voltage to increase the leakage current of the coffee and the low impurity; the In front of the ESD planting area - Hu Guxin. Furthermore, it is thinner than the unformed transmission, so that the vacant area with the stagnation area of the kinetic junction is compatible with the body 4, which is two: two; Furthermore, use high and low voltage input capacitors, good noise = = whether the protection circuit has low, based on the above reasons, the characteristics of the US and ^ Ε δ Ι tolerance. ESD protection, jujube, or excessive glitch due to tolerance will result in unpredictable low breakdown voltage and low noise. (〇vershooting circuit missing signal or function W is unexpectedly turned on during normal operation. , resulting in an integrated circuit. Conversely, j is therefore not suitable for use with a high and low voltage common containment circuit, its collapse voltage disk | ESD protection according to embodiments of the present invention is not different. Therefore, the board according to the present invention The junction breakdown voltage has high noise tolerance to avoid the $f-only ESD deployment method disclosed in the example and avoids the operation of the internal circuit.

1278092

The impact of news or overshooting. Furthermore, another advantage of the ESD implantation method disclosed in accordance with embodiments of the present invention is that the junction capacitance of the transistor of the conventional Es protection device can be reduced because the voltage of the crash* is not changed. In addition, the ESD protection device disclosed in the embodiment of the present invention has been successfully applied to the 0. 25-CMOS process to form a gate-grounded MOS transistor (gate-grounded NMOS, ggNMOS) and a stacked vertical NMOS (stack NMOS). ) and significantly improve ESD tolerance, especially mechanical mode ESD tolerance. According to the ESD protection device disclosed in the embodiments of the invention, the low parasitic capacitance, the unbroken breakdown voltage, the good noise 4 tolerance, and the excellent ESD tolerance are suitable for the high-speed and high-low voltage common-capacity integrated circuits. Output input circuit. [Embodiment] Embodiment: A third embodiment of the present invention is a cross-sectional view showing a manufacturing method of a protective device according to an embodiment of the present invention, and an ESD anti-skinning device according to an embodiment of the present invention. It is applied to the Zhu submicron c Μ 0 S process. In this finger-like structure, the ESD protection device 30 and the internal circuit 40 are simultaneously formed on a substrate 50 such as a lithography process, an ion implantation process, an oxidation process, and a remnant process in a conventional process. First, a p-type well region 52 and an isolation structure 5 1 are sequentially formed on the crucible base 50 to separate the E S D guard 3 〇 from the internal circuit 4 〇. The isolation structure 5 1 can be formed by a conventional technique of 1 〇 c a 1丨z e ^ oxidation of si 1 icon (LOCOS ) or a shallow trench isolation process. And the m〇S transistor includes a gate

0702-9558twf(nl) ; 91P77 ; Robert.ptd Page 12 1278092 V. INSTRUCTIONS (9) Oxidation insulating layer 5 3 , polysilicon gate 5 4 , lightly doped gate structure 5 7 , E SD planting area 6 0. The sidewall insulating spacers 62 and the source/drain regions are formed as follows. The gate oxide insulating layer 53 is formed by thermal growth in an oxygen supply system having a thickness of about 1 Å or less. Next, an ion implantation process for adjusting the threshold voltage is performed and a polycrystalline layer is deposited by a low pressure chemical vapor depos i on (LPCVD) to form a gate. 3B to 3E show the steps of forming a lightly doped gate structure. First, referring to FIG. 3B, a photoresist layer 55 is formed on the surface of the substrate 5 to cover the surface of the solder isolation structure 51, the P-type well region 52, and the gate 54, and then a photomask 56A is used to define the photoresist region. The isolation pattern is formed (as shown in Figure 5%). The remaining photoresist layer is indicated by reference numeral 55A. Next, referring to the 3D drawing, the gate 54 and the photoresist layer 55A are used as masks, ion implantation is performed to form a lightly doped drain (LDD) 57, and finally the photoresist 55A is removed (eg, 3E). Figure shows). After forming the lightly doped gate 57, as shown in FIG. 3f, a photoresist layer 58 is formed on the surface of the substrate 50 again to cover the surface of the isolation structure 5, the impurity drain 5, and the surface of the idle electrode 54. Using the photomask 56β having a predetermined ESD implantation pattern according to the present invention, in addition to the photoresist located on the ESD protection device 30 corresponding to the position of the ESD implantation pattern, the remaining photoresist is Reference numeral 58A is indicated (as shown in the figure). Next, refer to Figure 3H, with the gate 54 and the photoresist 58A as the cover.

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Curtain, a light N-type ESD implantation process is performed to form an ESD implant region 60 covering the lightly doped drain 57 and the predetermined drain region on the ESD guard 30, and finally removing the photoresist 58A (as in Figure 31) Show). Next, an inner dielectric layer (ILD) 61 is formed on the surface of the entire substrate 50 by chemical vapor deposition (CVD) (as shown in FIG. 3J), and then the inner dielectric layer is further formed. 6 1 Perform an anisotropic reactive ion etch (RIE) step to form sidewall insulating spacers 6 2 on the sidewalls of each of the gates 54 (as shown in FIG. 3K). Next, referring to FIG. 3 l, a photoresist layer 63 is formed on the entire surface of the substrate 50, and then a photomask is used to define an isolation pattern (as shown in FIG. 3M). The photoresist is indicated by reference numeral 63 A. Next, referring to FIG. 3n, a high-dose arsenic or phosphorus ion implantation process is performed with the gate 54, the sidewall insulating spacer 62, and the photoresist 63A as a mask to form a source/drain doping region 64, and finally Remove the photoresist 6 3A (as shown in Figure 30). Subsequent related processes, such as forming a metallization on the gate structure and the surface of the source/drain region, and a metal wiring process, are the same as the conventional techniques, and are not described here to simplify the description. Therefore, the method of manufacturing the guard according to the embodiment of the present invention is completed. It is important to note that the range of the ESD implant area 60 does not include the bottom of the metal halide (and the contact area) corresponding to the gate 54 located at the ESD guard 3, the source 'and> and the surface of the pole. The area.

1278092 V. INSTRUCTION DESCRIPTION (11) ' ^ ---- Figure 4A shows an upper view of an ESD protection device formed by an ES]) protective device manufacturing method according to an embodiment of the present invention, and a 4β figure display The semiconductor cross-sectional view along line A A' in the 4Aq diagram is the ESD guard 30 shown in the third diagram. Shown here is a gate-grounded NMOS (ggNM〇s) structure. As shown in FIG. 4A ® , the ESD implant region 70 is surrounded by an area outside the area indicated by the reference numeral s (the drain contact area) and between the gates 72. Referring to Fig. 4B, the ESD planting area 70 is located near the bottom of the non-polar region 74 between the gates 7 2, and does not include the area marked by the symbol S. Fig. 5A is a top view showing an ESD protection device formed by another method of manufacturing an ESD protection device according to an embodiment of the present invention, and the fifth β-picture shows a semiconductor sectional view taken along line BB' in Fig. 5A. 5A and 5β: the stacked NM0S structure is manufactured in the same manner as the conventional technology. However, as shown in FIG. 5A, the ESD planting area 80 is surrounded by the area indicated by the symbol s j > Outside the contact zone) and between the gates 82A and 84A. Referring to Fig. 5B', the ESD planting zone 8 is located near the bottom of the bungee zone 85 between the gates 82A and 84A, and does not include the area indicated by the symbol §.

The ESD protection device formed by the method for manufacturing an ESD protection device according to the embodiment of the present invention, for improving the ESD tolerance of the NMOS transistor, is formed on the bungee by a light N-type ion implantation process. A portion of the region below the region has a lower doping concentration than the N-type source/drain region. The ions implanted in the ESD plant can use arsenic or phosphorus ions as dopants and

1278092

Ion implantation by the source energy of the source/bungee planting

The planting area is located between the gates and the area indicated by the ESD. Furthermore, the 2 = :: square, but not including the label 5, which is covered by the light N-type implanted area, is known to have been destroyed due to the collapse of the P-type base junction. The collapse of the bungee region covered by the N-type implanted area is less than the collapse voltage of the bungee region that is not covered by the light N-type implanted area. The ESD stress of the NM〇s transistor of the ESD protection device according to the embodiment of the present invention is received when the positive ESD voltage is supplied to the 1/() bonding pad with respect to one of the Vss bonding pads. Since the breakdown voltage of the non-polar region and the P-type substrate junction not covered by the light n-type implant region does not change, the E sd current is first discharged through the junction and generates a side for rapidly triggering the parasitic circuit of the transistor. The substrate current to the bipolar junction transistor (lateral η-pn BJT). Finally, the ESD current is discharged through the parasitic lateral bipolar junction transistor of the NM0S transistor, where the discharge path of the E S D current is far from the fragile surface path of the NM0S transistor and is discharged through a large area. Therefore, the ESD stress tolerance that the NM0S transistor can withstand is greatly improved, especially the ESD response capability of the mechanical model mode. In addition, the method for manufacturing an ESD protection device according to the embodiment of the present invention has been successfully demonstrated to be applicable to a 0.25 //m CMOS process. Further, the ESD anti-corrosion manufacturing method according to the present invention can be applied to the formation of a PMOS transistor in addition to the ESD anti-compliant device which can be used to form an NMOS transistor structure. When forming an ESD protection device with a PM〇S transistor structure, the process is substantially the same as the previously described process, and the difference is poor.

0702-9558twf(nl) ; 91P77 ; Robert.ptd Page 16 1278092 V. Description of invention ~(13) "~"""""""""'" It is only to switch the implantation of P-type impurities and !-type impurities. Furthermore, the ESD implantation method according to the present invention can be applied to a stacked NM〇s structure, which has been widely applied to an output input circuit of high and low voltage common capacitance. The top view and the cross-sectional view of the NMOS structure and the stacked NMOS structure formed in accordance with the process disclosed in the present invention have been shown in Figures 4A, 4B, 5A, and 5B, respectively. As described above, the high-voltage and low-voltage integrated circuit uses a lower-level operating power supply in the core logic area, and the power received in the output input area is generally at a higher voltage level. Although the junction of the NM〇s transistor covered by the ESD implantation area is a structure with a high breakdown voltage, the breakdown voltage and noise tolerance of the area not covered by the E S D implantation area are not changed. Therefore, according to the present invention, it is possible to effectively solve the problem that the eSd guard is turned on during normal operation due to unpredictable noise or excessive severing.

In addition, since the junction parasitic capacitance value is inversely proportional to the width of the junction area of the transistor of the ESD protection device, according to the Ε 防护 D protection device of the present invention, the width of the junction of the vacant region of the MOS transistor does not change. Therefore, the parasitic capacitance of the ESD protection device according to the present invention is much smaller than that of the conventional ESD protection device having the junction of the prior art described in the prior art. Therefore, under the south speed operation of the circuit, the ESD protection device according to the present invention has low input impedance when it is connected to the input or output junction, and therefore does not prolong the rise or fall time of the signal, so it is suitable for high speed. The circuit of operation.

0702-9558twf(nl); 91P77; Robert.ptd Page 17 1298092 V. INSTRUCTIONS (14) The present invention has been disclosed in the preferred embodiments as described above, but is not intended to limit the scope of the present invention. The scope of protection of the present invention is defined by the scope of the appended claims.

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In order to make the above-mentioned preferred embodiment of the present invention, the following four-dimensional sign and advantages can be more clearly understood, and in conjunction with the drawings, a detailed description is shown in FIG. 1A showing a conventional input circuit. Circuit diagram. Fig. 1B shows a semiconductor cross section corresponding to Fig. 2A showing a conventional and right picture. 1 Find and die the cutaway diagram of the ESD protection device with the ESD planting area. Fig. 2B shows a conventional flow chart for forming an ESD process shown in Fig. 2A. Bite i

3A through 30 are cross-sectional views showing a method of manufacturing an esD guard according to an embodiment of the present invention. The Fig. 4A is a top view showing an ESD guard formed by the method of manufacturing an ESD guard according to an embodiment of the present invention. Figure 4B shows a cross-sectional view of the conductor along the line A A in Figure 4A. Fig. 5A is a top view showing an ESD guard formed by another method of manufacturing an ESD protection device according to an embodiment of the present invention. Figure 5B shows a cross-sectional view of the semiconductor along line BB in Figure 5A. DESCRIPTION OF SYMBOLS: 10~I/O bonding pad; 12A, 12B~NM0S transistor; 1 4~ESD protection circuit; 16, 40~ internal circuit; 20, 50, 52~P type well area;

0702-9558twf(nl) ; 91P77 ; Robeitptd Page 19 1278092______ Schematic description 2 1 A, 2 1 B, 5 3~ gate oxide insulating layer; 22 A, 22 B, 57~ lightly doped drain structure; 2 3 A, 2 3 B, 6 2~ sidewall insulation spacers; 24A~24C, 74, 85~ source/drain regions; 25 A~25C~ESD implant areas; 26A, 26B, 54, 72, 82A, 84A ~ gate structure; 30 ~ ESD protection device; 51 ~ isolation structure; 56A, 56B, 56C ~ mask; 55, 55A, 58, 58A, 63, 63A ~ photoresist layer; 61 ~ inner dielectric layer; 0, 7 0, 8 0~ESD planting area; S~ ESD-free planting area at the bottom of the contactless zone;

Vdd, V% ~ power supply.

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Claims (1)

1278092 SS_ 92115944 VI. Application for Patent Range ^lf (w) The method for manufacturing an electrostatic discharge protection structure, comprising the steps of: providing a second gate; forming a second conductive second gate electrically connected to form a first region and powering up Forming lightly doping to perform a light second conductivity type ESD implanting region; removing the above-mentioned ^ to form a sidewall side; and performing a concentrated type and a second gate of a conductive type rich blending 2 as in the application manufacturing method, 3 If applying for a manufacturing method, the method of applying a conductive type substrate has a first gate and a first conductive type lightly doped region on the surface of the substrate, which is between the gate and the second gate And a partial region-type sad doping region between the first gate and the second gate, and exposing a second portion between the first gate and the C concealing layer that is not covered by the shielding layer a conductivity-distributing process for forming a light second conductivity type ion shielding layer in a region of the lightly doped region exposed in the substrate; and a barrier spacer on the first gate and the second gate Extremely two t ion implantation process' The above-mentioned base-shaped impurity region between the insulating spacers of the gate sidewalls. The above-mentioned first conductivity type of the electrostatic discharge protection structure described in Item 1 is P-type. The second conductivity type of the electrostatic discharge protection structure is N-type. The electrostatic discharge protection structure of the first aspect of the invention is 127,809, the amendment No. 92115944. The manufacturing method of the patent scope, wherein the first conductivity type The method of manufacturing the electrostatic discharge protection according to the fourth aspect of the invention, wherein the second conductivity type is a p-type. "&quot; 6" as described in the scope of the patent application The step of forming a gate oxide layer between the second gate and the substrate. The method of the electrostatic discharge protection structure according to claim 3, wherein the light second type ion implantation process is doped The method of manufacturing an electrostatic discharge protection structure according to the fifth aspect of the invention, wherein the light second type ion implantation process is doped with boron. The method of manufacturing the electrostatic discharge protection structure according to Item 1, wherein the shielding layer between the first gate and the second gate is located at a center of a region between the first gate and the second gate. The manufacturing method of the electrostatic discharge protection structure according to claim 1, wherein the doping concentration of the second conductive type heavily doped region is higher than the light second conductivity type ion ES] The doping concentration of the implanting zone. The manufacturing method of the electrostatic discharge protection structure as described in claim 1, wherein the bottom depth of the light second conductivity type ion ESD implantation zone is greater than the above The bottom depth of the heavily doped region of the two conductivity type. 1 2 · A method for manufacturing an electrostatic discharge protection structure, comprising the steps of: providing a substrate of a first conductivity type, having a first isolation junction 0702-9558twfl(4.5) ; 91P77 ; Robert.ptc Page 22 of 1278092 is a conductive type and the above-mentioned mask doping area; the process is formed by a domain number 92115944. VI. Patent application scope and a second Forming a second conductive pattern between the first gate and the first second isolation structure and forming a shielding layer on the second gate and the second isolation node a second portion of the region between the gates is second to the first gate and the second gate layer is covered by the second conductivity type, and the second type of ion implantation is used to implant the second conductivity type of the lightly doped region. a masking layer; removing the shielding layer; forming sidewall insulating spacers on the side; and performing a second type ion implantation sidewall insulating spacer and a first spacer sidewall insulating spacer 舆 a second isolation second gate The sidewall insulating spacers are electrically doped regions. The manufacturing method of claim 1, wherein the first one is modified as in the patent application, the first gate and the second gate doped region are on the surface of the substrate, which is between the structures The second gate is between the first gate and the second gate; between the gate and the first isolation structure, and between the first gate and the first doped region, and between the layer And the two processes of the first gate and the second gate which are not exposed by the first light-shielding type ion exposed in the substrate, respectively, between the first gate-off structure and the second gate The above-mentioned substrate between the structures and the first gate and the second electrode of the second embodiment are electrically conductive type P-type. Electrostatic discharge protection structure according to 3 items 0702-9558twfl(4.5) : 91P77 ; Robert.ptc Page 23 Case No. 92115944 1278092 A manufacturing method for a six-application application area, wherein the second conductivity type is an N type. A method of manufacturing an electrostatic discharge protection structure according to claim 12, wherein the first conductivity type is NS. The method of manufacturing an electrostatic discharge protection structure according to claim 15, wherein the second conductivity type is a P type. The method for manufacturing an electrostatic discharge protection structure according to claim 12, further comprising forming a gate oxide layer between the first gate and the substrate and the second gate and the substrate. step. The method of manufacturing the electrostatic discharge protection structure according to claim 14, wherein the light second ion implantation process is doped with a phosphorus ion and a god ion to J. The method for manufacturing an electrostatic discharge protection structure according to claim 16, wherein the light second type ion implantation process is doped with boron from 〇2 〇. The method for manufacturing an electrostatic discharge protection structure according to any of the preceding claims, wherein the shielding layer between the first gate and the second gate is located at a center of a region between the first gate and the second gate. The method for manufacturing an electrostatic discharge protection structure according to claim 12, wherein the doping concentration of the second conductive type heavily doped region is higher than the light second conductivity type ion ESD implant. Doping concentration of the zone. 2. The method of manufacturing the electrostatic discharge protection structure according to claim 12, wherein the bottom second depth type of the light second conductivity type ion ESD implantation area is greater than the second conductivity type The depth of the bottom of the doped region. 23. A method of manufacturing an electrostatic discharge protection structure comprising the following steps 1278092 Case No. 92115944 Amendment VI. Application for Patent Scope a conductive substrate, providing a first isolation structure and a second spacer, a third gate, and forming a second conductive isolation structure and a second second gate, the third gate forming a shielding layer Between the first gate and the second, and between the fourth gate and the third gate are exposed, and the second gate-type second conductivity type lightly doped ESD is covered by the shielding layer of the second gate. a fourth gate type isolation between the structures and between the gate and the first gate of the fourth gate between the light-doped structure of the first and second sub-dipole regions, and sequentially disposed between - one of the first gates, ~' region on the surface of the substrate, where the first pole is not provided; the pole is separated from the first Α/τ brother by the first gate of the second gate, In the second gate area of the second brother, the unexposed state of the ion-isolation junction is the region between the three gates and the first and the second conductivity type lightly doped, so as to form a lighter layer in the above substrate. The first of the two types of conductive isolation structures Gate region implantation process electrical patterns formed on a light doping and removing the shielding layer; Forming sidewall insulating spacers on both sides of the first gate, the second gate, the third gate, and the fourth gate; and performing a first type ion implantation process for the first isolation structure and A second conductive type heavily doped region is formed between the second isolation structures without the above-mentioned gates. The method of manufacturing an electrostatic discharge protection structure according to claim 23, wherein the first conductivity type is a p-type. 0702-9558twfl(4.5) ; 91P77 ; Robert.ptc </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The method of manufacturing an electrostatic discharge protection structure according to claim 23, wherein the first conductivity type is N-type. 2. The method of manufacturing an electrostatic discharge protection structure according to claim 26, wherein the second conductivity type is a P type. The method of manufacturing an electrostatic discharge protection structure according to claim 23, further comprising the step of forming a gate oxide layer between the first gate and the substrate and the second gate and the substrate. The manufacturing method of the electrostatic discharge protection structure according to claim 25, wherein the light second type ion implantation process is doped with at least one of a cerium ion and a god ion. 3 〇 The manufacturing method of the electrostatic discharge protection structure described in claim 27, wherein the light second type ion implantation process is doped with a dead ion. 3. The method of manufacturing the electrostatic discharge protection structure according to claim 23, wherein the shielding layer between the second gate and the third gate is located at the first gate and the third gate The center of the area between the poles. 32. The method for manufacturing an electrostatic discharge protection structure according to claim 23, wherein the doping concentration of the second conductive type heavily doped region is higher than the above-described light-dielectric type ESD implantation. Doping concentration of the zone. The manufacturing method of the electrostatic discharge protection structure according to claim 23, wherein the bottom depth of the light second conductivity type ion ESD implantation region is larger than the second conductivity type densely doped region The bottom depth. 0702-9558twfl(4.5) ; 91P77 ; Robert.ptc Page 26 1278092 3 4 ^ An electrostatic discharge protection structure comprising: a substrate of a first conductivity type; a second dipole, a pole and a second gate disposed on the surface of the substrate; a second conductivity type ion doping a miscellaneous region, respectively disposed on a substrate between the second gate of the f=gate 舆 and the second gate between the first gate and the second gate; and//the second conductivity type ion The ESD implanting region is disposed on the base between the first gate and the second gate, and has an opening, so that a portion of the second type ion doping region disposed between the first gate and the second gate is formed Contact the substrate. 〇σ 3 5 · The electrostatic discharge protection structure as described in claim 4, further includes a immersion contact region provided at the above opening. 3 6 The electrostatic discharge protection structure according to claim 4, further comprising a side edge spacer disposed on both sides of the first gate and the second gate. The electrostatic discharge protection structure according to claim 4, wherein the first conductivity type is a P type. The electrostatic discharge protection structure of claim 37, wherein the second conductivity type is N-type. The electrostatic discharge protection structure of claim 34, wherein the first conductivity type is N-type. 40. The electrostatic discharge protection structure of claim 39, wherein the second conductivity type is p-type. 41 · Electrostatic discharge protection junction as described in claim 34 1278092 Case No. 92115944 Amendment 6. The scope of application for patents further includes a gate bump disposed between the gate and the substrate: the electrode and the substrate and the second κ emulsion layer. Structure, = as described above in the ϋ利-\园第38th item of the electrostatic discharge protection of the knot and strontium ions; the electric type ion ESD planting zone doped scales away from 4 3 · If the patent application Weng network constructor ^ 1 祀The electrostatic discharge protection junction described in the 40th item of the siblings &amp;&amp; * - ¥ electric type ion ESD planting area is doped with boron away from 44. The electrostatic discharge protection structure as described in claim 4 of the patent scope' The opening of the light second conductivity type ion ESD implantation area is located at the center of the area between the first gate and the second gate. 4 5 · The electrostatic discharge protection structure according to claim 4, wherein the doping concentration of the concentrated second conductivity type doping region is in the light second conductivity type ion ESD implantation region Doping concentration. The electrostatic discharge thinning structure according to claim 4, wherein the bottom depth of the light second conductivity type ion ESD implantation region is greater than the bottom of the concentrated second conductivity type doping region. depth. 0702-9558twfl(4.5) ; 91P77 ; Robert.ptc Page 28 No. Fig. 铖4B B Year Month R • Superficial Schedule: 95/9/1 72 72