TW200428633A - Electrostatic discharge protection device and method of fabrication thereof - Google Patents

Abstract

An ESD protection device includes a first gate and a second gate formed on a first-type substrate. A plurality of second-type heavily doped regions is formed on the substrate between and on the outer sides of the first and second gates, respectively. A second-type lightly doped region is formed on the substrate between the first and second gates and includes an opening directly connect the second-type heavily doped region formed between the first and second gates to the first-type substrate.

Description

200428633

[Technical Field to which the Invention belongs]

The present invention relates to a semiconductor process, in particular to a kind of electrostatic discharge (Eiectr static discharge) that has a low input impedance of f1, low parasitic capacitance at the interface, and high electrostatic discharge resistance. ESD) The submicron (deep — sub_microon) CMOS process of the anti-shy circuit. [Prior technology], Electrostatic discharge (ESD) is a relatively large amount of potential difference or charge generated by friction between different materials, according to different discharge modes, from several to hundreds of nanoseconds (nan0-sec〇nds) Caused by discharge within time. However, the most common causes of ESD stress are the following three models: human body model (HBM), machine model (MM), and charged device model (CDM). General integrated circuit product specifications are: ESD tolerance in 0M mode is ± 2k volts, ESD tolerance in MM mode is 200 volts, and ESD tolerance in CDM mode is ± 1〇 〇〇volt.

The part of an integrated circuit (IC) component that first encounters an electrostatic discharge pulse is usually an input / output buffer (I / O buffer) that is directly coupled to the bonding pad or terminal of the chip. FIG. 1A is a circuit diagram showing a conventional input circuit, and FIG. 1B is a semiconductor cross-sectional view corresponding to FIG. 1A. 1 / 〇Bond (PAD) 1 0 is coupled to the NM0S transistor 1 2 A and NM0S transistor 1 2B source / drain connection point, the source / drain of 12A transistor NM0S is coupled to the power supply

200428633

VDD 'and the source / non-polarity of the NM 0 S transistor 1 2 B is connected to the power source v. The gates of the NM0S transistor 12A and the NM0S transistor 12B are lightly connected, and the NM0S transistor 12A and the NM0S transistor 12B are dropped to +0 in normal circuits. Hold off. Therefore, the NMOS transistor 12A and the NMOS transistor 12 = protect the ESD protection circuit 14. | FU Feng When the I / O bonding pad 10 receives an electrostatic discharge pulse, a large amount of current will be released through the current path of the NMOS transistor 12A and the NMOS transistor 12B. If the integrated circuit does not have a good electrostatic discharge protection circuit, the above-mentioned large amount of ESD current can easily cause the gate of the NM0S transistor 12A and NM0S transistor 12B to be damaged. Or the ESD current may be concentrated in the NM0s transistor HA. It is close to the drain region of the NMOS transistor 12B near the surface of the most vulnerable channel region, and burns a specific region in the channel region. When the gate is damaged or the channel area is burned out, the integrated circuit will not operate smoothly. With the advancement of semiconductor process technology, Esd tolerance has become one of the main considerations for the reliability of integrated circuits. Especially when the semiconductor process technology enters the sub-quarter-micron era, the sealed ed-down transistor, shallower doped junction depth, thinner gate oxide layer, lightly doped Lightly doped drain (LDD), shallow trench isolation (STI) process, and metal silicide (Salicide) process are all vulnerable to ESD tolerance. Therefore, the I / O circuit in I C must be specially designed with ESD protection circuit to protect the components in IC from ESD damage.

III

0702-9558twf (nl); 91P77; Robert.ptd page 6 200428633

The clamping device (NM0s transistor 12A, 12B) in the ESD protection circuit 14 is used to protect the internal circuit 16 from being damaged by E. Among them, the source of the NM0S transistor 12A is coupled to 1 / 〇Joint pad 1〇, and its drain coupling

Connected to the VDD private terminal and the gate is coupled to the ground potential. Difficulty: The pole of the s transistor 1 2B is coupled to the 1/0 bonding pad 10, and its source is coupled to the vss potential terminal with a gate. The transistor 03, which is coupled to the I / O bonding pad 10, can be turned on before a voltage breakdown of its gate oxide layer occurs, and the ESD current can flow to the ground point to prevent the internal integrated circuit 16 from being damaged by the ESD. Since the ESD protection capability is mainly determined by the ESD tolerance of the clamping device, the traditional technology uses the implantation of impurities near the clamping device to improve the esd 9 capability of the clamping device. FIG. 2A is a cross-sectional view of a conventional ESD protection device having an ESD planting area, and FIG. 2B is a flow chart of a conventional process for forming the ESD protection device shown in FIG. 2A. As shown in FIG. 2A and FIG. 2B, gate oxide layers 21A and 21B (S1) are first formed on the p-type well region 20, and then lightly doped region structures 22A and 22B and sidewall insulating spacers 23A are sequentially formed. , 23B, and source / drain regions 24A to 24C (S2 to S4). After that, an ESD photoresist mask 'is formed, and an e g d cloth jp planting region 2 5 A to 2 5 C (S 5) is formed at the bottom of the source / inverted region 2 4 A to 2 4 C and its surroundings. Finally, a related subsequent process (s 6) is performed, for example, forming a metal oxide on the surface of the source / drain regions 24A to 24C. A self-aligned metal lithotripsy process (s a 1 i c i d e) can be used to deposit a metal layer to form a metal silicide. Among them, the metal layer is generally composed of refractory materials, such as

0702-9558twf (nl); 91P77; Robert.ptd Page 7 200428633 V. Description of the invention (4) Platinum (Pt), starting (Co) and chitin (Ti), taking titanium metal as an example, which can be physically vapor deposited (PVD) or chemical vapor deposition (CVD), for example, an annealing process (anneaiing) is performed by depositing a Ti layer after a gold plating process such as magnetron DC sputtering. ) Such as rapid thermal processing (Rapid Thermal Processing) to form a metal oxide interface. US Patent No. 5 5 5 9 3 52, Hsue discloses a method for forming an ESD protection device, which performs high-energy implantation through a contact window between a drain electrode and a source electrode to form a P-type ESD implantation region and a drain electrode therewith. A quina diode is formed to reduce the breakdown voltage of the junction. Therefore, by reducing the trigger voltage, the E g ρ protection circuit can be quickly turned on to prevent the thin gate oxide layer from being damaged by the ESD current and improve the ESD tolerance. U.S. Patent No. 59 536 01, Shiue proposed a method to reduce the breakdown voltage of the drain terminal junction of the ESD protection device to make it conductive before the voltage of the gate oxide layer collapses. This traditional method is to reduce the drain junction by forming a deep ion implantation region with the opposite doping: quality (P-type) in the square of the source / inverted region of the ESD protection system before performing the silicidation reaction. In addition, the collapse of the electric energy avoids the problem of increasing the resistance of the metal M layer caused by 2 sub-elements when performing high-energy ESD implantation. ^

National patent number N 0. 6 1 1 4 2 2 6 Chang proposed a method for forming ESD protection

200428633 V. Description of the invention (5) The method of protecting the device, using a photoresist mask to cover the internal circuit and the metal cutting layer of the ESD protection device. The part of the metal silicide layer that is not covered by the photoresist mask will be peeled off when the dry etching process is performed to expose the conductive layer and the source / drain regions. Then, the screen is not covered by a photoresist. :: Perform ion implantation process (Kina junction implantation) to form a thick heart. Next, 'use an additional ESD photoresist mask to implant and limit the lightly doped === (llghtly doped drain, LDD) structure Range. In this traditional technique, a dense p-type ESD implanting system formed with high energy is located at the bottom of the electrode =; the pole is formed: a kinescope diode is formed to reduce the junction electrical strength. Correspondingly, by reducing the trigger voltage, the ESD protection device can be guided earlier to prevent the thin gate oxide layer from being damaged and improve the tolerance. However, the shortcomings of the various UD implantation processes disclosed by the mentioned traditional technologies are that the formation of the basin> A "^ > ^ The leakage current of the Kinetron diode you have created will be Greater than ...: The leakage current of the esd fabric interface is low and it has a low noise tolerance. Furthermore, since the empty area of the kina diode is thinner than the empty area without this ESD fabric interface, Therefore, it has a larger parasitic capacitance. In addition, the use of high and low voltage integrative integrated circuit, its core logic area

It: t ΐ level, the operating power source '’and the power received by the input / output area-. :: the voltage level returned. The voltage of the ESD protection device can drop = about 5 to 8 volts. However, when using the high- and low-voltage co-capacitor IC 2 ί Ϊ 22 'predictable noise or overshooting V anti-fung device is turned on during normal operation, resulting in

200428633 V. Description of the invention (6) Signal or function is invalid. In addition, because the parasitic capacitance value is inversely proportional to:

Parasitic capacitance of bond pads. Under the high-speed operation of the circuit, when coupled to the I / O ^ Yen Fen's protective device with a kinah interface will extend the rise of the signal and reduce it by 8J. Therefore, the ESD protective device disclosed by the conventional technology is not suitable for high-speed circuits. [Inventive Content] Entertainment! Herein, in order to solve the above problem, the main purpose of the present invention is to provide an electrostatic discharge protection structure and a manufacturing method thereof, which can form a low voltage !, avoid collapse of voltage drop, good noise tolerance, and high ESD 1 The ESD protection device is suitable for high-speed operation and the high and low pressure co-concentration God 2 achieves the above-mentioned purpose. The present invention proposes a significant improvement in cmos product =, the depth of the road's ESD tolerance is in the order of microns) cmos =%. According to the method disclosed in the present invention, the distribution area of the ESD implanting area = the lower area except the non-polar contact area in the entire drain region; the traditional structure shown in FIG. 2A is different ... The method disclosed in the example is not the same as the traditional operation flow shown in Figure 2B. First, before forming the side wall insulation spacers, first define the ESD implanted area with an ESD photoresist mask, and then, in the entire drain region, lay a light N in the area except the drain contact area. Mask ion

200428633 V. Description of the invention (7) ESD implanted area of lightly doped drain (LDD) structure. When the ESD protection device has a larger discharge area, it has a higher ESD tolerance. The advantage of the ESD protection device according to the present invention is that it can reduce the current accumulation in the region of the drain region near the fragile channel surface and force the ESD current to be discharged through the region located at the bottom plane of the drain. In addition, the ESD protection device provided by Benming is compatible with the deep sub-micron (heart-seal-printed dagger 1111 ^ 〇11) 0103 process, and the "1) protection device fish circuit formed at the same time can be greatly reduced. Process cost. In addition, although the above-mentioned patent publications have disclosed that various types of ESD are implanted at the bottom of the ESD protection device ^ to form a kina diode to reduce the breakdown voltage and accelerate the conduction of the protection device, Adding the formed Kina diode, the leakage current increases and the noise tolerance is reduced. Furthermore, compared to the empty area of the common interface of the unregulated ESD planting area, the Kina is thinner. Therefore, it has a large parasitic capacitance. In addition, long-term compatibility: f-body circuits must pay special attention to whether the ESD protection circuit has: Input = valley, good noise tolerance, and high ESD tolerance. ί 'Earth from the ground' The low breakdown voltage and low noise tolerance of Kina diodes will lead to unexpected noise or excessive bursts " The circuit is accidentally turned on when the signal or function is lost, resulting in a thunder. Μ ί applies to High and low voltage compatibilities 2: According to the ESD protection circuit disclosed in the embodiment of the present invention, its breakdown voltage and no ESD implantation have been formed. = = 工 二 == The cloth disclosed in the embodiment is also indebted. To avoid the unexpected misunderstanding of the internal Thunder Road 1 and 4 operations

0702-9558twf (nl); 91P77; Robeitptd Page 11 200428633 V. Description of the invention (8) ----- The influence of signal or overshooting. Furthermore, another advantage of the ESD implanting method disclosed in the embodiments of the present invention is that since the breakdown x voltage does not change, the transistor of the conventional ESD protection device = the interface capacitance can be reduced. In addition, the ESD protection device disclosed in the embodiments of the present invention has been proven to be successfully used in the 0.25-Am CM0S process to form a gate-grounded NMOS (ggNMOS) and a stacked NMOS. (stacked NMOS), and greatly improve ESD tolerance, especially ESD tolerance in mechanical mode. According to the invention, two sets of protection devices are implemented, with low parasitic capacitance and unchanging breakdown power. ": Noise tolerance and excellent ESD tolerance, so it is suitable for high-speed and low-voltage compatible integrated circuit output. Input circuit. [Embodiment] Examples: Figures 3A to 30 are cross-sectional views showing a method for manufacturing an ESD protection device according to an embodiment of the present invention. The ESD protection device according to the embodiment of the present invention is applied to a deeper process. Micron CMOS process. In this finger structure, the ESD protection device 30 and the internal circuit 40 are simultaneously formed on a substrate 50 by a conventional process, such as a lithography process, an ion implantation process, an oxidation process, and an etching process. First, a p-type well region 52 and an isolation structure 51 are sequentially formed on the P-type substrate 50 to separate the ESD protection device 30 and the internal circuit 4. The isolation structure 51 can be formed by a local oxidation method of silicon (10 caiized oxon of siHcon (LOC0S)) or a shallow trench isolation (silicon trench isolation) process. The Mos transistor includes a gate

0702-9558twf (nl); 91P77; Robert.ptd page 12 200428633 V. Description of the invention (9)

The oxide insulating layer 53, the polycrystalline silicon gate 54, the lightly doped drain structure 57, the ESD implanted region 60, the sidewall insulating spacer 62, and the source / drain region are formed as follows. ^ The gate oxide insulating layer 53 is formed by thermal growth in an oxygen supply system (Oxygen stream system), and has a thickness of about ι0◦ or less. Next, an ion implantation procedure for adjusting the critical voltage is performed and a polycrystalline silicon layer is deposited by a low-pressure chemical vapor deposition (LPCVD) process to form a free electrode 54.

Figures 3B to 3E show the formation of a lightly doped drain junction. "Refer to Figure 3B, a photoresist layer redundant two and two separation structure 51, a P-type well region 52, and a gate electrode are formed on the surface of the substrate 50. Surface, and then use T light f cover 5 2 to form an isolation pattern (see Figure 3C ^, the remaining photoresist layer is indicated by reference number 55A. Next, refer to the figure, the gate electrode 54 and the photoresist layer 55A are used as a veil, and the disengagement: pole (LDD) 57 is performed, and finally, the 3D figure of Guangyi is removed). After the lightly doped drain electrode 57 is formed, a photoresist layer 58 is formed on the surface of the substrate 50 to cover it: 71

r-protection device: up, and connected :: Yu, the photoresist is marked with reference number 58a (such as 3G). Next, referring to the figure, the gate 54 and the photoresistor 58a are used as the weight: the cover

200428633 V. Description of Invention (10)

The curtain 'performs a light N-type ESD implantation process to form an ESD implantation area 60 that covers the lightly doped anode 5 and the predetermined drain region on the ESD protection device 30, and finally removes the photoresist 58A (such as the 31st) As shown). W Next, an interlayer dlelectric (ILD) 61 (as shown in FIG. 3J) is formed on the entire substrate 50 surface by chemical vapor deposition (CVD). The inner dielectric layer 61 is subjected to an anisotropic Reactive Ion Etching (RIE) step to form sidewall insulation spacers 62 on the sidewalls of each gate 54 (as shown in FIG. 3K). Next, referring to FIG. 3B, a photoresist layer 63 is formed on the entire surface of the substrate 50, and then a photomask 56C is used to define the photoresist area to form an isolation pattern (as shown in FIG. 3M). The remaining photoresist is Designated by reference number 63A. Next, referring to the second figure, a high-dose arsenic or phosphorus ion implantation process is performed using the gate 5 4, the sidewall insulating spacer 6 2 and the photoresist 6 3 A as a mask to form a source / drain doped region. 64, and finally remove the photoresist 6 3A (as shown in Figure 30). Subsequent related processes, such as forming on the gate structure and the source / drain region surface, will not be described in detail to simplify the description. Therefore, the manufacturing method of the protective device according to the embodiment of the present invention is completed. It is particularly noted that the range of the ESD implantation area 60 does not include the area corresponding to the bottom of the gate electrode 54, the source electrode, and the surface of the non-electrode forming metal silicide (drain contact area).

200428633 V. Description of the invention (11) Figure 4A shows the top view of the ESD protection device formed by the manufacturing method of the ESD protection device according to the embodiment of the present invention, and Figure 4B shows the line AA, along the line 4A in Figure 4A. The semiconductor cross-sectional view is the ESD protection device 30 shown in FIG. 30. Shown here is a gate-grounded M0S (gg-NM0S) structure. As shown in FIG. 4A, the ESD implantation region 70 is a region surrounding the area outside the region (drain contact region) indicated by reference numeral S and between the gates 72. Referring to FIG. 4B, the ESD implantation region 70 is located near the bottom of the drain region 74 between the gates 72, and does not include the area indicated by the number S. FIG. 5A is a top view of an ESD protection device formed by another method for manufacturing an es d protection device according to an embodiment of the present invention, and FIG. 5B is a cross-sectional view of the semiconductor not along the line BB ′ in FIG. 5A . The second figure and the fifth figure are stacked NMOS structures. The manufacturing method is the same as that of the conventional technology. However, as shown in Figure 5A, the ESD implantation area 80 surrounds the drain contact of the area indicated by the reference symbol s. Range) and gates between 82 A and 84A. Referring to FIG. 5B, the ESD implantation region 80 is located near the bottom of the drain region 85 between the gates 82A and 84A, and does not include the area indicated by the symbol s.

The ESD protection device according to the embodiment of the present invention is used to improve the resistance of the transistor ^ Qiu Ba W series / formed by the ❹-type ion implantation process planted under the drain region; i ΐ k i kN type Source /; and low doping concentration in the polar region. ESD allows the ions implanted by the plant to use Shishen or scaly ions as dopants, and

200428633 V. Description of Invention (12)

The ion implantation process is performed at the source / > and the electrode implantation energy. Therefore, the esd implantation area is located below the entire drain region between the gates, but does not include the area marked by the symbol s. Furthermore, those who are familiar with the related art know that the breakdown voltage at the interface between the drain region not covered by the light N-type implanted region and the p-type substrate has not changed, so the drain covered by the light N-type implanted region The breakdown voltage of the polar region is lower than the breakdown voltage of the drain region not covered by the light N-type implanted region. When a positive ESD voltage relative to one of the Vss bonding pads is supplied to the 1/0 bonding pad ', the drain of the NMOS transistor of the ESD protection device according to the embodiment of the present invention receives the above-mentioned ESD stress. Since the breakdown voltage at the interface between the non-polar region and the P-type substrate that is not covered by the light N-type implanted region has not changed, the esd voltage * is first discharged through this interface, and a side is used to quickly trigger the parasitic parasite The substrate current to the bipolar junction transistor (lateral n — p — n bjt). Finally, the ESD current is discharged to the bipolar junction transistor through the parasitic side of the NMOS transistor. Here, the discharge path of the ESD current is far from the fragile surface channel of the NMOS transistor and is discharged through a large area. Therefore, the ESD stress tolerance of the NMOS transistor can be greatly improved, especially the ESD tolerance of the mechanical model mode. In addition, the manufacturing method of the ESD protection device according to the embodiment of the present invention has successfully proved that the moon dagger can be applied to the 0.25 / zm CMOS process. In addition, according to the manufacturing method of the ESD protection device according to the present invention, in addition to the ESD protection device that can be used to form a NMOS transistor structure, it is also applied to the structure that forms a PMOS transistor. When forming an ESD protection device with a pM0s transistor junction, its manufacturing process is roughly the same as the aforementioned process, and ^

0702-9558twf (nl); 91P77; Robert.ptd page 16 200428633 V. Description of the invention (13) One ----- The difference lies only in the switch between p-type impurities and 1 ^ -type impurities. Furthermore, the ESD implanting method according to the present invention can be applied to stacked NMOS structures, and this structure has been widely used in high- and low-voltage compatible output-input circuits. The top view of the NMOS structure and the stacked NMOS structure formed by the process disclosed in the present invention have been shown in Figures 4A, 4β, 5A, and "" Figure 0 as shown above It is stated that the core logic area using a high-low voltage compatible integrated circuit uses a relatively high-level operating power supply, and the power supply 1 received by the output and input areas is a higher voltage level. Although the junction of the NMOS transistor covered by the ESD implanted area has a high breakdown voltage structure, the breakdown voltage and noise tolerance of the area not covered by the esd implanted area have not changed. Therefore, according to the present invention, the ESD protection device can be turned on during normal operation due to unexpected noise or overshooting. In addition, since the parasitic capacitance of the interface is inversely proportional to the width of the junction of the empty region of the transistor of the esd protection device, according to the ESD protection device of the present invention, the width of the junction of the empty region of the MOS transistor is not changed. The parasitic capacitance of the ESD protection device according to the present invention is much smaller than the traditional ESD protection device with a kinah interface described in the aforementioned conventional technology. Therefore, under the high-speed operation of the circuit, the place where the ESD protection device according to the present invention is coupled to the input or output bonding pad has low input impedance, and therefore does not prolong the rise or fall time of the signal, so it is suitable for high-speed operation. Circuit.

0702-9558twf (nl); 91P77; Robert.ptd Page 17 200428633 V. Description of the invention (14) Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art can do some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. _

0702-9558twf (nl); 91P77; Robert.ptd p. 18 200428633 The diagram briefly illustrates one '----- f makes the above-mentioned objects, features, and advantages of the present invention more obvious and easier to understand. The examples are implemented in accordance with the accompanying drawings, and are described in detail as follows: FIG. 1A is a circuit diagram showing a conventional turn-in circuit. The first β diagram is a cross-sectional view of the semiconductor corresponding to FIG. 1A. Fig. 2A is a cross-sectional view showing a conventional ESD protection device having an ESD distribution area. Fig. 2β is a flowchart showing a process for forming the ESD protection device shown in Fig. 2A in a conventional manner. 3A to 3O are cross-sectional views showing a method for manufacturing an ε $ d anti-compliance device according to an embodiment of the present invention. FIG. 4A is a top view showing an ESI) protection device formed by the md protection device manufacturing method according to an embodiment of the present invention. FIG. 4B is a cross-sectional view of the semiconductor taken along line A A in FIG. 4 A. FIG. FIG. 5A is a top view of an ESD protection device formed by the manufacturing method of another ESD protection device according to an embodiment of the present invention. FIG. 5B is a cross-sectional view of the semiconductor taken along line βB in FIG. 5A. Symbol Description:

1 0 ~ I / 0 bonding pads; 1 2 A, 1 2B ~ NM0S transistor; 1 4 ~ ESD protection circuit; 16, 40 ~ internal circuit; 20, 50, 52 ~ P well area;

200428633 Brief description of the diagram 2 1 A, 2 1 B, 5 3 ~ gate oxide insulation layer; 2 2 A, 2 2 B, 5 7 ~ lightly doped drain structure; 2 3 A, 2 3 B, 6 2 ~ Side wall insulation spacer; 24A ~ 24C, 74, 85 ~ source / drain region; 25A ~ 25C ~ ESD planting area; 26 A, 26B, 54, 72, 82A, 84A ~ gate structure; 30 ~ ESD protection Device; 5 1 ~ isolation structure; 56A, 56B, 56C ~ photomask; 55, 55A, 58, 58A, 63, 63A ~ photoresist layer; 6 1 ~ inner dielectric layer; 60, 70, 80 ~ ESD implant Area; S ~ ESD-free planting area at the bottom of the contact area;

Vdd, Vss ~ power supply.

0702-9558twf (nl); 91P77; Robert.ptd page 20

Claims (1)

200428633 VI. Application Patent Scope 1. A method for manufacturing an electrostatic discharge protection structure, comprising the following steps: providing a substrate of a first conductivity type, having a first gate electrode and a second gate electrode; forming a second conductivity type The lightly doped region is on the surface of the substrate, which is located between the first gate and the second gate; and the first layer and the second gate are in a partial region between the first gate and the second gate. Conductive type lightly doped region, and expose an electrically lightly doped region between the first gate, the second gate, and the shielding layer that is not covered by the shielding layer; ... perform light second type ion cloth In the implantation process, the p-, k-ESD implanted regions of the lightly doped region of the first conductive type exposed in the above substrate are implanted; the light-shielded second conductive type ion is formed in the £ field to remove the shielding layer; Side; = side wall insulation spacers perform a thick second type from both the first idler pole and the second intervening pole 41 & > & The above-mentioned substrate between the spacers of the doped-electrode conductive type and the heavily doped region spacers Formation-Second Manufacturing = The above-mentioned 罘 -conducting type of the electrostatic discharge protection structure described in item 1 of the application section is P type. In the method k for manufacturing the electrostatic discharge protection structure described in item 1 of the target square, the second conductive type is N-type. 4 · As stated in item 1 of the patent scope of the electrostatic discharge protection structure 0702-9558twf (nl); 91P77; Robert.ptd page 21 200428633 VI. Manufacturing method for patent scope, wherein the first conductive type is p type. It is stated in the patent scope of the static lightning manufacturing method described in item 1, that the second conductivity type is _. 6. The structure of the electric bowel structure. The manufacturing method according to item 丨 of the patent application scope further includes the step of forming a gate oxide layer between the first gate and the upper and the second substrate, and between the gate and the substrate. ^ 7. The manufacturing method according to item 3 of the scope of patent application, wherein the light second-type ion = at least one of direct current system ^ ^ and arsenic ion. The system is made of doped phosphorus ions, and the electrostatic discharge protection structure described in item 5 above. ^ / The above-mentioned Teide type I ion implantation process in eight middle schools is doped with boron. The method of dressing the electrostatic discharge protection structure according to item 1, /, the layer located in the first gate and the second gate is located in the center of the area between the first gate and the second gate, The method of manufacturing the electrostatic discharge protection structure described in item 1 of the above patent application, wherein the doping of the second conductive type heavily doped region is performed on the light first conductive type ion E § D Doping in the planting area.丨, 1 1 · The manufacturing method of the electrostatic discharge protection structure described in item 1 of the scope of the patent application, wherein the depth of the ESD implanted region of the light-second conductive type ion is greater than the concentration of the second conductive type. The bottom of the miscellaneous area is deeply productive. A 1 2. — A method for manufacturing an electrostatic discharge protection structure, including * " 下 " Steps: 1 ^ Provide a substrate of a conductive type, which is provided at a first isolation junction 200428633 The doped region is between the first gate of the off-structure and the gate and the structure in a conductive type with the above-mentioned shielded doped region; the process is to form a domain between the sixteen, patent-pending structure and a second isolation structure. Forming a second conductive pattern between the first gate and the first isolation structure and forming a shielding layer between the second gate and the second isolation junction gate Part of the second conductive type covered by the first gate and the second gate layer is weakly performed. The second type is ion implantation. The second is conductive conductivity. Removing the above-mentioned shielding layer; forming a side wall insulation spacer; and performing a side wall insulation spacer of the second type ion implantation and a _th side wall insulation spacer and a second @ _ second gate electrode side wall The electrically insulating spacer is a heavily doped region. 1 3 · The manufacturing method of the scope of the patent application, which escapes from the top _ 1 4 · The first gate of the scope of the patent application, and the first surface of the substrate above, which is the second gate and the second gate Between two gates; between the first isolation structure, and between the first gate and the lightly doped region, and exposed between the masking layer and the light second conductive type ions that are not exposed in the above-mentioned substrate The two processes of the first gate and the second gate are to form a substrate between the first gate separation structure, the second gate structure, and the first gate and the base respectively. The conductive cracking state of the electrostatic discharge protection structure described in the second item 2 is P type. Electrostatic discharge protection structure as described in item 3 0702-9558twf (nl) »91P77; Robert.ptd Page 23 200428633 6. Apply for the f-making method of special brake fan park, where the second conductivity type is N type. i 5 • The manufacturing method of the electrostatic discharge protection front as described in item 12 of the scope of the patent application, wherein the first conductive type is a P type. The structure β is the manufacturing method of electrostatic discharge 俾% as described in item 15 of the scope of patent application, wherein the second conductive type is N-type. Photo i 7 • The manufacturing method of the electrostatic discharge protection device as described in item 12 of the scope of the patent application, further comprising forming a gate between the first gate and the substrate and the second structure and the substrate. Oxidation step. The above 18 • The manufacturing method of electrostatic discharge protection & as described in item 14 of the scope of the patent application, wherein the above-mentioned light second-type ion implantation process is doped with at least one of a conformer and an arsenic ion. ^ j 9 • The manufacturing method of the electrostatic discharge protection device described in item 16 of the scope of the patent application, wherein the above-mentioned light second-type ion implantation process is doped with rotten ions. 20. The manufacturing method of the electrostatic discharge protection structure according to item 12 of the scope of the patent application, wherein the I shielding layer is located between the first and second gates. The center of the region between the poles. 2 1 · The manufacturing method of the electrostatic discharge protection structure described in item 12 of the scope of the patent application, wherein the doping concentration of the second conductive type heavily doped region is higher than that of the light second conductive type ion ESD cloth. Doping concentration in the planted area. 2 2 · The manufacturing method of the electrostatic discharge protection structure according to item 12 of the scope of the patent application, wherein the bottom depth of the light second conductivity type ion ESD implanting region is greater than the second conductivity type heavily doped region Bottom depth. 2 3 · —A manufacturing method of electrostatic discharge protection structure, including the following steps 0702-9558twf (nl) ^ 91P77; Robert.ptd page 24 200428633 6. Application scope: Provide a substrate of a first conductivity type, which is sequentially arranged between a first isolation structure and a second isolation structure A first gate, a second gate, a second gate, and a fourth gate; a first isolation structure forming a lightly doped region of two conductivity types on the surface of the substrate and a second Where the first gate, the second gate, the third gate, and the fourth gate are not provided between the isolation structures; a shielding layer is formed between the first gate and the first isolation structure, Brother, question f and the first: between the third gate and the fourth gate ^ between the fourth gate and the second isolation structure and between the second gate and the second gate, the second conductive type Lightly holding miscellaneous areas, and two, f # 二 Ｍ ϊ ί between the gate, the third gate and the above-mentioned shielding layer is not covered by the above-mentioned shielding layer-^ batch-< the first conductive type is lightly mixed Miscellaneous area; the first-ion implantation process' to expose the above-mentioned substrate to remove the shielding ; Forming sidewall insulation spacers on both sides of the upper three gate and the third interrogation pole; and the first gate and the second stage of the first ion implantation process between the first and second isolation structures The shape of the above poles is not provided: an m-type heavily doped region. Don't be conductive 24. The manufacturing method as described in item 23 of the scope of patent application ', wherein the first conductive type is a discharge-compliant structure 0702-9558twf (nl); 91P77-Robeit.ptd Page 25 200428633 VI. Application for patent scope 2 5. The manufacturing method of the electrostatic discharge protection structure described in the scope of patent application No. 24, wherein the above-mentioned second conductivity type For NS. -2 6. The manufacturing method of the electrostatic discharge protection structure according to item 23 of the scope of patent application, wherein the first conductive type is P type. 27. The manufacturing method of the electrostatic discharge protection structure according to item 26 of the scope of patent application, wherein the second conductive type is N-type. 28. The manufacturing method of the electrostatic discharge protection structure according to item 23 of the scope of the patent application, further comprising forming a gate oxide layer between the first gate and the substrate and the second gate and the substrate. step. 29. The manufacturing method of the electrostatic discharge protection structure according to item 25 of the scope of the patent application, wherein the light second-type ion implantation process is doped with at least one of phosphorus ions and arsenic ions. 30. The manufacturing method of the electrostatic discharge protection structure according to item 27 in the scope of the patent application, wherein the above-mentioned light second-type ion implantation process is doped with boron ions. 31. The manufacturing method of the electrostatic discharge protection structure according to item 23 of the scope of patent application, wherein the shielding layer located between the second gate and the third gate is located between the second gate and the third gate The center of the region between the poles. 32. The manufacturing method of the electrostatic discharge protection structure according to item 23 of the scope of the patent application, wherein the doping concentration of the second conductive type heavily doped region is higher than that of the light second conductive type ion ESD cloth. Doping concentration in the planted area. 33. The manufacturing method of the electrostatic discharge protection structure according to item 23 of the scope of the patent application, wherein the bottom depth of the light second conductivity type ion ESD implanted region is greater than the second conductivity type heavily doped region Bottom depth. 0702-9558twf (nl); 91P77; Robert.ptd p. 26 200428633 Including: 'Set on the surface of the above substrate; Itch areas are respectively located at the 3rd and the second gate of the first gate-a kind of electrostatic discharge protection structure-a first conductive type substrate; a first gate Electrode and a second gate complex with a plurality of second conductive type ions doped on the substrate between the first gate and the second gate and on the other side which is not adjacent to each other; and a second conductive type ion esd戸 弓 杌 述 筮 -Lush pillow > 0 ^ Cushion & set in the above, so that the substrate set between the straight gate and the first gate of the upper ion doped region has a first gate A portion between the electrode and the second gate electrode is thickly contacted with the substrate. / ~ f 3 scoop 5 including Shishen and: the electrostatic discharge protection structure described in item 34 of the professional prostitute, including a drain contact area, is disposed in the opening. 3 6 .If you read 'Zhehe Jwei No. 3 4 js, + 丄 $ ^ 1% dry discharge protection structure described in item 4 d', including 纟 and placed in the above ^^^. /, The sidewall insulation spacers on both sides of the gate. 3 7 · The electrostatic discharge protection structure as described in item 34 of the scope of the Shen / fen patent, wherein the first conductive type is a ρ type. 3 8 · The electrostatic discharge protection structure as described in item 37 of the patent application scope, wherein the second conductivity type is N type. 39. The electrostatic discharge protection structure according to item 34 of the scope of patent application, wherein the first conductive type is a p-type. 40. The electrostatic discharge protection structure according to item 39 of the scope of application, wherein the second conductive type is N-type. 41. The electrostatic discharge protection structure described in item 34 of the scope of patent application 0702-9558twf (nl); 91P77; Robeit.ptd 200428633 6. The scope of patent application, further includes a gate oxide layer disposed between the first-alarm and the above-mentioned substrate and between the second gate and the above-mentioned substrate. 4 2 · The electrostatic discharge protection structure as described in item 38 of Shen Qing's patent scope, wherein the light second conductive type ion ESD implanting region is doped with at least one of a phosphorus ion and an arsenic ion. 43. The electrostatic discharge protection structure according to item 40 of the scope of the patent application, wherein the implanting region of the above-mentioned light-conductive type ion E S D is doped with ions. 4 4 · The electrostatic discharge protection structure as described in item 34 of the Shenjing patent scope, wherein the opening located in the light-second conductive type ion ESD implanting area is located between the first gate and the second gate The center of the area. 45. The electrostatic discharge protection structure according to item 34 in the scope of the patent application, wherein the doping concentration of the doped region of the second conductive type is equal to the doping of the ESD implanted region of the light second conductive type ion. concentration.冋 46 · The electrostatic discharge NVC described in item 34 of the scope of the patent application, wherein the above-mentioned light second conductivity type ion ESD implanted area 卩 'deep production σ is larger than the bottom of the above-mentioned thick second conductivity type doped region depth. & 邛 Bing You 0702-9558twf (nl); 91P77; Robert.ptd page 28