TWI277982B - Semiconductor memory device with auto refresh to specified bank - Google Patents

Abstract

Method and apparatus for use with multi-bank synchronous dynamic random access memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

Description

1277982 IX. Description of the invention: [Technical field of the invention] The conductor device specifies the memory of the system, and is related to the dynamic random access memory (DRAM) half system, and the specific system is for one body of a multi-module The module performs a method and device for automatically updating each module. [Prior Art] The "M" device is well known to us and can usually be found in a digital system that requires reading and writing a number of it bodies. The dram device is so named because the data in the parent-memory unit must be periodically updated by reading the data, otherwise the data stored in the library will be destroyed. The new synchronous 嶋乂 device often uses -, automatically updates the I type, and each time it is initiated by an external memory controller - the automatic update operation, the device updates the dram memory to print a car 歹 j The internal update column counter is incremented column by column for a continuous automatic update operation and wraps around the top of the array when it reaches the bottom. The dram memory controller therefore has some flexibility in when to issue an automatic update command to a dram device, as long as all columns can be updated for the maximum time that the array = set to maintain stable data. Many SDRAM devices contain multiple memory modules, and the higher order column address bits provided to the SDRAM with one operation determine which module will receive the operation. Such a device is described in U.S. Patent No. 5,627,791, issued toW. Wright's device allows the use of these high-order column address bits: Addressing automatic update operations to individual modules. Wright maintains a separate update column counter for each module and selects the appropriate update column counter for the module that is the target of each update operation. Wright's Memory Controller Negative 101313.doc 1277982 _ Address each module at the minimum rate required to maintain data stability. SUMMARY OF THE INVENTION The described embodiments add flexibility and enhanced performance over prior art per-module update (PBR) SDRAM devices. A plurality of memory modules share an update address generator. The module address circuitry receives an externally provided module address for an update operation and applies the update operation to the current update column of the memory cell array module corresponding to the module address. A new _ new module address counter determines when the update address generator should be incremented to a new update column by one of several techniques described below. This allows a memory controller to efficiently schedule updates to certain modules while performing read/write operations on a separate memory module, and allows automatic update sequences for different update column transitions. [Embodiment] FIG. 1 shows a SDRAM device in block diagram form. The memory cell array 10 includes a plurality of memory cell array modules, wherein n can be any number greater than one, and is typically a power of two. As is well known in the art, each module includes a plurality of memory cells MC, each MC being coupled to a unique combination of one of a plurality of bit lines BL and one of a plurality of word lines WL. Column address decoder circuit 12 selects one of the word lines for each memory operation based on a provided column aradda. The column address decoder circuit 12 includes a plurality of column address decoders 12-ι to 12-n, each of which activates the memory cell array modules 10-1 to 10-ni respective memory cell arrays The word line in the module. A plurality of module selection signals bal to ban determine which column address solution 101313.doc 1277982 The coder corresponds to the column address radda. The address decoder circuit 14 selects the bit line to be read/written during the memory read/write operation based on the row address cadd. The row address decoder circuit 14 includes a plurality of row address decoders 14-1 through 14-11, each of which reads a respective memory cell of the memory cell 70 array modules iOU through 1〇-n The bit line in the array module. The update module address counter 16 receives an externally provided automatic update command REF, and g should initiate an address count refresh (ACU) signal to the update address counter 18 when a new update column address is generated. The update address counter provides the § 钿 update column address RADD to the selector 26. That is, when the memory 100 includes eight modules, the update module address counter 16 starts the address count refresh after receiving the external automatic update command signal (REF) 8 times (each time for a memory module). (ACU) signal. After the ACU signal is enabled, the current update column address RADD is refreshed to the next update column address RADD, and the next update column address RADD corresponds to a memory cell update column to be updated during the next update cycle time. . This process is repeated continuously during the update operation. The address latch 20 receives a plurality of external address signals ADD and a plurality of external module address signals B A . The external automatic update command signal rEf, active command (ACT) signal, write command (WR) signal, and read command (rD) signal determine how to interpret ADD and B A. During an active command, the ADD signal is latched and provided as a column address radd to the selector 26 for initiating a word line corresponding to the column address radd of a selected memory module, and the BA signal It is latched and provided to the module address decoder 22 as the module address ba of the selected memory module. Between a read or write command period 101313.doc 1277982, the ADD signal (and possibly also the BA signal) is latched and provided to the row address decoder circuit 14 as the row address cadd. During an automatic update command, the module address signal B A is latched and provided as a module address ba to the modular address decoder 22. The module address decoder 22 decodes the module address ba to generate a suitable module selection signal from the group bal-ban. The command decoder 24 receives the external command signal COM and generates various control signals including ACT, WR and RD. The selector 26 determines which one of the current update column address RADD or the address latch output address radd is to be passed as the column address ra (jda to the column address decoder circuit 12. The automatic update command signal ref is used as the selection signal Provided to selector 26' where raid is selected when REF is asserted, otherwise radd is selected. When write command signal WR is active, data input circuit 28 reads write data from an external data bus. Signal Din, and the write data signal din is provided to the memory cell array module selected in response to the module address B a. When the read command signal RD is active, the data output circuit 3 responds to The memory cell array module selected by the module address BA receives the read data signal dout, and supplies the read data signal D〇m to the external data bus. The following figure further illustrates the SDRAM device 1 Figure 2 shows an embodiment of 11 specifically updating the module address counter 16. The circuit 200 contains three D (switching) flip-flops 2 (μ, 2 (8) j and 200-3 ' #一Positive & has a connection The input terminal of the logic high 帛, an output terminal QB and a clock input terminal (3). For the flip-flop 2〇 (μ, I01313.doc 1277982 pulse input terminal CK is connected to REF, so that the flip-flop 200-1 The QB is switched when a continuous automatic update command is received. The output terminal QB of the flip-flop 200-1 is connected to the clock input terminal CK of the flip-flop 200-2 so that the flip-flop 200-2 receives every other time. Switching to an automatic update command. The output terminal QB of the flip-flop 200-2 is connected to the clock input terminal CK of the flip-flop 200-3 so that the flip-flop 2 0 0 - 3 is connected every fourth time. Switching to an automatic update command. The outputs of the flip-flops 200-1, 200-2, and 200-3 are provided as input Qbs Q2 and Q3 to a three-input NAND gate NA1. The NAND gate NA1 provides its output. To inverter II, the inverter II then provides its output as an update module address counter ACU signal. In operation, the counting circuit 200 generates 000, 001, 010, 011 in eight consecutive automatic update cycles, 1〇〇, 101,110, m output QiQ2Q3, and then repeated. For example, assume that the update command signal REF is enabled When the output data Q1Q2Q3 of the counter circuit 200 is 〇〇〇, the ACU is started when the output data Q1Q2Q3 is equal to 111, so that the signal is sent to the update address counter 18 to advance the current update column. In another example, it is assumed that the ref is enabled. After that, the output data qiq2q3 of the counter circuit 200 is 1, 〇 1, and when the output data Q1Q2Q3 becomes 100, the ACU is started. 3 shows a module address decoder 22 for the eighth module of FIG. The three module address signals ΒΑ0 to BA2 are decoded to select one of the eight module selection signals ba0-ba7. Figure 4 shows a timing diagram of the circuits of Figures 2 and 3. In Figure 4, the first - automatic update loop "an external controller determines the coffee and provides a module address BA = 000. The counting circuit 2 has an output q iq2q3 = 〇〇〇, and updates the column 101313.doc - 10- 1277982 Address RADD has the least significant bit 〇〇. In the next seven automatic update cycles, the memory controller provides different module addresses (unlike (8) 〇) in the eight modules. In each of the updated column addresses 〇〇.〇〇. In the further loop 8, Q1Q2Q3 has counted to in, causing Acu to transition to the logic level at the next clock edge. ACU transition to high level causes update address counter 18 (Fig. 1) increments RADD so that the least significant bit is now 〇 1. At update cycle 9, a module address 〇〇〇 is provided for the new update column 00..01. However, for loop 9- 16. The module update order is different from the update order of the loop 1_8. This does not change the operation of the update module address counter ,6, which sends a signal to the update address counter 18 to address the eight update operations to the current update column. The update column is advanced. Figure 5 illustrates the second embodiment of the present invention. For example, the update module address counter 5 16 replaces the update module address counter 16. The update module address counter 5 1 6 receives the external module address ba in addition to the automatic update command signal REF. This allows update The module address counter 5 16 ensures that all modules have been addressed in an automatic update operation before proceeding with the update address counter (even though the automatic update operation is repeated and requires more than eight update operations). Figure 6 shows the update Further details of an embodiment of the module address counter 5 16. The plurality of module address latches BAL0-BAL7 are arranged to be in an automatic update operation when the respective decoded module addresses ba0-ba7 are in an automatic update operation After being addressed, it is temporarily stored. The first inverse OR gate 610 reverses the output of the module address latches BAL0, 6 八乙1, and ugly 八乙2. The second > The outputs of the module address latches BAL3, BAL4, and BAL5 are inverted. The third NOR gate 614 inverses the output of the module address latches BAL6 and BAL7. 101313.doc 1277982 NOR gate 610, The outputs of 612 and 614 are provided as inputs to the 1^^^ gate 62〇. The 622 provides the output of the NAND gate 620 as an address count refresh signal ACU to the update address counter 18. In operation, each module address latch B ALO-BAL7 outputs a logic high level value until a The update operation is directed to the corresponding memory module. Each of the n〇r gates 610, 612, and 614 will generate a logic low level output until each module address latch BALn fed to the NOR gate is temporarily stored. An update operation that points to its corresponding memory module. The NAND gate 620/inverter 622 will cause the ACU to remain low due to > until each N〇R gate receives an indication that all module address latches (generated to the input of the NOR gate) have been temporarily stored. An indication of an automatic update operation with a corresponding module address. In other words, the ACU signal is activated after all modules have been enabled for the update operation of the same updated column address. Figure 7 shows additional details of an embodiment of a module address latch 516, and specifically shows additional details of BAL0 and BAL7. Regarding BAL0, the transfer gate 71〇 _ receives baO as an input and provides an output to a latch including two inverters 720 and 725. The output of inverter 720 provides a latch output A0 and an input to inverter 725. Inverter 725 is coupled back to the input of inverter 720 to maintain a latched value. The latch output A0 is provided as an input to the NAND gate 730. The other input of the NAND gate 73 0 receives the automatic update command signal REF. The output of the nand gate 730 directly drives a low-level transmission input of the transmission gate 710 and drives an upper level of the transmission enable terminal via an inverter 735. Finally, the acu signal drives a 101313.doc -12- 1277982 transistor 74q connected between the input of the latch and ground. In the operation of the towel, when the ACU is determined, the I crystal 74 is turned on and the input of the latch 720 is pulled to the low level, and the drive latch outputs the gossip to the high level. When the latch output A0 is high, the NAND gate 73 〇 can respond to the high level input at the auto update signal REF. When both the gossip and the tonnage are high, the _ ND gate 73 0 generates a low level output that energizes the transmission gate 71. When the pass gate 710 is energized, it passes the bus to the input of the latch transistor. In this case, the latch outputs the switching state I when the _ is high level, and outputs A0 at the low level, thereby indicating that the module 〇 has requested the automatic updating operation. Once this event is latched and A0 is low, NAND gate 730 will not respond to the additional auto-update cycle until (4) the latch is reset after all modules have been addressed.

8 illustrates an update module address count H that may replace an update module address counter in some embodiments. Embodiment 81 updates the module address counter to count each updated module in the order in which it is latched. However, the update module address - the tensor 816 operates in a different manner. The module address counter (10) is updated until a predetermined starting module address is accompanied by the -automatic update command - the data is counted until the update is counted, and thereafter the count is updated, reset, and then waited Another automatic update command is issued together with the initial module address. In the embodiment, the module is assigned as the start module. Once: the memory controller describes module 0 during the automatic update, it can then address the seven remaining modules in any order, and then automatically update the column advancement and the device waits for the automatic operation of the other-pointing module. Update to start counting again. An advantage of this embodiment is that the memory controller can determine the time at which the update operation begins in each column by its 101313.doc -13 - 1277982 determining the time of the REF along with the module address 〇. In FIG. 8, the update module address counter 8 16 includes: a counting circuit 800, a reset circuit 810, an update start detection/latch circuit 820, two NAND gates 1 and 2, and two inverters. 12. The update start detection/latch circuit 820 receives the external module address Β and the external automatic update command signal REF. Circuit 820 determines its output BAL when a predetermined starting module address on the BA is received along with the automatic update command on REF. _ Input 3 into 1^ and REF to NA2 so that once BAL is determined, the output of NA2 can respond to REF. Inverter 12 inverts the output of NA2 and provides the inverted signal to count circuit 800. The counting circuit 800 includes three T (switching type) flip-flops 800-1, 800-2 and 800-3, each flip-flop having an input terminal T connected to a logic high level, an output terminal QB and a clock input. End CK. For the flip-flop 800-1, the clock input CK is connected to the output of 12 so that the flip-flop 800-1 is continuously updated automatically upon receiving an automatic update command with the starting module address. Switch QB during the command. The output terminal QB of the flip-flop 800-1 is connected to the clock input terminal CK of the flip-flop 800-2 so that the flip-flop 800_2 performs switching every time an automatic update command is received after determining the BAL. The output terminal QB of the flip-flop 800-2 is connected to the clock input terminal CK of the flip-flop 800-3, so that the flip-flop 800-3 receives a self-updating command every fourth time after determining the BAL. Then switch. The outputs of the flip-flops 800-1, 800-2, and 800-3 are supplied as inputs Q1, Q2, and Q3 to the three-input NAND gate NA1. The NAND gate NA1 supplies its output -14 - 1277982 to inverter II, which in turn provides its output as the update module address counter ACU signal. The ACU is provided to the reset circuit 810, and the reset circuit 810 resets the update start detection/latch circuit 820 when determining the ACU. Once reset, the start detect/lock circuit 820 waits for an automatic update command for the starting module address to begin counting for the next updated column. 9A shows internal circuit details of the update start detection/latch circuit 820, which includes an update start detection circuit 900, a switch 910, a latch 920, and an electrical crystal 930. The update start detection circuit 900 receives REF and BA and determines an START signal when the BA matches the start module address. Switch 910 receives the START signal and passes it to the input of latch 920 when switch 910 is activated. When START is passed to latch 920, latch 920 is latched high, thereby determining output BAL from circuit 820. The BAL is also fed back to switch 910, thereby deactivating switch 910. When self reset circuit 810 (Fig. 8) determines RESET, transistor 930 is activated, thereby pulling latch 920 to a low level. When latch 920 is pulled low, the BAL is deasserted and switch 910 is restarted in preparation for the circuit to perform the next automatic update command for the start address. 9B and 9C show two possible update start detection circuits 900. In Figure 9B, circuit 900 includes a NAND gate 940 that is paired with inverter 950 to implement an AND function. The REF and a decoded module address (in this case, baO, but any other module address can also be selected) are provided as input to the NAND gate. When both REF and baO are high, the output of inverter 950 is also driven to a high level and is provided as a START signal. 101313.doc -15- 1277982 FIG. 10 shows a timing diagram of the memory devices of FIGS. 5, 8, 9A, and 9B. Three different update module address sequences are instructed for successive update columns: one sequence for automatic update loops 1-8, the second sequence for automatic update loops 9_16 and the first sequence for automatic update loops 17-24 . However, each sequence begins with an automatic update of the module address 〇 (BA 000), causing the self-update start detection/latch circuit 820 to determine the BAL. The BAL remains ok until eight automatic update operations are completed (at the automatic update loops 8, 16, and 24), at which point the ACU is asserted, thereby triggering the reset circuit 810 to reset the update start detect/latch circuit 82. And BAL. In Figure 9C, the update start detection circuit 9 accepts any module address as the starting module address. All eight decoded module bits aba〇_ba7 are ORed by three NOR gates 960, 962, and 964, and their outputs are combined by NAND gates. The monolithic or computed module address is combined with REF by using a 1^^^0 gate 980 and an inverter 990, in a manner similar to that used in Figure 9B for a single module address. A start signal. Figure 11 illustrates a third embodiment of the present invention, SDRAM circuit 11A, wherein an update module address detector 1116 replaces the update module address counter 516 of Figure 5. The update module address detector 1116 functions by determining an Acu whenever an update operation is received for a predetermined final module address. Figure 12 illustrates an embodiment of an update module address detector 111. The detector 1116 includes an inverter 121, an m input/m output transfer gate 122, a comparator 1300, and a module address register 1320. The m lines of the external module address ba are supplied to the transfer gate 1220. The transfer gate 1220 is driven by an external automatic update command signal REF ref directly to drive the n gate of the transfer gate, and drives the P gate of the transfer gate via the inverter 丨21 〇 I013I3.doc -16-1277982. The module address register 1320 contains a predetermined final module address, which is stored by using m bits in the same order as the m B A inputs. When REF activates the transfer gate 1220, the comparator 1300 compares the in BA inputs to the input of the module address register 1320. When the comparison result is true, the comparator 1300 determines the ACU. The module address register 1320 can be programmed in many different ways. A simple but inflexible approach involves designing a chip mask ® to permanently determine a given final module address. Several more flexible ways will now be described. Figure 13 shows the way to program any module address into the final module address. The module address register 1320 actually includes (=::(1) in the program corresponding to each module 8]<:0 to:6&11]<:7. 〇(16(1) binary module address <BA0, BA1, BA2> The switch crossbar structure (switchcr〇ssbar) 134〇 allows response to a plurality of selection signals generated by the programmable module selector 14〇〇 One of the _ (SEL) selects the signal (SEL), and loads any of the register 132 〇 module addresses into a module address latch 133 可. The programmable module selector 14 〇〇 A corresponding selection signal SEL energizes one of the switches in the crossbar structure 134, indicating a stylized module indication. The comparator 1300 includes three module address comparators for BA〇, BA1, and BA2, respectively. Each comparator performs a binary comparison between one of the module address lines and a corresponding bit from the module address latch 1330. All three module address comparators generate two The carry match is output to the _αν〇 circuit, which determines the ACU when all bits match. 101313.doc -17- 1277982 Figures 14A, 14B, 14C and 14D illustrate four uses A possible method for setting the programmable module selector 1400. In Figure 14A, the module selector 1400 includes one or more circuits including a bond pad 1420a and an inverter 1440a. The bond pad 1420a provides a bonding option. When pad 1420a is bonded to a lead frame Vcc contact 14 10a, inverter 1440a does not define a select output SEL for the other. When pad 1420a is bonded to a lead frame ground contact 1430a, inverter 1440a is directed The line determines a select output SEL. Therefore, the final module address can be selected during the packaging process by bonding a selector 1400 to the ground and the rest to Vcc. In Figure 14B, the mode register group (MRS) 1450 provides n select lines SEL1 to SELn. When a specific combination of inputs RASB, CASB, and WEB triggers MRS 1450, MRS 1450 reads external address line Ai and decodes the address into a particular mode temporary The instructions can be used to initiate different select lines in select lines SEL1 through SELn. After assembling the SDRAM device, the pattern register group can also be used to permanently program a final module address. .in In 14C, MRS 1450 provides a plurality of MRS fuse-burning outputs MRS 1 -MRSn. By determining a particular combination of the fuse outputs, an electrical fuse circuit permanently cuts off two for each select line SEL. One of the electric fuses F1 and F2. Even when the device is powered off and turned on again, each SEL line will be permanently set to a high level or a low level depending on which fuse is cut.

Another programmable module selection circuit 1400 is illustrated in FIG. 14D. The embodiment of Figure 14D uses a laser-cut fuse F3 that can be cut after the device is fabricated but before being packaged. The circuit 1400 relies on a delayed control voltage VCCH 101313.doc -18- 1277982 to delay power-on until the supply voltage is stable, the delayed control voltage VCCH until the supply voltage rises above a threshold (included in Figure HD) The time is triggered to the high level when it is indicated in the voltage graph. Depending on whether the fuse F3 is cut or not cut, once the device is turned on, it will always be determined or de-determined. Figure 15 contains an example of a timing diagram for an embodiment of Figures U-md. With the selected component, a final module address ln is selected for comparison with the external module address. The SDRAM 1100 continues to update the modules in the same column until it receives an automatic update command with an initial module address of 1 (automatic update cycles 8, 16, and 24). When the final module address 丨^ is received, the update command is executed and the update column is advanced. It is irrelevant to provide the order of other module addresses. In fact, in this circuit, the update column can be advanced without addressing each module of a given update column. It is assumed that each of the SDRAM devices described above is paired with a memory controller capable of providing a sequence of allowable update module addresses. In Fig. 6, a general setting for coupling the SDRAM and the memory controller is described as a memory system 1600. The memory system 1600 includes a memory controller 1610 and a memory module 1620. The memory module 丨 62 〇 includes one or more SDRAM devices coupled in a single or multiple rows of memory devices in accordance with an embodiment of the present invention. The memory controller 16 1 provides command (com), automatic update (REF), address (ADD), and module address (BA) signals to the SDRAM device on the memory module 1620. The data is provided to the memory module 1620 on the data line Din, and the material is received from the memory module 162 on the data line Dout (the lines Din and Dout can be the same line, only 101313.doc is allowed at any given time) 1277982 The controller 1610 and the module 162G move the line. The embodiment according to the present invention illustrates how to operate the memory of the graph for three non-^^^, case 2, and case 3. A different auto-update sequence is used in the parent case. Recording state 1610 knows which modules have the in-progress system and will soon be requested for memory access:; = out: when some new commands are ordered, remember dragon (four) (four) choose - fish, the module is not currently 2 It will not need to be taken before the automatic update command is completed for the module. This allows the least noticeable party when necessary: Operation. Beginners and newcomers Those skilled in the art will recognize that many other device clock changes are conceivable and many design parameters are not discussed. For example, (4) has been used - independent external automatic update signal line, but the automatic update command can also be decoded from the specific combination determined on the - command bus. Each of the four embodiments described can be combined with other embodiments. The particular circuits described and illustrated in the figures are merely illustrative, and in most cases other circuits may achieve the same or similar functions. Such minor modifications and implementation details are included in the embodiments of the present invention, and 1 is intended to fall within the scope of the patent application. The foregoing embodiments are illustrative. Although the specification may be presented in several places, "an", "an", "another" or "some" embodiment, this does not necessarily mean that each such reference is corresponding to the same embodiment. Or the feature is only applied to a single embodiment. [Simplified Schematic Description] 101313.doc 1277982 FIG. 1 illustrates, in block diagram form, a synchronous dynamic random access memory (SDRAM) device according to a first embodiment of the present invention; 2 illustrates, for example, an update module address counter useful in the FIG. ii SDRAM device; FIG. 3 includes, for example, a block diagram of a module address decoder useful in the SDRAM device of FIG. 1; FIG. 4 depicts FIG. FIG. 5 is a block diagram of a jg DRAM device in accordance with a second embodiment of the present invention; FIG. 6 illustrates, for example, an update module address counter useful in the SDRAM device of FIG. 5; 7 shows a circuit for a module address latch as used in FIG. 6; FIG. 8 depicts another update module address counter useful for embodiments of the present invention; FIG. 9A illustrates the update shown in FIG. Start detection/latch Internal organization of the road; 'Figures 9B and 9C show two possible update start detection circuits useful in the update start detection/latch circuit of Figure 9A; the figure contains an embodiment fixed in accordance with one embodiment of the present invention A timing diagram of an automatic update operation of the initial module address; the figure illustrates a further _sdram device in accordance with an embodiment of the present invention; and FIGS. 12 and 13 show that the m implementation allows the _programmed module address to be used as Circuit replacement for the final module address; 10I313.doc -21 · 1277982; Figure 14 A shows the useful option for stylizing a final module address. Figure 14B illustrates the stylization of a final module address. Useful mode temporary set circuit; sub-figure 14C illustrates an electronically configurable fuse circuit useful for stylizing a final module address; Figure 14D illustrates a refinery circuit useful for stylized _ final module address Figure 15 contains a timing diagram of an automatic update operation in which the final module address is fixed in accordance with one embodiment of the present invention; Figure 16 depicts a memory system in accordance with one embodiment of the present invention, and Figure 17 shows a memory system in accordance with the present invention. An embodiment may be Examples of different command sequences implemented by the memory system. [Main component symbol description] 1,8, 16, 24 Automatic update cycle time 10 Memory cell array 1〇_1 to 10-n Memory cell array module 12 address Decoder circuits 12-1 to 12-n column address decoder 14 row address decoder circuits 14-1 to 14-n row address decoder 16, 516, 816 update module address counter 18 update address counter 20 address latch 22 module address decoder 101313.doc -22- 1277982

24 command decoder 26 selector 28 data input circuit 30 data output circuit 100, 500 SDRAM device 200 counting circuit 200-1, 200-2, 200-3, 800-1, 800-2, 800-3 T flip-flop 610 First reverse OR (NOR) gate 612 Second NOR gate 614 Third NOR gate 710 Transfer gate 740, 930 Transistor 800 Counting circuit 810 Reset circuit 820 Update start detection/latch circuit 900 Update start detection Circuit 910 Switch 920 Latch 960, 962, 964 Reverse or (NOR) Gate 1100 SDRAM Circuit 1116 Update Module Address Detector 1220 m Input / m Output Transfer Gate 1300 Comparator 101313.doc -23- 1277982

1320 Module Address Register 1340 Switch Vertical and Horizontal Structure 1400 Programmable Module Selector 1410a, 1430a Contact 1420a Pad 1450 Mode Register Group Circuit (MRS) 1600 Memory System 1610 Memory Controller 1620 Memory Module A0, A7 latch output ACT active command signal ACU address count refresh signal ADD external address signal Ai external address line BA external module address signal BAO, BA1, BA2 module address signal <BA0, BA1 , BA2> The output of the binary module address BAL 820 written in the program BAL0-BAL7, 1330 module address latch ba module address ba1 to ban module selection signal BankO to Bank7 module BL bit Line 101313.doc -24- 1277982 CASE1, CASE2, CASE3 Case 1, Case 2, Case 3 cadd Line address COM External command signal din Write data signal dout Read data signal F13F2 Electric fuse F3 Laser cutting fuse 11 ,12, 622, 720, 725, 950, 990, 1210, 1440a Inverter MC Memory Unit MRSl_MRSn Melt Output NA1, NA2, 620, 730, 940, 970, 980 Reverse (NAND) Gate Ql, Q2, Q3 200 Update output column address RADD RASB, CASB, WEB MRS input of radd 1450, radda column address

RD REF RESET START SEL SEL1 to SELn VCCH Read command signal Automatic update command signal Reset signal Start signal Select signal Select line Delay control voltage 101313.doc -25- 1277982

Vcc lead frame WL word line WR write command signal

101313.doc -26-

Claims (1)

Ϊ 277982 X. Patent application scope: ' ι· A synchronous memory device, comprising: a plurality of n independently addressable memory cell array modules each having a module address; an update address generator For designating a current update column to all memory cell array modules; a module address circuit for receiving an externally provided module address for an update operation and applying the update operation to the pair The current update column of the memory cell array module of the module address _; and an update module address counter for arranging the update operation to 4 dedicated number of block cells array modules When the current update column in each of the ones is updated, a message is sent to the update address generator to generate a new update column. 2. The memory device of claim 1, wherein the update module address counter counts an update cycle, and when the counter reaches an integer multiple of n, signals to the update address generator to generate the new Update column. 3. The memory device of claim 1, wherein an update cycle is initiated by an external update command signal. 4. The memory device of claim 1, wherein an update cycle is initiated by an internal update command signal. 5. The memory device of claim 1, wherein one of the module addresses is assigned to be a starting module address, the update module address counter is received outside of an update operation Reset when the initial module address is provided. 6. The memory device of claim 5, wherein the update operation of the current update column in each of the plurality of memory 101313.doc I277982 array modules is received from a memory controller The externally provided starting module address. The memory device of claim 1, wherein one of the module addresses is assigned as a final module address, and the update module address counter is received outside of an update operation When the final module address is provided, a signal is sent to the update address generator to generate the new update column. • The memory device of claim 1, wherein n is equal to 2 m, and the update module address counter includes an m-level counter. 9. The memory device of claim 8, wherein the (five) stage counter comprises a first flip-flop that receives the update command signal and generates a first output signal to the address counter to refresh the signaling circuit; a flip-flop that receives the first output signal and generates a second output signal to the address counter refresh signaling circuit; and a second flip-flop that receives the second output signal and generates a third φ The output signal to the address counter refreshes the signaling circuit. 0. The memory device of claim 1, wherein the update module address counter comprises: n module address latches corresponding to the n memory cell array modules, when an update is to be performed When the operation is addressed to the corresponding memory cell array module, the update module address counter is set to a corresponding module address latch; and the address counter refreshes the signaling circuit, which is used when all n When the module address latches have been set, the signals are sent to the update address generator and 101313.doc 1277982 resets the n module address latches. 11. The memory device of claim 1, wherein each of the n module address latches comprises a .-transmission gate for receiving a corresponding one of the n module selection signals a signal; a gate enable logic for enabling the transfer to be turned off during the "update operation" of the latch; a latch circuit for storing the logic value of the module select signal; and A reset circuit 'resets the latch circuit based on receiving a signal from the money counter refreshing the signaling circuit. For example, in the memory device of claim 11, each of the n module address latches includes a logic circuit, and the logic circuit receives the update command signal and the module address latch An output signal is generated and a control is generated to the gate terminal of the transmission gate. 13. The memory device of claim 1, wherein the update module address counter comprises: an initial (four) latch circuit for enabling an update module when receiving the first-out-provided module address a bit count; and a reset circuit for addressing the update operation to the plurality of registers. The module address count is turned off after the current update column of each of the hidden single TL array dragon groups. 14. The memory device of claim 13, wherein the first externally provided module address is any valid module address. 15. The device of claim 14, wherein the initial detection latch circuit comprises: 〇R logic for receiving 11 module selection signals, each module selecting 101313.doc 1277982 汛唬 不 不 不 不 不 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 针对 不 不 不 不 不 不 不 不 不 不 不 不The (10) logic output and the -update operation signal are ANDed during the update operation. 16: 17. 18. The memory device of claim 13, wherein the first externally provided module is a predetermined module address, and the initial detection latch circuit comprises a logic 2 circuit to receive the The module address is scheduled and the update command signal. The initial detection latch circuit includes: an AND logic for providing a predetermined module address as a module address for an update operation, Generating a start pulse during the update operation; an initial latch for latching the output of the AND logic; a switching circuit for latching the start pulse to the start lock In the memory, the output of the AND logic is disconnected from the start latch; and the ° reset logic is used to reset the start latch based on the output of the reset circuit. A synchronous memory device, comprising: a plurality of n independently addressable memory cell array modules each having a module address; an update address generator for all memory cell array modules Specifying a current update column; 101313.doc 1277982 a module address circuit for receiving an externally provided module address for an update operation and applying the update operation to the corresponding module address The current update column of the memory cell array module; and an update module address detector for addressing each of the plurality of delta recall cell array modules when the update operation is addressed When the current update column is in the middle, the signal is sent to the update address generator to generate a new update column, and the update module address detector receives an update command signal and a current module address. 19. The memory device of claim 18, wherein the update module address predator comprises: a temporary register for storing a predetermined final module address; and a comparison descent for comparing the current mode The group address is the final module address, and the signal is sent to the update address generator when the current module address matches the final module address. 20. The memory device of claim 19, wherein the register comprises a fixed predetermined final module address. The device of claim 19, wherein the register comprises: a module address selection register comprising a fixed module address; a squat selector for the module The address selection register selects one of the fixed module addresses; and ▲ a latch 'used to hold the selected fixed module address as the final module address. 22. The memory device of claim 19, further comprising a mode register group' wherein the final module address is stylized by the mode register set force 101313.doc 1277982. 23. The memory device of claim 19, wherein the final module address is programmable by a lysis circuit. 24. The memory device of claim 19, wherein the final module address is programmable by a mask option. 25. The memory device of claim 19, wherein the final module address is programmable by a join option. 26. The memory device of claim 8, further comprising an external update signal input terminal' wherein an update operation is initiated by externally determining the update signal. 27. The memory device of claim 18, further comprising a command decoder for receiving an external command, the command decoder being responsive to the plurality of commands received by the command decoder to generate an internal update signal. 28. A memory system, comprising: at least one memory unit having n memory modules and a module addressable automatic update operation, the memory unit including an automatic update circuit, the automatic update circuit pair An automatic update operation is performed in one of the modules updated in an automatic update operation until all of the n modules have been addressed in at least one automatic update operation corresponding to the update column; and a controller To determine an active command and provide an external update module address signal to the memory unit, the controller has a standard automatic update mode that provides all n modes in n consecutive automatic update operations The group address signals are provided, and all n module address signals are provided in subsequent n consecutive automatic update operations. 101313.doc 1277982 29. The request item batch memory system, wherein the η sequence of the n module bits provided in a continuous automatic update operation is controlled to reduce the simultaneous sequence with the memory unit conflict. In effect 30. The memory system of claim 28, the body module and the controller is in the controller. Wherein the memory unit is a memory under the control of an external processor 3 1 • The memory system command signal of claim 28 is forwarded to the automatic update operation on this memory. The eighth central controller will have an external update list 7L to start a memory system in the memory unit 32. The memory unit of claim 28, wherein the memory unit generates an internal update command signal to initiate a memory in the memory. The automatic update operation on the body unit. 33. The memory system of claim 28, wherein the memory unit is an integrated body 34. The memory system of claim 28, wherein the memory controller is integrated On a processor. 35. A method of operating a synchronous memory device having a plurality of memory cell array modules, the method comprising: receiving an external update module address; and corresponding to the external update The current column of one of the memory cell array modules of the module address performs an automatic update operation; and when the automatic update operation has been performed on the current column of each memory cell array module, the current column is refreshed to a new column 101313.doc 1277982 36. If the volume of the branch of the request 1|35 is T-field, the sub-package of the parent-memory cell array module: refresh the current column to -new when performing the automatic update operation The number of automatic update operations that have been performed; and the modulo two::: from: the number of update operations is equal to the memory cell array, such as request = party new current column to the new column and reset the count. The group that has been slammed into the group has a list of the parent-memory unit smashing modules: j仃 仃 automatic update operation to refresh the current column to a new array of memory unit array module which memory unit | 丨夕丨』稹The current 丨 of the group - when the automatic update operation has been performed for each body; and the dynamic update; r your main heart - the current column of the array module is executed from 38. If the request is 2: the new: when: column And restart the memorial. /, Zhongdang has opened every _ ancient _ f army open p fish million, gentleman for:::: one by one brush =:::: for receiving, the final module bit At 391, the method of claim 38, wherein the predetermined final module address is a programmable group = t before == 'where the per-memory cell array module is packaged: "When the update operation is refreshed, the refresh Forefront to - new when accompanied - automatic update operation received - scattered start module address 10l313.doc 1277982 ' Start the automatic update operation on this new column. 41. A synchronous memory device, comprising: a plurality of independently addressable memory cell array modules; an update address generator configured to specify a current update column shared by all memory cell array modules; An means for externally addressing an update operation to a portion of all of the plurality of memory arrays of the memory array module; and for addressing the update operation to the plurality of memory The cell array, and the parent node, when the column is currently updated, sends a signal to the update address generator to generate a new update column component. 42. A synchronous memory device, comprising: a plurality of n independently addressable memory cell array modules each having a module address; an update address generator for all memory The unit array module specifies a current update column; a module address circuit for receiving an externally provided module address for an update operation, and applying the update operation to the corresponding module address The memory unit array module; and an update module address counter for signaling when the update operation is addressed to the current update column in each of the plurality of memory cell array modules Up to the update address generator to generate a new update column, the update module address counter includes an update start debt/latch circuit, the update start detection/latch circuit in the new update column After generating 101313.doc 1277982 'when receiving the predetermined starting module address as the module address of the m new operation', start the update module address counter to start the update for the new update column Operation count. 43. A type of synchronous memory device, comprising: a plurality of n independently addressable memory cell array modules, each having a module address; updating address generation for use in all memory cells The array module specifies a current update column; the module address circuit is configured to receive an externally provided module address for an update operation and apply the update operation to the memory unit of the (four) group address An array module; and an update right group address counter, configured to send a signal to the update address when the update operation is addressed to the current update column in each of the plurality of memory cell array modules Generating a generator to generate a new update column, the update module address counter including a module address for comparing an update operation with a predetermined final module address and for use in an update operation The circuit that generates the rfl number when the group address is equal to the predetermined final module address. 101313.doc 10-