JP4912613B2 - Semiconductor memory device having automatic refresh function for specific bank - Google Patents

Description

  The present invention relates to a DRAM semiconductor device and system, and more particularly, to an apparatus and method having a bank-by-bank automatic refresh operation for a specific memory bank of a multi-bank.

  DRAM devices are generally known widely and are often found in digital systems where digital memory with read / write functions is required. The name of the DRAM device is that the data of each memory cell is periodically refreshed, otherwise the stored data disappears. Current synchronous DRAM (Synchronous DRAM) devices generally use an auto-refresh mode, and the auto-refresh operation refreshes position rows in the DRAM memory cell array during each time period under the control of an external memory controller. The internal refresh row counter increases the number of rows by continuous automatic refresh operation, and returns to the top row of the memory array when the last row is reached. Thus, the DRAM memory controller generates an autorefresh command so that all rows can be refreshed within a specified maximum time for the array to hold stable data.

Many SDRAM devices have a multi-bank memory, and upper row address bits that determine which bank is to be operated are supplied to the SDRAM. US Pat. No. 5,627,791, registered by Wright et al., Describes such a device. The write device uses the upper row address bits to enable an automatic refresh operation for individual banks. The write memory controller designates each bank at the minimum rate required to maintain data safety.
US Pat. No. 5,627,791

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having an improved capability with added flexibility as compared with a conventional Per-Bank Refresh (PBR) SDRAM device.

  The refresh address generator of the present invention is shared by a plurality of memory banks. The bank address circuit receives a bank address supplied from the outside for the refresh operation, and supports the refresh operation for the current refresh row in the memory cell array bank corresponding to the bank address. The refresh bank address counter uses one of several methods described below to determine when the refresh address generator will increment as a new refresh row. This allows the memory controller to have flexibility in predicting which memory bank to perform an auto refresh operation when a read / write operation is in progress on each separate memory bank, The automatic refresh operation for the refresh row can be changed.

  The present invention can generate refresh addresses for a plurality of memory banks with a simple circuit configuration and method. In addition, the memory system for the semiconductor memory device of the present invention has an internal write / read operation and refresh I operation in response to a command signal and a refresh control signal for continuously authorized write or read operation. Can be performed at the same time.

  FIG. 1 is a block diagram showing a configuration of an SDRAM device 100 according to the first embodiment of the present invention. Memory cell array 10 includes a plurality of memory cell array banks 10-1 to 10-n. Here, n is a number larger than 1 and is generally a multiplier of 2. Each bank includes a plurality of memory cells MC, and each memory cell MC is connected to one of a plurality of bit lines BL and one of a plurality of word lines WL.

  The row address decoder 12 circuit selects one of the word lines for each memory operation based on the received row address radda. The row address decoder 12 circuit includes a plurality of row address decoders 12-1 to 12-n, and the row address decoders 12-1 to 12-n connect word lines in the memory cell array banks 10-1 to 10-n. Activate. The plurality of bank selection signals ba1 to ban determine the row address decoders 12-1 to 12-n that receive the row address radda.

  The column address decoder 14 circuit selects a bit line to be read or written during a memory read / write operation based on the column address cadd. The column address decoder 14 circuit includes a plurality of column address decoders 14-1 to 14-n, and each column address decoder 14-1 to 14-n activates a bit line in each memory cell array bank 10-1 to 10-n. Make it.

  The refresh bank address counter 16 receives an auto-refresh command signal REF supplied from the outside, and an address count update (ACU: Address Count Update) input to the refresh address counter 18 when a new refresh row address must be generated. ) Activate the signal. The refresh address counter 18 supplies the current refresh row address RADD to the selector 26. That is, when the SDRAM device 100 is configured as eight banks, the refresh bank address counter 16 receives the eighth external auto-refresh command signal REF once for each memory bank. Later, the address count update ACU signal is activated. After the address count update ACU signal is activated, the current refresh row address RADD is updated to the next refresh row address RADD by the refresh row of the memory cell that must be refreshed during the next refresh period. Such a process is continuously repeated during the refresh operation.

  The address latch 20 receives a plurality of external address signals ADD and a plurality of external bank address signals BA. The interpretation of the address signal ADD and the bank address signal BA is determined by the external automatic refresh command signal REF, the active command signal ACT, the write command signal WR, and the read command signal RD. When the active command signal ACT is received, the address signal ADD is latched, and the row address radd is supplied to the selector 26 in order to activate the word line corresponding to the row address radd in the selected memory bank. The bank address signal BA is latched and supplied to the bank address decoder 22 as the bank address ba of the selected memory bank. When a read RD or write command signal WR is received, the address signal ADD is latched and supplied as a column address cadd to the column address decoder 14 circuit (a bank address signal BA is also possible). When the automatic refresh command signal REF is received, the bank address signal BA is latched and supplied to the bank address decoder 22 as the bank address ba.

  The bank address decoder 22 decodes the bank address ba in order to generate an appropriate bank selection signal for the groups ba1 to ban.

  The command word decoder 24 receives the external command signal COM, and generates command signals such as an active command signal ACT, a write command signal WR, and a read command signal RD in response thereto.

  The selector 26 selects one from the current refresh row address RADD and the output radd of the address latch 20 in order to supply the row address radda to the row address decoder 12 circuit. Then, the automatic refresh command signal REF is supplied as a selection signal to the selector 26 (when the automatic refresh command signal REF is activated, the row address RADD is selected, and when it is deactivated, the output radd of the address latch 20 is output). Selected).

  When the write command signal WR is activated, the data input circuit 28 inputs the write data signal Din from the external data bus and supplies the write data signal din to the memory cell array bank selected corresponding to the bank address BA. . When the read command signal RD is activated, the data output circuit 30 receives the read data signal dout from the memory cell array bank selected in response to the bank address BA and supplies the read data signal Dout to the external data bus. . The operation of the SDRAM device 100 can be described in more detail from the following drawings.

  FIG. 2 shows an embodiment of the refresh bank address counter 16. Particularly in this embodiment, n = 8, assuming that there are 8 banks. Count circuit 200 includes three T (toggle) flip-flops 200-1, 200-2, and 200-3, each flip-flop connected to a logic "high" level, an output T, an output QB, and a clock. Contains input CK. Since the clock input CK of the flip-flop 200-1 is connected to the auto-refresh command signal REF, the output QB of the flip-flop 200-1 is toggled by the continuous auto-refresh command word. Since the output QB of the flip-flop 200-1 is connected to the clock input CK of the flip-flop 200-2, the output QB of the flip-flop 200-2 is also toggled every time the automatic refresh command signal REF is received. Is done. Since the output QB of the flip-flop 200-2 is connected to the clock input CK of the flip-flop 200-3, the output QB of the flip-flop 200-3 toggles every four times the automatic refresh command signal REF is received. Is done.

  The outputs of the flip-flops 200-1, 200-2, and 200-3 are supplied to the inputs Q1, Q2, and Q3 of the three-input NAND gate NA1. The output of the NAND gate NA1 is supplied by the input of the inverter I1, and the output of the inverter becomes the output signal ACU of the refresh bank address counter 16.

  The count circuit 200 generates eight consecutive auto-refresh periods, with the output Q1Q2Q3 being subsequently repeated as 000, 001, 010, 011, 100, 101, 110, 111. For example, if the output Q1Q2Q3 of the counter circuit 200 is 000 after the automatic refresh command signal REF is input, the output signal ACU of the refresh bank address counter 16 is activated when the output Q1Q2Q3 becomes 111, and this output signal ACU Causes the refresh address counter 18 to increment the current refresh row. As another example, if the output Q1Q2Q3 of the counter circuit 200 is 101 after the automatic refresh command signal REF is input, the output signal ACU may be activated when the output Q1Q2Q3 becomes 100. .

  FIG. 3 shows the bank address decoder 22 when there are 8 banks as in the assumption of FIG. Three bank address signals BA0 to BA2 are decoded as selection signals ba0 to ba7 for selecting one of the eight banks.

  FIG. 4 is a timing diagram showing the operation of the circuit shown in FIGS. 1, 2, and 3. Looking at the first auto-refresh period 1 in FIG. 4, the external controller supplies the auto-refresh command signal REF, and the bank address BA supplies 000. The output Q1Q2Q3 of the count circuit 200 is 000, and the least significant bit of the refresh row address RADD is 00. During the next seventh automatic refresh period, the memory controller supplies a bank address BA different from 000 to refresh the row addresses 00... 00 in each of the eight banks. In the refresh cycle 8, the output Q1Q2Q3 of the count circuit 200 becomes 111 so that the output signal ACU of the refresh bank address counter 16 is transitioned to logic “high” from the next clock edge. As the output signal ACU transitions to “high”, the refresh bank address counter 16 (FIG. 1) increases RADD, and as a result, the least significant bit becomes 01.

  In refresh cycle 9, 000 of bank address BA is supplied for a new refresh row 00. In the cycles 9 to 16, the bank refresh order is different from the cycles 1 to 8. However, the operation of the refresh bank address counter 16 which generates a signal for causing the refresh address counter 18 to increase the refresh row after the eighth refresh operation is performed on the current refresh row is not changed.

Figure 5 is a block diagram showing the structure of a SDRAM according to a second embodiment of the present invention, the refresh bank address counter 16 is replaced by refresh address counter activation 516. Refresh address counter activation unit 516 receives the auto-refresh command signal REF and the external bank address BA. Thus, refresh address counter activation 516 before the refresh address counter is counting is to be performed an automatic refresh operation for all banks (eg, one is duplicated eight times or more refresh operations This is also the case when the is required).

Figure 6 shows a detailed configuration of the refresh address counter activation device shown in FIG. A plurality of bank address latches BAL0-BAL7 constitute a register so that each decoded bank address ba0-ba7 is processed during the automatic refresh operation. The first NOR gate 610 combines the outputs of the bank address latches BAL0, BAL1, and BAL2. The second NOR gate 612 combines the outputs of the bank address latches BAL3, BAL4, and BAL5. The third NOR gate 614 combines the outputs of the bank address latches BAL6 and BAL7. The outputs of NOR gates 610, 612, and 614 are provided to the input of NAND gate 620. The output of the NAND gate 620 is supplied as an address count update signal ACU to the refresh address counter 18 via the inverter 622.

  When the operation is performed, each of the bank address latches BAL0 to BAL7 outputs a logic “high” value until a refresh operation for the corresponding memory bank is performed. Each NOR gate 610, 612, and 614 generates a logic low output while each bank address latch BAL0-BAL7 stores a refresh operation related to the corresponding memory bank. Accordingly, NAND gate 620 and inverter 622 maintain the address count update signal ACU at a logic low until the NOR gate receives a signal that any address bank latch has saved the auto-refresh operation with the corresponding bank address. That is, the address count update signal ACU is activated after the refresh operation is enabled for the same refresh row address in all banks.

  FIG. 7 is a circuit diagram showing a detailed configuration of bank address latches BAL0 and BAL7. In the bank address latch BAL0, the transfer gate 710 receives the input ba0 and supplies an output to a latch composed of two inverters 720 and 725. The output of inverter 720 provides latch output A0 and provides input to inverter 725. Inverter 725 is fed back and connected to the input of inverter 720 to maintain the latch value.

  The latch output A0 is supplied as one input to the NAND gate 730, and the other input receives the auto-refresh command signal REF. The output of NAND gate 730 is connected to the “low” enable transfer input of transfer gate 710 and is connected to the “high” enable transfer input of transfer gate 710 via inverter 735. The address count update signal ACU drives the transistor 740 connected between the latch input and the ground voltage.

  During operation, when the address count update signal ACU is activated, the transistor 740 is turned on, causing the input of the latch 720 to be “low” and the latch 720 output A0 to be “high”. When the output A0 of the latch 720 is “high”, the NAND gate 730 receives the remaining input from the auto-refresh command signal REF and generates an output in response thereto. When both the latch output A0 and the automatic refresh command signal REF are “high”, the output of the NAND gate 730 becomes “low” and the transfer gate 710 is activated. When the transfer gate 710 is activated, the input ba0 is transferred to the input of the latch 720. In such an environment, the latch changes state, and when input ba0 is "high", it switches output A0 to "low" to indicate that an automatic refresh operation has been requested for bank 0. Thus, once latched and output A0 goes "low", NAND gate 730 will not respond to additional auto-refresh cycles after every bank has been addressed until address count update signal ACU resets the latch.

8, as another embodiment, showing a refresh bank address counter 816 that can replace the refresh address counter activation 516. Compared to counting each refreshed bank according to the order in which the refresh bank address counter 516 is latched, the refresh bank address counter 816 operates in a different manner. The refresh bank address counter 816 does not start counting the refresh period until a start bank address predetermined according to the automatic refresh command is received. Then, the counter is reset after counting eight refresh cycles, and waits for a start bank address and another automatic refresh instruction word. For example, in one embodiment, if bank 0 is designated as the start bank and the memory controller activates bank 0 during an auto-refresh operation, the remaining seven banks are processed in any order and auto-refreshed. The row then proceeds and the device will wait for another auto-refresh in bank 0 to begin counting again. One advantage of this embodiment is that when the automatic refresh command signal REF is activated together with the bank address 0, the memory controller can control when the refresh operation starts in each row.

  In FIG. 8, the refresh bank address counter 816 includes a count circuit 800, a reset circuit 810, a refresh start detection / latch circuit 820, two NAND gates NA1 and NA2, and two inverters I1 and I2. The refresh start detection / latch circuit 820 receives a bank address BA and an automatic refresh command signal REF from the outside. When a predetermined start bank address is received at bank address BA together with automatic refresh command signal REF, refresh start detection / latch circuit 820 activates output signal BAL.

  The output signal BAL and the auto refresh command signal REF are input to the NAND gate NA2, and when the output signal BAL is activated, the output of the NAND gate NA2 responds to the auto refresh command signal REF. The inverter I2 inverts the output of the NAND gate NA2 and supplies the inverted signal to the count circuit 800.

  Count circuit 800 includes three T flip-flops 800-1, 800-2, and 800-3, each of which has an input T, an output QB, and a clock input CK connected to a logic “high”. Including. Since the clock input CK is connected to the output of the inverter I2 in the flip-flop 800-1, when the start bank address and the auto refresh command signal are received, the output QB is toggled by the continuous auto refresh command signal REF. . Since the output QB of the flip-flop 800-1 is connected to the clock input CK of the flip-flop 800-2, the flip-flop 800-2 receives the automatic refresh command signal REF after the output signal BAL is activated. The output QB is toggled every double time. Since the output QB of the flip-flop 800-2 is connected to the clock input CK of the flip-flop 800-3, the flip-flop 800-2 receives the automatic refresh command signal REF after the output signal BAL is activated. The output QB is toggled every four times.

  The outputs of the pull rib pull lobes 800-1, 800-2, and 800-3 are supplied to the inputs Q1, Q2, and Q3 of the three-input NAND gate NA1. The output of the NAND gate NA1 is supplied to the input of the inverter I1, and the output of the inverter becomes the output signal ACU of the refresh bank address counter.

  The output signal ACU of the refresh bank address counter is supplied to the reset circuit 810. The reset circuit 810 resets the refresh start detection / latch circuit 820 when the output signal ACU of the refresh bank address counter is activated. When the refresh start detection / latch circuit 820 is reset, the refresh start detection / latch circuit 820 waits for an automatic refresh command signal for a start bank address to start counting for a new refresh row.

  FIG. 9A shows an internal configuration for the refresh start detection / latch circuit 820, which includes a refresh start detection circuit 900, a switch 910, a latch 920, and a transistor 930. The refresh start detection circuit 900 receives the automatic refresh command signal REF and the bank address BA, and activates the START signal when the bank address BA matches the start bank address. The switch 910 receives the START signal and transfers the START signal at the input of the latch 920 when the switch 910 is activated. When the START signal is transmitted to the latch 920, the latch 920 latches “high” and activates the output BAL of the refresh start detection / latch circuit 820. The output BAL is fed back to the switch 910 to deactivate the switch 910.

  When the output (RESET) of the reset circuit 810 is activated, the transistor 930 is activated to make the latch 920 “low”. When latch 920 goes “low”, output BAL is deactivated and switch 910 is activated again in preparation for the next auto-refresh command for the start address.

  9B and 9C show an embodiment of the refresh start detection circuit 900. FIG. In FIG. 9B, the refresh start detection circuit 900 includes a NAND gate 940 and an inverter 950 to implement an AND function. The auto-refresh command signal REF and one decoded bank address (currently ba0 and other bank addresses are possible) are supplied to the input of the NAND gate. When the automatic refresh command signal REF and the decoded bank address ba0 are all “high”, the output of the inverter 950 becomes “high” and is supplied as the START signal.

  In FIG. 9C, the refresh start detection circuit 900 can accommodate any bank address as a start bank address. All eight decoded bank addresses ba0-ba7 are OR'ed by three NOR gates 960, 962, and 964 connected to the inputs of NAND gate 970. The ORed bank address is supplied to the input of the NAND gate 980 together with the automatic refresh command signal REF, and passes through the inverter 990 to generate a START signal. Such a method is similar to the method of FIG. 9B using a single bank address.

  FIG. 10 shows a timing diagram for the memory devices of FIGS. 5, 8, 9A, and 9B. Three different refresh bank address sequences are used for successive refresh rows, with the first sequence being auto-refresh cycles 1-8, the second sequence being auto-refresh cycles 9-16, In order, there is an automatic refresh period 17-24. Each sequence starts with an automatic refresh for bank address 0 (BA000), and activates output BAL to refresh start detection / latch circuit 820. BAL remains in the active state at auto refresh periods 8, 16, and 24, respectively, until eight auto refresh operations are completed. When address count update signal ACU is activated, reset circuit 810 is triggered to reset refresh start detection / latch circuit 820 and output BAL.

Figure 11 shows a second 3 SDRAM according to an embodiment (1100) device of the present invention, refresh address counter activation 516 shown in FIG. 5 is an alternative as refresh address counter activation 1116. Refresh address counter activation unit 1116, during the refresh operation, it operates by activating the address counter update signal ACU each time it receives an end bank address predetermined.

Figure 12 shows an embodiment of a refresh address counter activation 1116. Refresh address counter activation 1116 includes an inverter 1210, a transfer gate 1220 having m- input / m- output, a comparator 1300 and the bank address register 1320. The m lines of the external bank address BA are supplied to the transfer gate 1220. Transfer gate 1220 is controlled by an external auto-refresh command signal REF which is connected to the “high” enable input of transfer gate 1220 and also to the “low” enable input of transfer gate 710 via inverter 1210. Connecting.

  The bank address register 1320 includes a predetermined end bank address and is stored as m bits having the same order as the input of the m bit bank address BA. When the automatic refresh command signal REF activates the transfer gate 1220, the comparator 1300 compares the m-bit bank address BA input with the M bank address register 1320 input. The comparator 1300 activates the address count update ACU signal when the m-bit bank address BA input and the M bank address register 1320 input match.

The bank address register 1320 can be programmed in various ways. A simple but inflexible way is to permanently include a given end bank address in the chip mask design. Several methods with more flexibility than this are described below. For example, it can be programmed with bonding options.

  FIG. 13 shows that any bank address is programmed as an end bank address. The bank address register 1320 includes binary bank addresses BA0, BA1, and BA2 of codes (hard-coded) fixed corresponding to the banks Bank0 to Bank7. The switch crossbar 1340 inputs the bank address of the bank address register 1320 to the bank address latch 1330 in response to one selection signal SEL among the plurality of selection signals SELs generated from the programmable bank selector 1400. Like that. The programmable bank selector 1400 activates one of the switches 1340 by a selection signal SEL indicating a programmed bank.

  Comparator 1300 includes three bank address comparators each responsible for bank addresses BA0, BA1, and BA2. Each bank address comparator performs a binary comparison between one of the bank address lines and the corresponding bit from the bank address latch 1330. All three bank address comparators output a binary result value to the AND circuit, and when all bits are matched, the address counter update ACU signal is activated.

  14A, 14B, 14C, and 14D illustrate a method for setting a programmable bank selector 1400. FIG. In FIG. 14A, the bank selector 1400 is composed of one or more circuits including a coupling pad 1420a and an inverter 1440a. Bond pad 1420a provides bond selection. When bond pad 1420a is coupled to bond pad 1410a connected to Vcc, inverter 1440a does not activate select output SEL for that line, and bond pad 1420a is coupled to bond pad 1430a connected to ground. Inverter 1440a activates select output SEL for that line.

  In FIG. 14B, the mode register three (MRS) 1450 provides n select lines SEL1-SELn. The mode register three 1450 receives an external address line Ai in response to a specific combination of inputs RASB, CASB, and WEB, and decodes an address as a specific mode register instruction word. Different mode register instruction words are used to activate other lines among the selection lines SEL1 to SELn.

  The mode register three 1450 is used to permanently program the end bank address after the SDRAM device is assembled. In FIG. 14C, the mode register three 1450 provides a plurality of fuse-burning outputs MRS1-MRSn. By activating a specific combination of fuse-burning outputs, one of the electrical fuses F1, F2 is permanently cut at each selected line SEL. Each select line SEL is permanently set to “high” or permanently “low” each time the device powers on and off depending on which fuse is blown.

  FIG. 14D shows another embodiment of a programmable bank selector 1400 circuit. FIG. 14D includes a laser-cut fuse F3 that is cut before the device is completed and packaged. The programmable bank selector 1400 circuit relies on the control voltage VCCH to delay the supply voltage from being triggered “high” before it rises above the threshold voltage, so that the power is on until the supply voltage stabilizes. Delay to become. FIG. 14D shows a graph of voltage level over time. When the power is turned on depending on whether or not the fuse F3 can be cut, the selection signal SEL is activated or deactivated.

  FIG. 15 shows a timing diagram for the embodiment of FIGS. 11-14D. The end bank address 111 is selected for comparison with the external bank address by the selected method. The SDRAM 1100 continues to refresh the bank for the same row in which the auto refresh command signal and the end bank address 111 are received (auto refresh periods 8, 16, and 24). When the end bank address 111 is received, a refresh command is executed and the refresh row increases. The current order at other bank addresses is not a consideration. In fact, the refresh row may be increased even if the processing is not completed in any bank with respect to the refresh row applied to this circuit.

  Assume that each of the SDRAM devices described above has a memory controller with the ability to provide an acceptable refresh bank address order. FIG. 16 illustrates a general combination of SDRAM and memory controller as a memory system 1600. The memory system 1600 includes a memory controller 1610 and a memory module 1620. The memory module 1620 includes one or more SDRAM devices in which memory devices are combined in a single row or multiple rows according to an embodiment of the present invention. The memory controller 1610 supplies a command signal COM, an auto refresh command signal REF, an address signal ADD, and a bank address signal BA to the SDRAM device of the memory module 1620. Data is supplied to the memory module 1620 via the data line Din, and data is received from the memory module 1620 via the data line Dout. The data lines Din and Dout are also the same line and are allowed to drive the line at a given time, only one of the memory controller 1610 and the memory module 1620.

  FIG. 17 illustrates three other operation sequences Case1, Case2, and Case3 as a timing diagram illustrating the operation of the memory system illustrated in FIG. In each operation order, different automatic refresh orders are used. The memory controller 1610 knows in which bank the memory access is in progress and from which memory bank the memory access is requested soon. When an auto-refresh instruction is generated, the memory controller selects a bank that is not currently being accessed and does not need to be accessed before the auto-refresh instruction word ends. Such a method allows the automatic refresh operation to be completed most naturally if necessary.

  Those skilled in the art will appreciate that the configuration of the device can be varied in many ways and many design parameters have not been discussed. For example, even though a separate external auto-refresh signal line REF is assumed, auto-refresh instructions can be decoded by a combination of activated instruction buses, and the various features of the described embodiment are different from other implementations. Can be combined with examples. The particular circuits shown and described by the drawings are only examples and can be embodied as other circuits that are generally the same or have similar functions. Some modifications and implementation details are included in the embodiments of the invention and are also within the scope of the claims.

1 is a block diagram showing a configuration of an SDRAM device according to a first embodiment of the present invention. FIG. FIG. 2 is a diagram showing a configuration of a refresh bank address counter included in the SDRAM device shown in FIG. 1. FIG. 2 is a block diagram showing a configuration of a bank address decoder included in the SDRAM device shown in FIG. 1. FIG. 2 is a timing diagram illustrating an operation of the SDRAM device illustrated in FIG. 1. FIG. 5 is a block diagram showing a configuration of an SDRAM device according to a second embodiment of the present invention. Is a diagram showing a configuration of a refresh address counter activation unit included in the SDRAM device shown in FIG. FIG. 7 is a circuit diagram showing a configuration of a bank address latch shown in FIG. 6. It is a figure which shows the other refresh bank address counter used in the Example of this invention. FIG. 9 is a diagram showing an internal structure of the refresh start detection / latch circuit shown in FIG. 8. FIG. 9B is a diagram showing a refresh start detection circuit used in the refresh start detection / latch circuit shown in FIG. 9A. FIG. 9B is a diagram showing a refresh start detection circuit used in the refresh start detection / latch circuit shown in FIG. 9A. FIG. 5 is a timing diagram showing an automatic refresh operation when a start bank address is fixed in an embodiment of the present invention. It is a block diagram which shows the structure of the SDRAM apparatus by 3rd Example of this invention. FIG. 4 is a circuit diagram that allows a programmable bank address to be used as an end bank address in an embodiment of the present invention. FIG. 4 is a circuit diagram that allows a programmable bank address to be used as an end bank address in an embodiment of the present invention. FIG. 6 is a diagram illustrating a coupling selection circuit used to program an end bank address. It is a figure which shows the mode register set circuit used for programming an end bank address. FIG. 5 illustrates an electrically configurable fuse used to program an end bank address. FIG. 3 is a diagram showing a laser cut fuse used to program an end bank address. FIG. 6 is a timing diagram illustrating an automatic refresh operation when an end bank address is fixed in an embodiment of the present invention. It is a block diagram which shows the structure of the memory system by the Example of this invention. FIG. 6 is a diagram illustrating another example of an instruction sequence that can be implemented in the memory system according to the embodiment of the present invention.

10-1: Memory cell array (bank 1)
12-2: Row address decoder 14-1: Column address decoder 1 6: Refresh bank address counter
516, 1116: Refresh address counter activator 18: Refresh address counter 20: Address latch 22: Bank address decoder 24: Command decoder 26: Selector 28: Data input circuit 30: Data output circuit 810: Reset circuit 820: Refresh stat Detection / latch circuit 1300: Comparator 1320: Bank address register 1330: Bank address latch 1340: Switch 1400: Programmable bank selector 1610: Memory controller 1620: Memory module BAL0-7: Bank address latch

Claims (22)

N independently addressable memory cell array banks with respective bank addresses;
A refresh address counter activator that activates an address count update signal by detecting that an nth refresh command signal is applied from the outside via a refresh control terminal;
A bank address for receiving n different bank addresses sequentially supplied from the outside together with the refresh command signal for a refresh operation and supporting a refresh operation for a current refresh row of the memory cell array bank corresponding to the bank address Circuit,
A refresh address counter for designating a current refresh row for all memory cell array banks in response to the activated address count update signal;
With
The refresh address counter activator counts refresh cycles,
The synchronous memory device, wherein the refresh address counter is operated to generate the new refresh row when the integer multiple of n is reached. N independently addressable memory cell array banks with respective bank addresses;
A refresh address counter activator that activates an address count update signal by detecting that an nth refresh command signal is applied from the outside via a refresh control terminal;
A bank address that receives n different bank addresses sequentially supplied from the outside together with the refresh command signal for a refresh operation and supports a refresh operation for the current refresh row of the memory cell array bank corresponding to the bank address Circuit,
A refresh address counter for designating a current refresh row for all memory cell array banks in response to the activated address count update signal;
With
The refresh address counter activator counts refresh cycles,
When the integer multiple of n is reached, the refresh address is generated to generate the new refresh row.
Operate the less counter,
The synchronous memory device, wherein the refresh cycle starts with the refresh command signal. N independently addressable memory cell array banks with respective bank addresses;
A refresh address counter activator that activates an address count update signal by detecting that an nth refresh command signal is applied from the outside via a refresh control terminal;
A bank address that receives n different bank addresses sequentially supplied from the outside together with the refresh command signal for a refresh operation and supports a refresh operation for the current refresh row of the memory cell array bank corresponding to the bank address Circuit,
A refresh address counter for designating a current refresh row for all memory cell array banks in response to the activated address count update signal;
With
The synchronous memory device, wherein the start bank address supplied from the outside is received from a memory controller after a refresh operation relating to a current refresh row in each of a plurality of memory cell array banks is completed. N independently addressable memory cell array banks with respective bank addresses;
A refresh address counter activator that activates an address count update signal by detecting that an nth refresh command signal is applied from the outside via a refresh control terminal;
A bank address that receives n different bank addresses sequentially supplied from the outside together with the refresh command signal for a refresh operation and supports a refresh operation for the current refresh row of the memory cell array bank corresponding to the bank address Circuit,
A refresh address counter for designating a current refresh row for all memory cell array banks in response to the activated address count update signal;
With
One of the bank addresses is designated as an end bank address, and the refresh address counter activator generates a new refresh row by receiving an end bank address supplied from the outside for a refresh operation. Synchronous memory device. N independently addressable memory cell array banks with respective bank addresses;
A refresh address counter activator that activates an address count update signal by detecting that an nth refresh command signal is applied from the outside via a refresh control terminal;
A bank address that receives n different bank addresses sequentially supplied from the outside together with the refresh command signal for a refresh operation and supports a refresh operation for the current refresh row of the memory cell array bank corresponding to the bank address Circuit,
A refresh address counter for designating a current refresh row for all memory cell array banks in response to the activated address count update signal;
With
n is 2m, and the refresh address counter activator includes an m-stage counter. The m-stage counter is
A first flip-flop receiving the refresh command signal and generating a first output signal in an address counter update signal circuit;
A second flip-flop receiving the first output signal and generating a second output signal in the address counter update signal circuit;
The synchronous memory device according to claim 5, further comprising: a third flip-flop that receives the second output signal and generates a third output signal in the address counter update signal circuit. N independently addressable memory cell array banks with respective bank addresses;
A refresh address counter activator that activates an address count update signal by detecting that an nth refresh command signal is applied from the outside via a refresh control terminal;
A bank address that receives n different bank addresses sequentially supplied from the outside together with the refresh command signal for a refresh operation and supports a refresh operation for the current refresh row of the memory cell array bank corresponding to the bank address Circuit,
A refresh address counter for designating a current refresh row for all memory cell array banks in response to the activated address count update signal;
With
The refresh address counter activator
A start detection latch circuit for enabling refresh bank address counting upon receipt of a bank address supplied from the first external;
And a reset circuit for disabling bank address counting after a refresh operation has been performed on the current refresh row in each of all memory cell array banks. The start detection latch circuit includes:
an OR logic that receives an n bank select signal;
AND logic that ANDs the output of the OR logic together with the refresh operation signal during the refresh operation,
8. The synchronous memory device according to claim 7, wherein each bank selection signal indicates that a refresh operation is performed on a corresponding one of the n memory cell array banks for the current refresh row. The first bank address supplied from the outside is a bank address which is determined in advance, the start detection latch circuit comprising: a logic may circuitry for receiving bank address and the refresh command signal the it is previously determined Me The synchronous memory device according to claim 7. The start detection latch circuit includes:
An AND logic that generates a start pulse during the refresh operation when a predetermined bank address is supplied as the bank address for the refresh operation;
A start latch for latching the output of the AND logic;
When a start pulse is latched in the start latch, the start latch
A switch circuit for disconnecting at the output of the ND logic;
The synchronous memory device according to claim 7, further comprising: a reset logic that resets the start latch based on an output of the reset circuit. N independently addressable memory cell array banks each having a bank address;
A refresh address counter activator for designating a predetermined final bank address and activating an address count update signal if a bank address applied via a refresh control terminal matches the final bank address;
During the refresh operation, together with the refresh command signal, n different bank addresses sequentially supplied from the outside are received to support the refresh operation for the current refresh row of the memory cell array bank corresponding to the bank address. A bank address circuit;
A synchronous memory device comprising: a refresh address counter for designating a current refresh row for all memory cell array banks in response to the activated address count update signal. The refresh address counter activator
A register for storing a predetermined end bank address;
The synchronous memory according to claim 11, further comprising: a comparator that operates the refresh address counter when the bank address applied via the refresh control terminal matches the end bank address. apparatus. The register is
A bank address selection register containing a fixed bank address; and
A programmable selector for selecting one of the fixed bank addresses from the bank address selection register;
The synchronous memory device according to claim 12, further comprising: a latch that holds the selected and fixed bank address as the predetermined end bank address. Further comprising a mode register set,
The synchronous memory device according to claim 12, wherein the end bank address is programmable via the mode register set. The synchronous memory device according to claim 12, wherein the end bank address is programmable by a fuse circuit. The synchronous memory device of claim 12, wherein the end bank address is programmable by a mask option. The synchronous memory device of claim 12, wherein the last bank address is programmable by a bonding option. An instruction word decoder for receiving an external instruction;
The synchronous memory device according to claim 11, wherein the command word decoder is capable of generating an internal refresh signal in response to a plurality of commands. In a refresh method for a semiconductor memory device having n (n is an integer of 2 or more) memory cell array banks,
Activating an address count update signal by counting up to n in response to a refresh control signal applied from the outside through a refresh control terminal;
Generating a refresh address in response to the activated address count update signal,
Each of n memory cell array banks selected in response to n different bank addresses sequentially applied from the outside together with the refresh control signal performs a refresh operation in response to the same refresh address,
The address count update signal generation step includes:
Counting up to n in response to the refresh control signal;
And a step of activating the address count update signal when n is counted. A refresh method for a semiconductor memory device, comprising: In a refresh method for a semiconductor memory device having n (n is an integer of 2 or more) memory cell array banks,
Activating an address count update signal by counting up to n in response to a refresh control signal applied from the outside through a refresh control terminal;
Generating a refresh address in response to the activated address count update signal,
Each of n memory cell array banks selected in response to n different bank addresses sequentially applied from the outside together with the refresh control signal performs a refresh operation in response to the same refresh address,
The address count update signal generation step includes:
If the bank address applied together with the refresh control signal is a refresh start bank address, the address count update signal is activated by counting up to n in response to the refresh control signal. Refresh method. The n different bank addresses are:
21. The semiconductor according to claim 20, wherein the refresh start bank address is input first, and the remaining (n-1) bank addresses excluding the refresh start bank address are input regardless of the order. Memory device refresh method. In a refresh method for a semiconductor memory device having n (n is an integer of 2 or more) memory cell array banks,
Activating an address count update signal by counting up to n in response to a refresh control signal applied from the outside through a refresh control terminal;
Generating a refresh address in response to the activated address count update signal,
Each of n memory cell array banks selected in response to n different bank addresses sequentially applied from the outside together with the refresh control signal performs a refresh operation in response to the same refresh address,
The address count update signal stage includes:
Latching the bank address and outputting a bank address latch signal if the bank address is a refresh start bank address;
Outputting the refresh control signal when the bank address latch signal is activated;
Counting up to the n in response to the refresh control signal;
Activating the address count update signal when n is counted;
And a step of resetting the bank address latch signal when the address count update signal is activated.

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