•twf.doc/y 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種顯示面板之驅動，且特別是有關 於一種顯示面板之電荷分享方法與裝置。 - 【先前技術】 - 目1是說明-般顯示器之方塊圖。圖2是說明圖工中 • 3號二？序圖。請同時參照圖1與圖2，在此假設顯示 面板4 nxm顯示面板，其中m、n為整數 垂直同步錢STV與致能信號〇Ε輸出給掃』 於掃描驅動器120中’移位暫存請將所接 rtn步信號STV逐級移位’以便輪出多個掃描信 掃V作：;、二、致旎㈣0E而決定是否透過緩衝器輸出 .便；;' 9 i〜ss(m)給顯示面板140之掃描通道。為方 月’圖2中僅顯示掃描信號SS(1)〜ss(3)。 器插信號之時序，時序控制 鎖信號LP啥資散m數位顯示資料dd與問 丄：=二：步:號：級移位， 貝琥、、、口弟一線閂鎖器132。第一 所輸出之輸 m之全應之通道中。待第—線_ ㈣運均元成一貝料阿鎖後，第二線严-1鎖器】33依 »2Vltwf.doc/y 照時序控制器11 〇所輸出之閂鎖信號L P，而儲存第一線閂 鎖器132所輸出之閂鎖資料。數位類比轉換器134則將第 二線問鎖器133所輸出之數位資料轉換為類比顯示信號 AD(1)〜AD(n)，此顯示信號AD(1)〜AD(n)將透過緩衝器 傳送至顯示面板140之資料通道。為方便說明，圖2中僅 說明顯示信號AD(1)。 為了增進顯示面板140之動態表現，一般均運用極性 反轉技術來驅動顯示面板140。以顯示信號AD(1)為例， f參照圖2，於掃描信號SS⑴致能期間顯示信號AD(1)轉 態$負極性’於掃描信號SS(2)致能期間顯示信號AD(1) 轉悲為正極性，而於掃描信號致能期間顯示信號 AD(1)再次轉態為負極性。上述正極性與負極性是參考共 同電壓VCOM之準位而定義之。顯示信號八以^在正負極 性之間變換時，資料驅動器130必須耗費大量功率。為了 降,資料驅動器所輸出顯示信號之擺幅，以節省耗電，一 般疋採用電荷分享（Charge sharing)技術。 電荷分旱技術是在奇數資料通道與偶數資料通道之間 配，開關SW ’如圖3所示。為方便說明，圖3中僅以第 一貪料通道（提供顯示信號AD(1))與第二資料通道（提 ΐ顯不信號AD(2))為說明例。藉由控制開關SW，而在 、資料通道之顯示信號變換正負極性之前先行將奇數資料通 ^與偶數資料通道彼此短路，使得奇數資料通道與偶數資 料通道得以平均分配電荷，而使奇數資料通道與偶數資料 L道之黾位預先下降（上升）至共同電壓附近。因 6 12770^ twf.doc/y 此’資料驅動器只需使資料通道之電 VCOM附近放電至負極性準位（或充带千1自，、同電壓 亦即降低資料驅動器所輪出顯示信號極，，）， 性反轉所耗電力。 i田進而節省極 圖4是說明傳統電荷分享之訊號時序圖。士 H3與4 ’傳統電荷分享是在閃鎖信號LP 參照 時間實施，亦即每-個奇數資料通道與偶數料^位之 的開關SW會依照閃鎖信號LP之控制，而使相=之間 料通道與偶數資料通道將會先彼此短路 =數資 正負電荷極性中和（即分別從正極性電壓道 VCOM =及從負極性電壓上升到共同電麼。電屢 在問鎖信號LP下緣時開關sw為斷路 。然後 通道與偶數㈣通道之輪㈣騎由να)Μ電^數資料 生）至所需要的負極性（正極性）電廢。如此來降(上 驅動器在驅動資料通道時便不須要由正極性電承^貧料 極性電壓（或從負極性電麗變化到正極性電„到負 ==驅動器對資料通道之輪出電流，達到節= 泊耗之目的。 4即名功率 錯riU於傳統技術是利用所有掃描線禁能项門r” 鎖mp為南準位期間）進 曰1 (鬥 板1斤有晝素均被關閉（turn of^間進行it顯示面 因此傳統技術只能讓相鄰奇數資料線及偶數資科了刀旱， f中電;，，而無法-併使顯^ 何中和，所以使得電荷分享之省電功能大打折扣。忠素電 1.27701㈤y 【發明内容】 本叙、月的目的就是提供一種顯示面板之電荷分享方 法以改善傳統电荷分享（Ch * ) 讓省電功能極大化。 ❹久 置：:¾:的-種顯示面板之電荷分享裝 荷分享方法，其面本發明提出-種顯示面板之電 電荷分享方法包括步驟如下板至=、包含二個資料通道。該 一時間，«料通道之間麻$先，於畫相啟期間之第 二時間，使資料通道之間斷?、;後於-晝素開啟期間之第 顯示信號至顯示面板。，以便使資料通道各自傳送 仗另-觀點來看，本 旱裝置，其中顯示面板包人杈出種顯不面板之電荷分 掃描通道。該電荷分享裝^、二個資料通道與至少一個 動器、至少-開關以及一時描驅動器、一資料驅 接至掃描通道，用以依照制裔。掃插驅動器電性連 f信號’以便控制掃描通道上=號而決定是否輸出掃 裔電性連接至資料通道，用畫素之啟閉。資料驅動 =不化號’以驅動顯示面板。鎖信號而閂鎖並輸出 :，用以依照控制信號而决定”電性連接於 資料^通道之 :序控制器電性連接至開關、：：使資料通道之間短路。 从於晝素開啟期間藉由輪出:，驅動器與掃插驅動器， 死信號控制掃播驅動器而 r f.doc/y 開啟（她⑻掃描通道上所有 期間之第一時間，時戽批剝哭茲山於旦常開啟 μ此序Μ 由控制錢而控制開關， /0:床:運之間紐路，以及於晝素開啟期間之第二時 間，制H藉由控繼號而控制關，使該些資料通 迺之，=以便使資料驅動器分別傳送顯示信號至顯示 面板之負料通道。 傳統電荷分享功能只能讓相鄰資料線上的正負電荷極 f生中淨並热去達到爷、電功能的最佳化。本發明因可以於 畫素開啟顧完成電荷分享，因此本發明不僅可以讓相鄰 貧料通迢上的正貞電荷極性巾和，同時亦能將對應掃描線 上相鄰之奇數與偶數晝素上的正負電荷極性中和，如此將 能有最佳的省電效果。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖5是依照本發明實施例說明具有電荷分享（也紅狀 sharing)功能之顯示器方塊圖。圖中資料驅動器53〇與掃 描驅動器520之實施方式分別可以與圖1中資料驅動器 130與掃描驅動器120相同。圖6是說明圖5中各信號之 時序圖。請同時參照圖5與圖6，在此假設顯示面板54〇 為具有nxm晝素之薄膜電晶體液晶顯示面板（TFT-LCD panel)，其中m、η為整數。 I277〇m4twf.doc/y 時序控制器510輸出垂直同步信號STV與輸出致能信 f 0E給掃描驅動器52〇。掃描驅動器52〇依照輸出致能 k號0E而決定是否輸出掃描信號ss(i)〜ss(m)給顯示面 之掃描通道。在此定義「畫素開啟期間」為每次致 月b佗唬0E為低準位（即輪出掃描信號ss(1)〜ss(m))之 期間。非於晝素開啟期間，掃描驅動器、，關（她〇ff)TWf.doc/y IX. Description of the Invention: [Technical Field] The present invention relates to driving of a display panel, and more particularly to a charge sharing method and apparatus for a display panel. - [Prior Art] - Head 1 is a block diagram showing the general display. Figure 2 is an illustration of the work • No. 3? Sequence diagram. Please refer to FIG. 1 and FIG. 2 at the same time. Here, it is assumed that the display panel 4 nxm display panel, where m and n are integer vertical sync money STV and enable signal 〇Ε output to scan in the scan driver 120 'shift temporary storage, please Shifting the connected rtn step signal STV step by step 'to turn out a plurality of scanning signals to sweep V for:; 2, to 旎 (4) 0E to determine whether to output through the buffer.; '9 i~ss(m) to The scanning channel of the display panel 140. For the square month, only the scan signals SS(1) to ss(3) are shown in FIG. Timing of the signal insertion, timing control Lock signal LP 啥 散 数 数 m m = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The first output of the output is in the channel of the full response. After the first line _ (four) transport equals into a shell material A lock, the second line Yan-1 lock] 33 according to the »2Vltwf.doc / y timing controller 11 〇 output latch signal LP, and save the first The latch data output by the one-line latch 132. The digital analog converter 134 converts the digital data output by the second line lock 133 into analog display signals AD(1) to AD(n), and the display signals AD(1) to AD(n) will pass through the buffer. The data channel is transmitted to the display panel 140. For convenience of explanation, only the display signal AD(1) is illustrated in FIG. In order to enhance the dynamic performance of the display panel 140, the polarity inversion technique is generally employed to drive the display panel 140. Taking the display signal AD(1) as an example, f refers to FIG. 2, and during the enable of the scan signal SS(1), the display signal AD(1) is rotated to the negative polarity. The display signal AD(1) is enabled during the enable of the scan signal SS(2). Turning sorrow is positive polarity, and the display signal AD(1) is again turned to negative polarity during the enable of the scan signal. The above positive polarity and negative polarity are defined by reference to the level of the common voltage VCOM. When the display signal eight is changed between positive and negative polarities, the data driver 130 must consume a large amount of power. In order to reduce, the data driver outputs the amplitude of the display signal to save power, and generally uses charge sharing technology. The charge-distribution technique is provided between the odd data channel and the even data channel, and the switch SW' is shown in FIG. For convenience of explanation, only the first grazing channel (providing the display signal AD(1)) and the second data channel (providing the illuminating signal AD(2)) are illustrated in Fig. 3. By controlling the switch SW, the odd data channel and the even data channel are short-circuited to each other before the display signal of the data channel is converted to the positive and negative polarity, so that the odd data channel and the even data channel can evenly distribute the charge, and the odd data channel and the odd data channel are The clamp of the even data L channel is pre-decreased (raised) to the vicinity of the common voltage. Because 6 12770^ twf.doc/y This 'data driver only needs to discharge the vicinity of the VCOM of the data channel to the negative polarity level (or charge the battery for one thousand, and the same voltage will reduce the display signal of the data driver. ,,), the power consumed by sexual reversal. i Tian and then save the pole Figure 4 is a signal timing diagram illustrating the traditional charge sharing. The H3 and 4' traditional charge sharing is implemented in the flash lock signal LP reference time, that is, the switch SW of each odd data channel and even material bit is controlled according to the flash lock signal LP, so that the phase = between The material channel and the even data channel will be shorted to each other first = positive and negative charge polarity neutralization (ie, from the positive polarity voltage channel VCOM = and from the negative polarity voltage to the common power respectively. When the power is repeatedly asked the lock signal LP lower edge The switch sw is open circuit. Then the channel and the even (four) channel wheel (four) ride by να) Μ electric data generation) to the required negative polarity (positive polarity) electric waste. In this way, when the upper driver drives the data channel, it is not necessary to change the polar voltage of the positive polarity from the positive polarity (or from the negative polarity to the positive polarity) to the negative == the output current of the driver to the data channel. To achieve the purpose of section = parking consumption. 4 Name power riU in the traditional technology is to use all the scanning line disables the door r" lock mp for the south level period) into the 曰 1 (the board 1 kg has been cut off (turn of ^ between the it display surface so the traditional technology can only make adjacent odd data lines and even-numbered resources for the knife drought, f power;,, but can not - and make the display neutral, so the charge sharing The power saving function is greatly reduced. Zhongsu Electric 1.27701 (five) y [Invention] The purpose of this narration is to provide a charge sharing method for the display panel to improve the traditional charge sharing (Ch * ) to maximize the power saving function. A charge sharing load sharing method for a display panel, the present invention proposes that the electric charge sharing method of the display panel includes the following steps to =, including two data channels. The time, the material channel Between the first and the first During the second period of the inception period, the data channel is interrupted, and the first display signal is displayed to the display panel during the opening period of the halogen element, so that the data channels are transmitted separately. The display panel package displays a charge-sharing channel of the display panel. The charge sharing device, the two data channels and the at least one actuator, at least the switch and the one-time driver, and a data drive to the scan channel are used for According to the system of people, the sweep driver electrically connected the f signal 'to control the scan channel on the = number to determine whether to output the sweeping electrical connection to the data channel, using the pixel to open and close. Data drive = not number 'to drive display The panel locks the signal and outputs it: it is determined according to the control signal. “Electrically connected to the data channel: the sequence controller is electrically connected to the switch, and:: shorts the data channel. During the turn-on period, by the wheel: the driver and the sweep driver, the dead signal controls the sweep driver and r f.doc/y is turned on (she (8) scans the first time of all the periods on the channel, when the batch is peeled off Once the μ is frequently turned on, the control switch is controlled by the control, /0: bed: between the transportation, and during the second time during the opening of the element, the control H is controlled by the control number, so that The data is wanted, so that the data driver can respectively transmit the display signal to the negative channel of the display panel. The traditional charge sharing function can only make the positive and negative charges on the adjacent data lines be net and heat to reach the function of the master and the electric. Optimized. The present invention can complete the charge sharing because the pixel can be turned on. Therefore, the present invention can not only allow the positive charge of the adjacent lean material to pass through, but also the odd number adjacent to the corresponding scan line. The polarity of the positive and negative charges on the even halogen is neutralized, so that the best power saving effect will be obtained. In order to make the above and other objects, features and advantages of the present invention more apparent, the preferred embodiments are described below. The details will be described below in conjunction with the drawings. [Embodiment] FIG. 5 is a block diagram showing a display having a charge sharing (also red sharing) function according to an embodiment of the present invention. The embodiment of the data driver 53A and the scan driver 520 in the figure may be the same as the data driver 130 and the scan driver 120 of Fig. 1, respectively. Fig. 6 is a timing chart for explaining the signals of Fig. 5. Referring to FIG. 5 and FIG. 6 together, it is assumed here that the display panel 54A is a TFT-LCD panel having nxm elements, wherein m and n are integers. The I277〇m4twf.doc/y timing controller 510 outputs the vertical synchronizing signal STV and the output enable signal f 0E to the scan driver 52A. The scan driver 52 determines whether to output the scan signals ss(i) to ss(m) to the scan channel of the display surface in accordance with the output enable k number 0E. Here, the "pixel open period" is defined as a period in which the monthly b佗唬0E is a low level (i.e., the scanning signals ss(1) to ss(m) are rotated). Scan driver, off (not 昼 ff) during the start of 昼素
對應之㈣通道上所有錢。為方便制，圖6中僅顯示 掃描信號SS⑴〜SS⑶。 配。掃杬驅動器520輸出掃描信號^(丨）〜％^)之時 ^ ’時序控制器5H)亦輸出水平同步信號STH、數位顯示 貧料D D與閃鎖信號L P給資料驅動器5 3 〇。對一般薄膜電 ，體液晶顯示面板的驅動方式而言，資料驅動器53〇會 _信號LP為低準位時輸出顯示錢AD⑴〜AD⑻，2 掃描驅動器520會在致能作缺^ ^ 铁㈣、 4低準位時輸綺描信 料驅動器530分別輸出顯示信號AD⑴ ⑻至顯不面板54〇對應之資料通道。為方便說明， 圖6中僅說明顯示信號AD。）。 於本實施例中，每一個奇數資料通道與偶數資 =均電性連接-個關。這些開關均依照控静= 而決疋是否使奇數與偶數資料通道之間短 & 施例中將設定控制信號LD與閂鎖，貫 依照本發明之精神，町之為相同信號。 器510,使其輸出之致能信號〇Ε㈣二序控制 或者，使其輸㈣鎖健LP _序落魏信^^Corresponding to (4) all the money on the channel. For convenience, only the scan signals SS(1) to SS(3) are shown in FIG. Match. When the broom driver 520 outputs the scan signal ^(丨)~%^) ^ 'the timing controller 5H) also outputs the horizontal synchronizing signal STH, the digital display lean D D and the flash lock signal L P to the data driver 5 3 〇. For the driving method of the general thin film electric and liquid crystal display panel, the data driver 53 will output the display money AD(1) to AD(8) when the signal LP is at the low level, and the 2 scan driver 520 will be disabled (4). When the low level is low, the input strobe driver 530 outputs the display signals AD(1)(8) to the data channels corresponding to the display panel 54〇. For convenience of explanation, only the display signal AD is illustrated in FIG. ). In this embodiment, each odd data channel is connected to an even number of powers. These switches are in accordance with the control of the static = whether or not to make the odd and even data channels between short & the control signal LD and latch are set in the embodiment, according to the spirit of the present invention, the same signal. 510, the output signal of its output 〇Ε (four) second-order control or, to make it (four) lock health LP _ sequence Wei Wei ^ ^
Ι·277〇1_ 時序控制器510於對庫之蚩本 Ο F㈣# ^ 旦素開啟期間藉由輸出致能信號 tL f請’而使雜轉請開啟 二）對應之#描通道上所有晝素。於晝素開啟期間一 日守間（在此為問鎖作贫了 ρ古 、 ’ 蕤由刚4 τί 回準位期間），時序控制器51〇 敗“❿控制各開關，使奇數與偶數資料通道 1啟朗1二咖（纽胡鎖^ _ y 日守序控制器510藉由控制信號LD而控 制各而使奇數與偶數㈣通道之間斷路，此時資料 驅動裔530_分別傳送顯示信號AD⑴〜ad⑻至顯示面板 540對應之貧料通道。因此’本實施例可同時使資料通道 及相關畫素進行正負極性中和動作（即電荷分享）。非於 晝素開啟期間，時序控制器训控制各開關而使該些資料 通道之間斷路。 而第一貝施例則為修改資料驅動器53〇進行電荷分享 之Η说點’而卩铺信號LP與致能信號qE卿持習知操作 方式。本貝細例中將於圖5中配置一延遲電路(如圖7 所示），用以接收並延遲問鎖信號Lp，以輸出控制信號 LD。此延遲電路700是由多個正反器串接而成。每個正反 态均被糸統時脈CLK所觸發。藉由決定延遲電路7〇〇中正 反器之串接數量，即可以決定延遲電路7〇〇之延遲時間。 本實施例之訊號時序圖可以參照圖8所示。 請麥照圖5、7與8，由於延遲電路7〇〇之延遲，使得 於時序上控制信號LD落後閂鎖信號Lp。於畫素開啟期間 之第一時間，即閂鎖信號LP之下降緣後的一段時間内（此 127701— 時控制4§號1^高準位），時序控制器51〇藉由控制信號 LD而控制各開關，使奇數與偶數資料通道之間短路。於 晝素開啟_之第二時間（在此為控制信號LD低準位期 間），時序控制器510藉由控制信號1〇而控制各開關， 而使奇數與偶數資料通道之間斷路，此時資料驅動器53〇 分別傳送顯不信號AD(1)〜AD(n)至顯示面板540對應之 資料通道。因此，本實施例亦可同時使資料通道及相關畫 素進行正負極性中和動作（即電荷分享）。 控制信號LD之產生並不限於上述諸實施例所採行之 方式，熟習此技藝者當可以任何手段產生控制信號ld。 設計者可以視其需要而決定控制信號LD之寬度（ 電荷分享之時間長）。 仃 綜上所述，本發明因可以於畫素開啟期間完成電荷分 享，因此本發明不僅可以讓相鄰資料通道上的正負電荷極 性中和’同時亦能將對應掃描線上相鄰之奇數與偶=辛 上的正負電荷極性中和，如此可大幅減少料鶴器=於 出電流’使省電功能進一步提昇。 雨 雖然本發明已以較佳實施例揭露如上，然其並非 限定本發明’任何熟習此技藝者，在不麟本發明之 和範圍内’當可作些許之更動與潤飾，因此本發明之= 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是說明一般顯示器之方塊圖。 12 圖2是說明圖1中各信號之時序圖。 圖3是說明在奇數與偶數資料通道之間配置開關之電 荷分享技術。 圖4是說明傳統電荷分享之訊號時序圖。 圖5是依照本發明實施例說明具有電荷分享功能之顯 示器方塊圖。 圖6是依照本發明實施例說明圖5中各信號之時序圖。 圖7是依照本發明實施例說明延遲電路之電路圖。 圖8是依照本發明另一實施例說明圖5中各信號之時 序圖。 【主要元件符號說明】 110 :時序控制器 120 :掃描驅動器 121 :移位暫存器 122 :準位移位器 # 130 :資料驅動器 131 :移位暫存器 132 :第一線閂鎖器 133 :第二線閂鎖器 134 :數位類比轉換器 140 :顯示面板 510 :時序控制器 520 :掃描驅動器 13 ϊ277.〇1_ 530 :資料驅動器 540 ·顯不面板 AD(1)〜AD(n):顯示信號 DD :數位顯示資料 LD :控制信號 LP :閂鎖信號 OE :輸出致能信號 SS(1)〜SS(m):掃描信號 STH :水平同步信號 STV :垂直同步信號 SW :開關 VCOM :共同電壓Ι·277〇1_ The timing controller 510 is in the library 蚩本ΟF(4)# ^ During the turn-on period, by outputting the enable signal tL f please 'mute the turn, please turn on 2) corresponding to all the elements on the channel . During the opening of the day, during the opening of the 昼 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 问 问 问 问 问 问 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序 时序Channel 1 Kailang 1 2 coffee (New Hu lock ^ _ y day control device 510 is controlled by the control signal LD to make the circuit between the odd and even (four) channels, at this time the data drive 530_ respectively send the display signal AD(1)~ad(8) to the poor material channel corresponding to the display panel 540. Therefore, the present embodiment can simultaneously perform positive and negative neutralization actions (ie, charge sharing) on the data channel and related pixels. The switches are controlled to open the data channels. The first example is to modify the data driver 53 to perform charge sharing. The signal LP and the enable signal qE are used in the conventional operation mode. In the present example, a delay circuit (shown in Figure 7) is arranged in Fig. 5 for receiving and delaying the lock signal Lp to output a control signal LD. The delay circuit 700 is composed of a plurality of flip-flops. Made in series. Each positive and negative state The delay time of the delay circuit 7〇〇 can be determined by determining the number of series connection of the flip-flops in the delay circuit 7〇〇. The signal timing diagram of this embodiment can be referred to FIG. Please note that the delay of the delay circuit 7〇〇 causes the control signal LD to lag behind the latch signal Lp at the first time during the pixel on period, that is, the drop of the latch signal LP due to the delay of the delay circuit 7〇〇. After a period of time (this 127701 - time control 4 § 1 ^ high level), the timing controller 51 控制 controls the switches by the control signal LD to short-circuit between the odd and even data channels. The second time when _ is turned on (here, during the low level of the control signal LD), the timing controller 510 controls the switches by the control signal 1 , to open the odd and even data channels, and the data driver 53 at this time. 〇 respectively transmitting the display signals AD(1) to AD(n) to the data channel corresponding to the display panel 540. Therefore, in this embodiment, the data channel and the related pixels can simultaneously perform the positive and negative neutralization actions (ie, charge sharing). Control signal LD production It is not limited to the manner adopted by the above embodiments, and the skilled person can generate the control signal ld by any means. The designer can decide the width of the control signal LD (the length of charge sharing time) according to his needs. According to the present invention, since the charge sharing can be completed during the pixel on period, the present invention can not only neutralize the polarity of the positive and negative charges on the adjacent data channels, but also can also add the odd and even pairs on the corresponding scan lines. Positive and negative charge polarity neutralization, so that the material can be greatly reduced = the current is generated to further improve the power saving function. Although the present invention has been disclosed in the preferred embodiment as above, it is not limited to the present invention. It is to be understood that the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a general display. 12 Figure 2 is a timing diagram illustrating the signals of Figure 1. Figure 3 is a diagram illustrating a charge sharing technique for configuring switches between odd and even data channels. Figure 4 is a timing diagram illustrating the signal sharing of conventional charge sharing. Figure 5 is a block diagram showing a display having a charge sharing function in accordance with an embodiment of the present invention. FIG. 6 is a timing diagram illustrating signals in FIG. 5 in accordance with an embodiment of the present invention. Figure 7 is a circuit diagram illustrating a delay circuit in accordance with an embodiment of the present invention. Figure 8 is a timing diagram showing the signals of Figure 5 in accordance with another embodiment of the present invention. [Main component symbol description] 110: Timing controller 120: Scan driver 121: Shift register 122: Quasi-bit shifter #130: Data driver 131: Shift register 132: First line latch 133 : second line latch 134 : digital analog converter 140 : display panel 510 : timing controller 520 : scan driver 13 ϊ 277. 〇 1_ 530 : data driver 540 · display panel AD (1) ~ AD (n): Display signal DD: digital display data LD: control signal LP: latch signal OE: output enable signal SS(1)~SS(m): scan signal STH: horizontal sync signal STV: vertical sync signal SW: switch VCOM: common Voltage
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