1276145 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種具有鎳矽化物之半導體元件與製作鎳矽化 物之方法，其巾半導體元件之源極/汲極區域之麵具有由石夕化鎳 與-石夕化鎳域之财化物，且上述鎳魏物制用二次快速熱 製程加以製作。 【先前技術】 金屬石夕化物由於具有高雜與低電阻等優點，因此已廣泛地應 用在積體電路的製作上，侧是在現今積體電路的線寬、接觸面 積與接面深鮮都逐親小的情況下，切分半賴元件之閉 極、源極與汲極均需_金屬魏物崎侧極電阻、鋪電阻 (_act resistance)並減少電阻電容延遲效應(Rcde㈣等進而提 尚半導體元件的驅動電流。 金屬石夕化物的製作縣於半導體基底上形成—金屬薄膜，再利 用熱處理方式加以達成。—般而言，金㈣麟儀物理氣相沉 積方式，如級或濺鍍方式，沉積於轉縣底上並覆蓋於欲形 成金屬石夕化物之位置’例如閘極、源極與没極，接著再對金屬薄 膜加熱使其與其所覆蓋之雕以及雜與錄反應，從而形成金 屬碎化物。 。 金屬石夕化齡了具讀述可降侧極電阻、接觸電阻與電阻電 1276145 谷延遲效應之伽外，金射化物在製程上的另—概勢在於其 ’、有自行對準功施。就現行技術而言，自行對準石 (self-align^^ silicide, salicide)6^^i^ffi 〇 明爹考第1圖至第4圖。第1圖至第4圖為習知製作金屬石夕化物 之方法示意圖。如第1圖所示，首先提供-半導體基底10，其上 包含有已製作完成之隔祕12，例如魏化層錢細離，一間 極介電層14、-多晶石夕閘極16設於閘極介電| 14之上、一侧壁 子結構18設於多晶石夕閘極16之側壁，以及源極/没極區域％設於 多晶石夕閘極16與隔離區12之間。 如第2圖所示，接著利用物理氣相沉積方式於半導體基底1〇 上沉積-金屬薄膜22,以覆蓋多晶㈣極16與源極/没極區域2〇。 隨後如第3圖所示，進行一回火製程，以使金屬薄膜22與多晶石夕 閘極16與源極級極區域2G反應，並於多晶㈣極％與源極/沒 極區域20之表面形成金屬矽化物24。最後如第4圖所示，去除未 反應之金屬薄膜22，即完成金屬石夕化物24的製作。 一般而言，用以製作金屬矽化物之金屬薄膜主要包含有鈦、鈷 與鎳等材質，其中二雜鈦雖然具有較低之電阻值(約介於12至 20# Ω-cm)，但由於易產生微細線幅效應(nam)wlinewidth effect) ’因此在積體電路之線寬下降至i8〇nm以下時，其片電阻 (sheetresistance)會產生劇幅上揚的現象。另一方面，二石夕化銘與 矽化鎳之電阻值雖略高於二矽化鈦(二者之電阻值約介於15至如 1276145 ’但由於沒有明顯的微細線幅效應，因此目前廣泛地被 用乍金屬石夕化物之材質，其中鎳更由於在形成相同片電阻的條件 下，所消耗的石夕厚度較始為少，因成為目前金屬石夕化物材料之主 ;、、、:而利用鎳作為金屬⑪化物之材料於製程巾仍存在著待 之問題:請參考第5圖與第6圖。第5圖與第6圖分別為利用習 知技術製作之具有鎳石夕化物之半導體元件的示意圖。如第$圖與 第6圖所不’習知半導體元件包含有一半導體基底％、隔離區幻、 一間極介電層34設於半導體基底3〇上、-多晶極36設於閘 極介電層34之上、—侧壁子結構％設於多晶極％之侧壁， 、及，源極/及極區域4〇設於乡晶石夕閘極％與隔離區％之間。另 外’半導體元件之鎳石夕化物42，則形成於源極/沒極區域4〇表面。 然而’利用上述習知方法所製作之鎳石夕化物42，特別是對於p型 半導體疋件而言’易向下成長而產生如第5圖所示的挪呢缺 陷，進而導致_/錄輯4G與轉縣底3()之魅嚴重的漏 電流問題。而除了 spiking缺陷外，利用習知方法所製作之錄石夕化 物42，特別是對於N型半導體元件而言，則易於往水平方向擴散 而產生piping缺陷’如第6圖所示。一旦發生帥㈣缺陷，則會 導致啟始電壓下降，而影響轉體元件的操作。 有鑑於此，為了避免上述問題，本發明提供一種具有錄石夕化物 之半導體70件婦作射錄之方法，其t轉體元件之源極級 1276145 極區域之表面具有由魏鎳與二魏齡成之鎳雜物，且錄石夕 化物係利用— 欠快速熱製程加以製作，藉以避免產生spik邮缺陷 與piping缺陷。 【發明内容】 本發明之目的之-在於提出—種具有射錄之半導體元件 與製作鎳魏物之，簡決習知技術無法克服之難題。 為獲致上述目的，本發日出—種製作鎳魏物之方法，上述 方法之主要包含有下列步驟：魏提供—半導體基底，且上述半 導體基底包含錢數娜舰域；接騎上辭導縣底上形成 一鎳層’再進行-第-快速練程，使上_層與錄其下方之 上述摻雜區域反應；隨後絲未反應之上層，並進行一第二 快速熱製程’其巾上述第二快速絲觀含有—峰值退火製程， 且其製程溫度介於400至600°C。 為獲致上述目的，本拥另提出—種具有翁化物之半導體元 t上述半導體元件主要包含有：_轉縣底；複數個換雜區 域設於上料導縣射；毅個·結構設赴料導體基底 上；以及複數個射錄’分顺於上述雜區辆，各錄^化 物包含有-由石夕化鎳組成之石夕化_域位於各捧雜區域之表面 2一由：魏齡成之：魏_袋_位於抑 各摻雜區域之界面。 ^興 1276145 為獲致上述目的，本發明另提出—種具有鎳石夕化物之半導體元 t上述半導體元件主要包含有：—轉縣底；複數個摻雜區 域設於上述料縣底巾；複數侧極結構設於上料導體基底 上:以及複數個鎳石夕錄，分別設於上述摻雜區域内，各錄石夕化 物係由魏鎳與二魏鎳組成，且二魏鎳之重量百分比係介於 1%至 10%。 ☆為了使貴審查委員能更近一步了解本發明之特徵及技術内 容’請參閲以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考熊職_，並_鱗本㈣純限制者。1276145 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device having nickel germanide and a method for fabricating nickel germanide, the surface of which is a source of a source/drain region of a semiconductor device The nickel and the shixihua nickel domain are chemically produced, and the above-mentioned nickel-wei materials are produced by a secondary rapid thermal process. [Prior Art] Due to its high impurity and low electrical resistance, metal ceramsite has been widely used in the fabrication of integrated circuits. The side is the line width, contact area and junction depth of today's integrated circuits. In the case of small parents, the closed-pole, source and drain of the component are required to be _metal Weisaki side-pole resistance, _act resistance and reduce the resistance-capacitor delay effect (Rcde (4), etc. The driving current of the semiconductor element. The metal lithium is produced on the semiconductor substrate by a metal film, which is then formed by heat treatment. In general, the gold (four) physics physical vapor deposition method, such as grade or sputtering. Deposited on the bottom of the county and covered with the location where the metal lithology is to be formed, such as the gate, the source and the immersion, and then the metal film is heated to make it covered with the engraving and the miscellaneous recording reaction. Metal Fragmentation. Metallic Stone Age is characterized by the ability to reduce the side resistance, contact resistance and resistance of the 1276145 valley delay effect, and the gold shot in the process is another In its ', there is a self-aligned function. For the current technology, self-align^^ silicide, salicide 6^^i^ffi 〇明爹考1 1 to 4. 1 to 4 are schematic views showing a conventional method for producing a metal ceramsite. As shown in Fig. 1, first, a semiconductor substrate 10 is provided, which contains a finished secret 12, such as a Weihua layer. Separately, a pole dielectric layer 14, a polycrystalline silicon gate 16 is disposed on the gate dielectric | 14 , and a sidewall substructure 18 is disposed on the sidewall of the polycrystalline silicon gate 16 and the source The /pole region % is disposed between the polycrystalline silicon gate 16 and the isolation region 12. As shown in Fig. 2, a metal thin film 22 is deposited on the semiconductor substrate 1 by physical vapor deposition to cover more The crystal (four) pole 16 and the source/no-polar region 2〇. Subsequently, as shown in FIG. 3, a tempering process is performed to react the metal thin film 22 with the polycrystalline silicon gate 16 and the source-level region 2G. And forming a metal halide 24 on the surface of the polycrystalline (four) pole % and the source/nopole region 20. Finally, as shown in FIG. 4, the unreacted metal film 22 is removed, that is, the metal is completed. In general, the metal film used to make the metal telluride mainly contains titanium, cobalt and nickel, among which the two-titanium has a lower resistance value (about 12 to 20#). Ω-cm), but it is easy to produce a um) wlinewidth effect. 'When the line width of the integrated circuit drops below i8〇nm, the sheet resistance will increase. On the other hand, the resistance values of Ershi Xihuaming and Strontium Nickel are slightly higher than those of titanium dioxide (the resistance values of the two are about 15 to 1,276,145' but there is no obvious fine line amplitude effect, so it is widely It is used as the material of the cerium metal cerium compound, in which the thickness of the cerium consumed by the nickel is less than that at the beginning of the formation of the same sheet resistance, which is the main material of the current metal lithium material; The use of nickel as the material of the metal 11 compound still has problems in the process towel: please refer to Fig. 5 and Fig. 6. Fig. 5 and Fig. 6 respectively show a semiconductor having a nickel-lithium cerium compound by a conventional technique. A schematic diagram of a device. As shown in FIGS. $ and 6, a conventional semiconductor device includes a semiconductor substrate %, an isolation region, and a dielectric layer 34 is disposed on the semiconductor substrate 3, and the polypole 36 is provided. Above the gate dielectric layer 34, the sidewall structure % is disposed on the sidewall of the polycrystal gate, and the source/pole region 4 is disposed at the gate and the isolation region. Between the other 'semiconductor elements of nickel lithium 42, formed in the source / The surface of the immersed area is 4 。. However, the nickel cerium compound 42 produced by the above-mentioned conventional method, especially for the p-type semiconductor element, is easy to grow downward to produce a shift as shown in Fig. 5. Defects, which in turn lead to the problem of serious leakage current of _/ recording 4G and Zhuan County 3 (). In addition to spiking defects, the recorded lithography 42 made by the conventional method, especially for N-type semiconductor components In other words, it is easy to spread in the horizontal direction to generate a piping defect as shown in Fig. 6. Once a handsome (four) defect occurs, it will cause a drop in the starting voltage and affect the operation of the rotating element. In view of this, in order to avoid the above The present invention provides a method for recording 70 semiconductors of a semiconductor having a lithographic compound, wherein the surface of the source region of the t-turn element is 1276145, and the surface of the polar region is made of nickel and nickel. Moreover, the Lishi compound is produced by using a sub-rapid thermal process to avoid the occurrence of spik post defects andpiping defects. SUMMARY OF THE INVENTION The object of the present invention is to provide a semiconductor component with recording and fabrication. Nickel Weeds, a simple and difficult problem that can not be overcome by conventional techniques. In order to achieve the above objectives, the present invention is a method for producing nickel weeds, and the above method mainly comprises the following steps: Wei provides a semiconductor substrate, and the above The semiconductor substrate contains the Qianna Na ship field; a nickel layer is formed on the bottom of the revelation county to perform a 're-running-first-fast process, so that the upper layer reacts with the above-mentioned doped region below the recording; The upper layer, and performing a second rapid thermal process 'the second fast wire view containing the peak annealing process, and the process temperature thereof is between 400 and 600 ° C. In order to achieve the above purpose, the present invention proposes The semiconductor element of Weng's semiconductor element mainly includes: _ turn county bottom; a plurality of replacement areas are set in the upper material guide county; Yi·· structure is set on the substrate of the conductor; and a plurality of records are distributed In the above-mentioned miscellaneous area, each recorded compound contains - the Shi Xihua _ domain consisting of Shi Xihua nickel is located on the surface of each holding area 2: Wei Xiancheng: Wei _ bag _ is located in each doping The interface of the area. ^兴1276145 In order to achieve the above object, the present invention further proposes a semiconductor element having a nickel-lithium cerium compound. The semiconductor element mainly comprises: - a turntable bottom; a plurality of doped regions are disposed in the material county back towel; The pole structure is disposed on the substrate of the feeding conductor: and a plurality of nickelstones are respectively disposed in the doped region, and each of the recorded Lithium compounds is composed of Wei nickel and Weiwei nickel, and the weight percentage of the Weiwei nickel is Between 1% and 10%. ☆ In order to enable the reviewing committee to further understand the features and technical contents of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings. However, the drawings are only for reference to bear _, and _ scale (four) pure limit.
L貫施万式J ^參考第7圖。第7 _本剌—触實麵製作餅化物之 下列=。如第7圖所示，本發明製作輪物之方法包含有 步驟5〇 =供一半導體基底，且半導體基底包含有複數個捧雜區 步驟52 :於半導體基底上形成—鎳層； 步驟54 第Γ快速熱製程’使錄層與位於其下方之換雜區 或反應，並生成矽化鎳； 步驟56 :去除未反應之鎳層；以及 步驟58 :=第高她，崎彻 其中弟二快速熱製程包含有—峰值退火製程，且其製i 1276145 溫度介於400至600°C。 '本發明製作餅化物之方法的主要特徵在於彻—二階段快 速熱製程’亦即在於半導體基底上形成鎳層後先進行第一快速熱 製程，以於源極/絲區域形成魏錦，隨後再去除未反應之錄層 亚進仃第二快速鋪程’使部分則b轉換成二魏鎳。盆中石夕 化鎳之電阻錄低(約介於15至20/ζ Ω__但較不穩定^二石夕 化鎳之電阻錄高(約介於40至50㈣_cm)但較穩定而本發明 j方法將部紗fb雜換為二魏鎳的目的在於湘其穩定性較 高的特性，發難__簡免魏鎳向下錢侧向過度生長 而產生前述spiking缺陷與piping缺陷。另外餅說_是於本發 明之較佳實施射’二魏鎳所佔之重量百分比僅佔1%至1〇%， 因此並不料財錄之電_祕影響，卻可有效避切㈣ 缺陷與piping缺陷。 請繼續參考第8圖至第11圖。第8圖至第η圖為本發明一較 佳實施例製作餅化物之方法示意圖，其中圖中僅㈣—半導體 讀作為制。如第8圖所示，首先提供—半導體基底6〇，其中 半導體基底60可為矽基底或矽覆絕緣(s〇I)基底等，且其上包含有 已製作完成之隔離區62，例如場氧化層或淺溝隔離，一閘極介電 層64 ’如一閘極氧化層、一閘極66設於閘極介電層私之上、一 侧壁子結構68設於閘極66之側壁，以及源極/没極區域7〇設於閘 極66與隔離區62之間。其中於本實施例中，半導體元件係泛指 1276145 各種電晶體元件、記憶體元件與邏輯元件等。 接著如第9圖所示，利用物理氣相沉積方式，例如蒸鍍或贿 方式，於半導體基底60上沉積一鎳層72，以覆蓋間極％與源極/ 汲極區域70，其中鎳層72可為-鎳金屬層或一鎳合金層。另外， 於沉積鎳層72後，本發明之方法亦可選擇性地於鎳層72上再形 成-阻障層73，例如-鈦層或一氧化鈦層，以避免鎳層72的氧 化。如第10圖所示，隨後進行一第一快速熱製程，以使鎳層72 與源極/汲極區域70以及閘極66反應，並於源極/汲極區域％之 表面形成石夕化鎳區域74，而於閘極66之表面形成石夕化鎳％。此 外，由於鎳層72僅與閘極66以及源極/没極區域7〇接觸，而於隔 離區62與側壁子結構68並不會生成金屬石夕化物，因此具有自行 對準功能。另外值得說明的是於本實施例中第一快速熱製程可為 一持溫退火(soak anneal)製程或一峰值退火製程，其製程溫度介於 250至350°C，並以300°C為較佳。 如第11圖所示，去除阻障層73以及未反應之鎳層72，並進行 —第二快速熱製程，藉此將矽化鎳區域74底部之矽化鎳轉換為二 =化鎳，以於石夕化鎳區域74底部形成二石夕化鎳口袋區域兀。'值: 說明的是於本實施例中，第二快速熱製程係為一夸值退火製程，于 其製程溫度係介於400至60(TC，並以介於480至520。(；為=， 而峰值退火製程之製程時間則係介於5至20秒，並以介於8至12 移為較佳。另外，上述實施例中之峰值退火製程之製程時間係以 12 1276145 T-50定義，所謂Τ-50係指製程溫度到達最高溫(假設為 的丁魏與之後的T-坑的所經歷之時間。此外由於在第一快速 熱製程中，除了產切化鎳之外，亦有可能生成另—種高電阻值 之鎳石夕化物：魏二鎳，耻本㈣之第二快速熱縣亦具有將 矽化二鎳轉換為矽化鎳之功用。 藉由上述綠，即可製糾本翻之具有翁絲之半導體元 件，其中鎳魏物係由魏舰域與環繞魏舰域之二石夕化錄 口袋區域所組成，且二魏鎳之重量百分比係控制於1%至祕之 間’藉此不致影響鎳石夕化物之電阻值又可有效避免印㈣缺陷與 Piping 缺陷。 請參考第12圖至第15圖。第U圖至第15圖為本發明另一較 佳實施例製作鎳魏物之方法示意圖，其中圖中僅纷出一半導體 讀作為說明。如第12圖所示，首先提供一半導體基底⑽，其上 包含有已製作完成之隔離區82，一閘極介電層84、一閉極％設 於閘極介電層84之上、一侧壁子結構88設於閘極％之侧壁，以 及源極/汲極區域9〇設於閘極86與隔離區82之間。其中於本實施 例:’半導體元件係泛指各種電晶體元件、記憶體元件與邏輯元 件等。 接者如第13圖所示，利用物理氣相沉積方式於半導體基底80 積鎳層92 ’以覆蓋間極86與源極/没極區域90，接著再選 13 1276145 擇性地於鎳層92上沉積-轉層93 _免騎％的氧化。如第 Η圖所示，隨後進行-第-快速熱餘，以使鎳層％與源極/汲 極區域90以及間極86反應，並於源極/沒極區域％之表面形成石夕 化鎳區域94 ’而於閘極86之表面形成矽化鎳％。 如第15圖所示，去除阻障層93與未反應之錄層％，並進行一 第二快速熱製程，以财化舰域94中部分魏鎳轉換為二石夕化 鎳’而形成-由石夕化鎳與二石夕化錄組成之錄石夕化物區域％。盆中 第二快速熱製程係為-♦值退火製程，且二槪鎳之重量百分比 亦係控制於Ρ/。至跳之間。她於前—實施例，本實施例不同之 處在於藉由機第-快速熱製域第二快速_程之參數，本實 ，之翁化物所包含之魏鎳與二魏鎳係為均勻分佈，‘ 如前一實施例之錄石夕化物所包含之石夕化鎳與二石夕化鎳具有明顯之 本—發明之方法储部分魏_換為二魏鎳，並彻二石夕化 鎳穩定性較高的特性，發揮阻障的功用以避免魏錄向下方或側 向過度生長而產生spiking缺陷與piping缺陷，因此相較於習知技 術，可有效提升轉體元件之電性表現與可靠度。L 贯施万式J ^ Refer to Figure 7. The 7th _ Ben 剌 - the solid surface of the cake to make the following =. As shown in FIG. 7, the method for fabricating a wheel of the present invention comprises the steps of: 供=for a semiconductor substrate, and the semiconductor substrate comprises a plurality of holding regions. Step 52: forming a nickel layer on the semiconductor substrate; Step 54 ΓRapid heat process 'Let the recording layer react with the miscellaneous area located below it and react to form nickel halide; Step 56: Remove the unreacted nickel layer; and Step 58: = High, she is the hottest The process includes a peak-to-peak annealing process and the temperature of the i 1276145 is between 400 and 600 °C. The main feature of the method for producing a cake according to the present invention is a thorough-two-stage rapid thermal process, that is, a first rapid thermal process is performed after forming a nickel layer on a semiconductor substrate to form Wei Jin in the source/filament region, and then Then remove the unreacted recording layer sub-injection second rapid spread 'to convert part b to diWei nickel. The resistance of the nickel in the basin is low (about 15 to 20 / ζ Ω__ but less stable ^ the resistance of the two nickel (the temperature is about 40 to 50 (four) _cm) but more stable and the method of the present invention j The purpose of replacing the partial yarn fb with diWei nickel is to have the characteristics of high stability of the fluorene, and it is difficult to make the above-mentioned spiking defect and the piping defect. In the preferred embodiment of the present invention, the weight percentage of the 'Wei-nickel' is only 1% to 1%, so it is not expected to be affected by the electricity, but it can effectively avoid (4) defects andpiping defects. 8 to 11 are a schematic view of a method for preparing a cake according to a preferred embodiment of the present invention, wherein only (4)-semiconductor read is used as the system. As shown in Fig. 8, firstly, A semiconductor substrate 6 is provided, wherein the semiconductor substrate 60 can be a germanium substrate or a germanium-insulating insulating (s?I) substrate, etc., and includes a completed isolation region 62, such as a field oxide layer or shallow trench isolation, The gate dielectric layer 64' is a gate oxide layer and a gate 66 is disposed on the gate dielectric layer. A sidewall substructure 68 is disposed on the sidewall of the gate 66, and a source/nomogram region 7 is disposed between the gate 66 and the isolation region 62. In the present embodiment, the semiconductor component is generally referred to as 1276145. A crystal element, a memory element, a logic element, etc. Next, as shown in Fig. 9, a nickel layer 72 is deposited on the semiconductor substrate 60 by physical vapor deposition, such as evaporation or bribery, to cover the inter-electrode % and The source/drain region 70, wherein the nickel layer 72 can be a nickel metal layer or a nickel alloy layer. Additionally, after depositing the nickel layer 72, the method of the present invention can also be selectively formed on the nickel layer 72 - A barrier layer 73, such as a titanium layer or a titanium oxide layer, to avoid oxidation of the nickel layer 72. As shown in FIG. 10, a first rapid thermal process is then performed to cause the nickel layer 72 to be source/drain The region 70 and the gate 66 react and form a shihua nickel region 74 on the surface of the source/drain region %, and form a shixi nickel on the surface of the gate 66. Further, since the nickel layer 72 is only connected to the gate The pole 66 and the source/no-polar region 7 are in contact, and the isolation region 62 and the sidewall substructure 68 are not generated. The metal lithium compound has a self-alignment function. It is also worth noting that in the embodiment, the first rapid thermal process can be a soak anneal process or a peak annealing process, and the process temperature is between 250. Up to 350 ° C and preferably 300 ° C. As shown in Fig. 11, the barrier layer 73 and the unreacted nickel layer 72 are removed, and a second rapid thermal process is performed, whereby the nickel halide region 74 is removed. The bottom nickel-deposited nickel is converted into two-nickel nickel to form a two-stone nickel pocket region at the bottom of the Shihua nickel region 74. 'Value: It is illustrated that in the present embodiment, the second rapid thermal process is one The quasi-annealing process has a process temperature range of 400 to 60 (TC) and between 480 and 520. (; = =, and the process time of the peak annealing process is between 5 and 20 seconds, and is preferably between 8 and 12. In addition, the processing time of the peak annealing process in the above embodiment is 12 1276145 T-50 defines that the so-called Τ-50 means that the process temperature reaches the highest temperature (assuming the time elapsed for the D-well and the subsequent T-pit. In addition, because in the first rapid thermal process, in addition to the production of nickel In addition, it is also possible to generate another high-resistance nickel-nickel compound: Wei Er-Ni, the second fast-heat county of Shame (4) also has the function of converting the niobium-nickel-nickel into niobium-nickel. The correction of the book has the semiconductor components of Wengsi, in which the nickel-wei system is composed of the Wei Shipyard and the area surrounding the Wei Shipyard, and the weight percentage of the two-wet nickel is controlled at 1% to the secret. Between the two, it is possible to effectively avoid the defects of the nickel (4) defects and the Piping defects. Please refer to Figures 12 to 15. Figures U to 15 show another preferred embodiment of the present invention. A schematic diagram of a method for producing nickel weeds, in which only half of the figures are shown. The conductor is read as an illustration. As shown in Fig. 12, a semiconductor substrate (10) is first provided, which includes a completed isolation region 82, a gate dielectric layer 84, and a gate electrode % disposed on the gate dielectric layer. Above the 84, a sidewall substructure 88 is disposed on the sidewall of the gate %, and the source/drain region 9 is disposed between the gate 86 and the isolation region 82. In this embodiment: 'Semiconductor component system Refers to a variety of transistor components, memory components and logic components, etc. As shown in Figure 13, the physical layer is used to deposit a nickel layer 92' on the semiconductor substrate 80 to cover the interpole 86 and the source/no pole. Zone 90, followed by 13 1276145, selectively deposits on the nickel layer 92 - the oxidation of the layer 93 _ ride-free %. As shown in the figure, the -first-rapid heat balance is subsequently performed to make the nickel layer % and source The pole/drain region 90 and the interpole 86 react to form a nickel-plated nickel region 94' on the surface of the source/no-polar region % and form a nickel-deposited nickel on the surface of the gate 86. As shown in Fig. 15, Removing the barrier layer 93 and the unreacted recording layer %, and performing a second rapid thermal process to finance the portion of the ship 94 The formation of Wei-nickel into two-stone nickel-formed nickel--the composition of Shishihua nickel and the two-stone Xihua recorded the magnetite area. The second rapid thermal process in the basin is the -♦ value annealing process, and two The weight percentage of bismuth nickel is also controlled between Ρ/. to hop. In the previous embodiment, the difference in this embodiment lies in the parameters of the second fast _ process of the machine-fast thermal domain. The Wei-Ni and Wei-Wei-nickel contained in the Weng compound are uniformly distributed, and the method of the invention is as obvious as the Shi Xihua nickel and the Ershi Xihua nickel contained in the Shi Xixiang of the previous embodiment. The storage part Wei _ is replaced by diWei nickel, and the stability of the nickel is higher, and the function of the barrier is used to prevent the shovel defect and the piping defect from being caused by the downward or lateral overgrowth of Wei Lu. Compared with the prior art, the electrical performance and reliability of the rotating component can be effectively improved.
以上所述僅為本發明之較佳實酬，凡依本伽 所做之均等·與修飾，皆觸本㈣之涵蓋範圍/ 14 1276145 【圖式簡單說明】 第1圖至第4圖為習知製作金屬矽化物之方法示意圖。 第5圖與第6圖分別為利用習知技術製作之具有鎳矽化物之半導 體元件的示意圖。 第7圖為本發明一較佳實施例製作鎳矽化物之方法流程圖。 第8圖至弟11圖為本發明一較佳實施例製作鎳石夕化物之方法示意 圖。 第12圖至第15圖為本發明另一較佳實施例製作鎳石夕化物之方法 示意圖。The above description is only the preferred remuneration of the present invention, and all the equivalents and modifications made by Benga are in the scope of this (4) / 14 1276145 [Simple description of the drawing] Figures 1 to 4 are the habits A schematic diagram of a method for producing a metal halide is known. Fig. 5 and Fig. 6 are schematic views respectively showing a semiconductor element having a nickel telluride produced by a conventional technique. Figure 7 is a flow chart showing a method of fabricating nickel telluride according to a preferred embodiment of the present invention. Fig. 8 to Fig. 11 are schematic views showing a method of producing a nickel-base compound according to a preferred embodiment of the present invention. 12 to 15 are schematic views showing a method of producing nickel cerium compound according to another preferred embodiment of the present invention.
【主要元件符號說明】 10 半導體基底 12 隔離區 14 閘極介電層 16 多晶矽閘極 18 侧壁子結構 20 源極/汲極區域 22 金屬薄膜 24 金屬石夕化物 30 半導體基底 32 隔離區 34 閘極介電層 36 多晶砍閘極 38 侧壁子結構 40 源極/汲極區域 42 鎳矽化物 50 流程步驟 52 流程步驟 54 流程步驟 56 流程步驟 58 流程步驟 60 半導體基底 62 隔離區 64 閘極介電層 66 閘極 15 1276145 68 侧壁子結構 70 源極/没極區域 72 鎳層 73 阻障層 74 矽化鎳區域 76 石夕化鎳 78 二矽化鎳口袋區域 80 半導體基底 82 隔離區 84 閘極介電層 86 閘極 88 侧壁子結構 90 源極/没極區域 92 鎳層 93 阻障層 94 矽化鎳區域 96 石夕化鎳 98 鎳矽化物區域 16[Main component symbol description] 10 Semiconductor substrate 12 Isolation region 14 Gate dielectric layer 16 Polysilicon gate 18 Sidewall substructure 20 Source/drain region 22 Metal film 24 Metal lithium 30 Semiconductor substrate 32 Isolation region 34 Gate Pole Dielectric Layer 36 Polycrystalline Gate 38 Sidewall Substructure 40 Source/Torminal Region 42 Nickel Telluride 50 Process Step 52 Process Step 54 Process Step 56 Process Step 58 Process Step 60 Semiconductor Substrate 62 Isolated Region 64 Gate Dielectric layer 66 Gate 15 1276145 68 Sidewall substructure 70 Source/nothing region 72 Nickel layer 73 Barrier layer 74 Deuterated nickel region 76 Shihwa nickel 78 Diminated nickel pocket region 80 Semiconductor substrate 82 Isolation region 84 Gate Pole dielectric layer 86 Gate 88 Sidewall substructure 90 Source/nominal region 92 Nickel layer 93 Barrier layer 94 Deuterated nickel region 96 Shihua nickel 98 Nickel telluride region 16