1275931 九、發明說明： 【發明所屬之技術領域】 本發明係指一 方法 種用於-系統晶片之内建即時測試方法 種可實現喊且即雜之自_試，舰含_路徑之測試的曰 【先前技術】 隨著積體電路技術的日新月異膽展，使得單塊^的集成 度越來越高，將複雜系統集成於一個獨立的系統晶片 (syst_-Chip ’ S〇c)成為可行的方案。系統晶片較以前的電 路板系統在重量、體積、性能和價格等方面都具有優勢，然而由 於測武生麟_與電賴模成三次方正設計者若 在:又相忽略測试問題’待產品大量生產時甚至會出現測試代價 超過製造代價的情形。因此，峨問題是⑽發展的—大挑戰。 s 主要是通過控制和觀察電路巾的信號，以確定電路 疋否正#工作。為提高晶片的可控性和可觀測性，掃描（Sc⑽） 疋現7最為常用的可測試設計Design F〇r Testabi卿，DFT )技術 之一’其做法是將晶片之記憶元件，如FliP_fl〇p、Lateh等串接為 知域（SeanChain)，如此記憶元件之内容都可以經由掃描鏈的 移動（Shifting)存取。在職時，測觸樣可經由掃描鏈移入 5 1275931 (Shift-in) ’測試結果可經由掃描鏈移出（Sh出_〇ut)。測試圖樣是 指一組邏輯輸入值，若理想的電路輸出和帶有錯誤的電路輸出不 .同，該錯誤就會被該測試向量_到。傳統上，晶片測試採用單 ^ 一固定錯誤模型（Si_ Stuck-at Fault Model，SSF )，該模型假設 電路某節點（N°de)在有缺陷時，該節點可以被模擬（M()del)成 固定邏輯-錯誤（Stuck-at One Fault)或固定邏輯零錯誤（灿也如 • ZeroFault)，亦即單元中的訊號狀態被鎖定在邏輯〇 (sa〇)或者 邏輯1 (SA1)上。此外，對於深次微米製造製程的晶片，其高性 能的測試帽必縣合錄實速或即雜（At_speed)故障模型， 包括躍遷故障（TransitionFault)模型、路徑延遲故障（p她D咖 Fault)模型等。 躍遷故IV模型包括慢上升（Si〇w_t〇_Rise)和慢下降 • (Slow_t〇-Fall)兩種類型。以慢上升故障模型為例，請參考第！ 圖。在第1目巾，_窗口是電路正f卫作所鱗的最大躍遷延 遲時間，測試時如果在觀測窗口時間段内捕捉（c叩㈣不到期 望的輸出，則認為被測試節點存在躍遷故障。 路控延遲故障模型與躍遷故障模麵似，不同的是利用路和 延遲故障模型測試電路的某—路徑的集中延遲情況。請參考第f 圖，第2圖為習知路徑延遲故障模型測試之示意圖。路徑延遵故 1275931 障模型測朗縣是電路巾—斜料徑，透過對路徑的輸入端 峨或發送（Launch)事件進行觸發，然後在特定的觀測時間窗 ^ 口内，由路役輸出端擷取或捕捉（Capture)期望輸出。 - 習知技術可藉由掃描鏈產生躍遷故障模型，然而其錯誤覆蓋 率（FaultCo職ge)可能無法包含關鍵路徑（Criticalpath)的測 鲁 4。所謂錯誤覆蓋率係指被偵測到錯誤數佔電路所有可能之錯誤 總數的比率’而關鍵路徑則是指在晶片中超出所定義之時間延遲 的特定路徑。因此，習知技術勢必須耗費額外的系統資源。 【發明内容】 口此’本發明之主要目的即在於提供一種用於一系統晶片之 内建即時測試方法，以改善習知技術的缺點。 本發明揭露-種用於-系統晶片之内建即時測試方法，其包 3有以下步驟.取得該系統晶片之一靜態時序分析（s加流 Analysis)結果；根據該靜態時序分析結果，決定該系統晶片中欲 進行-即時性測試之複數個關鍵路徑（Criticalpath);分析該複數 個關鍵路彳f之每-_路徑的魅控繼（⑽⑽p〇⑷ 訊號及捕捉㈣點（Ca_e 〇)咖丨PGint)峨妓纽數個測試 狀態；以及賴複數侧試狀態輸人至—虛擬脑軟體結構 1275931 (Virtual Instrumentation Software Architecture )封裝（Wrapper ) 中。 本發明另揭露一種用於一系統晶片之内建即時測試方法，其 包含有以下步驟：決定該系統晶片中欲進行一即時性測試之複數 個關鍵路徑（CriticalPath);決定每一關鍵路徑的觀查控制點 (ObserveControlPoint)及捕捉控制點（CaptureContr〇lp〇int); 以及根據每一關鍵路徑的觀查控制點及捕捉控制點的訊號，分析 該系統晶片。 【實施方式】 請參考第3圖，第3圖為本發明内建即時測試流程3〇之示意 圖。流程30·係用於一系統晶片，其包含以下步驟： 步驟300 :開始； 步驟302 :取得該系統晶片之一靜態時序分析（Statistic Timing Analysis)結果； - 步驟304 :根據該靜態時序分析結果，決定該系統晶片中欲進 行一即時性測試之複數個關鍵路徑（Critical Path ); 步驟306 :分析該複數個關鍵路徑之每一關鍵路徑的觀查控制 點（ObserveControlPoint)訊號及捕捉控制點 (Capture ControlPoint)訊號以產生複數個測試狀 8 1275931 態； 步私308 ·將该複數個測試狀態輸入至一虛擬儀器軟體結構 (Virtual Instrumentation Software Architecture)封裝 (Wrapper)中； 步驟310 :結束。 簡言之’本發明係藉由包含物理電路節點和加權邊緣 (WeightedEdge)的時序圖，描述該系統晶片之電路以取得該系 統晶片之時序分析結果，再根據靜態時序分析結果決定該系 統晶片中欲進行-即時性測試之複數個關鍵路徑。接T來，先啟 動-準備階段提示該即時性測試的啟始，再啟動—發送階段 ( 明）以輸出測式訊號，最後啟動-捕捉階段（Capture s=.咖_她。如此—來，本發明可分析該複數個關鍵 路位之母關鍵路麵觀查控概⑽贿沿咖1驗G 及捕捉控伽（c_c。咖1PGint) f_產 ^ 複數個測試狀態透過該虛擬儀器軟體結構之—測： 從而進行㈣雖^賴1軟留_中， 舉例來說，請參考第 程30執行測試之示意圖， 4圖及第5圖。第4圖為依據本發明流 第5圖為對應於第4圖之訊號波形示意 1275931 圖。在第4圖中’控制器50係根據—時脈訊號 减SO、S卜S2以進订測試，並將測試結果傳送至虛擬儀器軟體 麵裝中。㈣咖，帛4目愉了—贿控制點仙、 -親察點42…捕捉控繼4切及—捕捉點*，其分別位於〇 塑正反器52、54、56、58的輸出端。假設時脈訊號CX每一週期 長度為了，若麵5G於说時輸嶋ιτ糊訊號％，則 此時進入準歸段’D型正Μ 52會被清除（ci_即輸出訊號 轉為邏輯◦)’而D型正反器54、56、58會被設定（^即輸出 訊號轉為邏輯1 型正Μ 52的輪出峨會與電路巾其 m號進行或（or)運算，因朴^剂X c ^ _ 日此1"败反11 54的D端輸入訊號為 迷輯〇 ’但由於D型正反器54處於設定狀態，所以d型正反哭 54的輸出仍為賴卜在職2 5τ，控㈣5_紐叮的於 制訊號S1 ’ @此私發鞠I賴，Μ與時脈訊號 OCjt行或聽，於3T時將D虹反^ 54錄，使得3丁時 親察點42的訊號轉為邏輯Q，亦即開始發送㈤祕）。接下來， 控制器50於3·5Τ時輸出長度1Τ的控制訊號S2，則此時進入捕捉 階段。控制訊號S2與時脈訊號CK進行或運算後，將結果輸入至 D型正反器58 ’因此D型正反器％於_被致能，則捕捉點恥 訊號於4T時由邏輯1轉為邏輯〇。然後，再比較D型正反号％ 的輪出訊號與—預期值。最後，將電路中所有比較結果輸出至控 制器50中。 1275931 t之’本發明係於不同時間清除或設定麟路徑上的D型 正反器，因此不會受到時序的影響。再者，本發明可於一系統晶 片實現内建且即時性之自我測試，並克服習知技術中無法包含關 鍵路徑測試的問題。 _ 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為躍遷故障模型中慢上升故障模型之示意圖。 第2圖為習知路徑延遲故障模型測試之示意圖。 第3圖為本發明内建即時測試流程之示意圖。 φ第4圖為第3圖之流程執行測試之示意圖。 第5圖為對應於第4圖之訊號波形示意圖。 【主要元件符號說明】 30流程 300、302、304、306、308、310 步驟 40觀察控制點 42觀察點 11 1275931 44捕捉控制點 46捕捉點 52、54、56、58 D型正反器 50控制器 SO、SI、S2 控制訊號 CK時脈訊號 121275931 IX. Description of the invention: [Technical field to which the invention pertains] The present invention refers to a method for the built-in instant test method for a system chip, which can realize the shouting and the self-test, the test of the ship-containing path曰[Prior Art] With the rapid development of integrated circuit technology, the integration of single blocks is getting higher and higher, and it is feasible to integrate complex systems into a single system chip (syst_-Chip 'S〇c). Program. The system chip has advantages in terms of weight, volume, performance and price compared with the previous circuit board system. However, since the measurement of Wu Shenglin and the electric aging model are three squares, the designer is: Ignore the test problem. There may even be cases where the test cost exceeds the manufacturing cost. Therefore, the problem is (10) the development of the big challenge. s mainly by controlling and observing the signal of the circuit towel to determine whether the circuit is working or not. In order to improve the controllability and observability of the wafer, Scan (Sc(10)) is one of the most commonly used testable design Design F〇r Testabi, DFT technology, which is the memory component of the chip, such as FliP_fl〇 p, Lateh, etc. are connected in series (SeanChain), so that the contents of the memory element can be accessed via Shifting of the scan chain. At the time of service, the touch test can be moved through the scan chain 5 1275931 (Shift-in) ' Test results can be removed via the scan chain (Sh out _ 〇 ut). The test pattern refers to a set of logic input values. If the ideal circuit output and the circuit output with the error are not the same, the error will be _ to the test vector. Traditionally, wafer testing has adopted a Si_Stuck-at Fault Model (SSF), which assumes that a node (N°de) of a circuit can be simulated (M()del) when it is defective. A fixed logic-stack (Stuck-at One Fault) or a fixed logic zero error (can also be like ZeroFault), that is, the signal state in the unit is locked to logic 〇 (sa〇) or logic 1 (SA1). In addition, for deep sub-micron manufacturing processes, its high-performance test caps must record real-time or at-speed fault models, including transition fault models (TransitionFault) models and path delay faults (p-D-Dafe Fault). Models, etc. The transition IV model includes two types: slow rise (Si〇w_t〇_Rise) and slow fall • (Slow_t〇-Fall). Take the slow rise fault model as an example, please refer to the first! Figure. In the first earpiece, the _window is the maximum transition delay time of the scale of the circuit, and if it is captured during the observation window period (c叩(4) is less than the expected output, then the transition of the tested node is considered to be faulty. The road delay fault model is similar to the transition fault model. The difference is the use of the road and delay fault model to test the concentrated delay of a certain path of the circuit. Please refer to the f-figure, and the second figure is the conventional path delay fault model test. Schematic diagram of the path delaying the 1759931 barrier model to measure the county is the circuit towel - the oblique path, triggered by the input of the path or the Launch event, and then in the specific observation time window, by the road The output captures or captures the desired output. - The conventional technique can generate a transition fault model by scanning the chain. However, the error coverage (FaultCo ge) may not contain the critical path (Criticalpath). Error coverage is the ratio of the number of errors detected to the total number of possible errors in the circuit' and the critical path is the time delay beyond the defined time in the wafer. A specific path that is late. Therefore, the prior art has to consume additional system resources. [Invention] The main purpose of the present invention is to provide a built-in instant test method for a system wafer to improve the conventional knowledge. Disclosed are the built-in instant test method for the system chip, and the package 3 has the following steps: obtaining a static timing analysis (s plus flow analysis) result of the system chip; according to the static timing analysis As a result, a plurality of critical paths of the system chip to be tested-immediately tested are determined; the magical control of each of the plurality of critical paths 分析f is analyzed ((10)(10)p〇(4) signal and capture (four) point (Ca_e) 〇) 丨 丨 丨 丨 丨 丨 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 丨 丨 丨 丨 丨 丨 丨 丨 丨The built-in instant test method of the chip includes the following steps: determining a plurality of off-the-shelf tests in the system chip Path (CriticalPath); determine the observing control point (ObserveControlPoint) and capture control point (CaptureContr〇lp〇int) of each critical path; and analyze the control point and the capture control point signal according to each critical path [System] [Embodiment] Please refer to Figure 3, which is a schematic diagram of the built-in instant test flow of the present invention. The process 30 is used for a system wafer, which includes the following steps: Step 300: Start; 302: obtaining a Statistic Timing Analysis result of the system chip; Step 304: determining, according to the static timing analysis result, a plurality of critical paths in the system chip for performing an immediacy test; Step 306: Analyze an Observe Control Point signal and a Capture Control Point signal of each of the plurality of critical paths to generate a plurality of test patterns 8 1275931 state; Step private 308 · The plurality of critical paths Test status input to a Virtual Instrumentation Software Architecture package (Wra Pper); Step 310: End. Briefly, the present invention describes a circuit of the system chip by using a timing diagram including a physical circuit node and a weighted edge to obtain a timing analysis result of the system chip, and then determines the system wafer according to the static timing analysis result. A number of critical paths to be tested - immediacy. Connect T, first start-prepare stage prompts the start of the immediacy test, restart - send phase (clear) to output the test signal, and finally start-capture phase (Capture s =. coffee _ her. So - come, The invention can analyze the key road surface inspection and control of the plurality of key road positions (10) bribes along the coffee 1 check G and capture control gamma (c_c. coffee 1 PGint) f_production ^ a plurality of test states through the virtual instrument software structure - Test: Thus proceed to (4) Although it depends on 1 soft leave _, for example, please refer to the schematic diagram of the execution of the test 30, 4 and 5. Figure 4 is the flow according to the present invention, Figure 5 corresponds to The signal waveform of Figure 4 shows the 1275931 diagram. In Figure 4, the controller 50 is based on the clock signal minus SO, S Bu S2 to subscribe to the test, and the test results are transmitted to the virtual instrument software surface device. Coffee, 帛 4 eyes are pleasant - bribe control points, - pro-point 42... capture control 4 cuts and - capture points *, which are located at the output of the plastic flip-flops 52, 54, 56, 58 respectively. The length of each cycle of the clock signal CX is, if the face 5G loses the signal value % when speaking, then this time The quasi-return section 'D-type positive 52 will be cleared (ci_ is the output signal to logic ◦)' and the D-type flip-flops 54, 56, 58 will be set (^ the output signal is converted to logic type 1 The round-out 52 52 will be ORed with the m-number of the circuit towel, because the PC X c ^ _ 1" defeated the D-end of the 11 54 input signal is the 〇 〇 'but due to the D-type positive The counter 54 is in the set state, so the output of the d-type positive and negative crying 54 is still Laibu's in-service 2 5τ, control (four) 5_纽叮's signal S1 ' @ this private hair 鞠 I 赖, Μ and clock signal OCjt line Or listen, when D3 is recorded at 3T, so that the signal of the 3rd time watch point 42 turns into logic Q, that is, it starts to send (5) secret. Next, the controller 50 outputs the length at 3·5Τ. The control signal S2 of 1Τ enters the capture phase at this time. After the control signal S2 is ORed with the clock signal CK, the result is input to the D-type flip-flop 58' so that the D-type flip-flop is enabled at _, Then capture the point shame signal from logic 1 to logic 4 at 4T. Then, compare the round-out signal of the D-type positive and negative number % with the expected value. Finally, all the comparison results in the circuit are lost. Out of the controller 50. 1275931 t 'The invention is to clear or set the D-type flip-flop on the lining path at different times, so it is not affected by the timing. Moreover, the present invention can be implemented in a system wafer Self-testing and self-testing, and overcoming the problem that the critical path test cannot be included in the prior art. _ The above is only a preferred embodiment of the present invention, and the equal variation and modification made by the scope of the patent application of the present invention All should be within the scope of the present invention. [Simple Description of the Drawing] Figure 1 is a schematic diagram of the slow rising fault model in the transition fault model. Figure 2 is a schematic diagram of a conventional path delay fault model test. Figure 3 is a schematic diagram of the built-in instant test process of the present invention. Figure 4 of φ is a schematic diagram of the process execution test of Figure 3. Figure 5 is a schematic diagram of the signal waveform corresponding to Figure 4. [Main component symbol description] 30 flow 300, 302, 304, 306, 308, 310 Step 40 observation control point 42 observation point 11 1275931 44 capture control point 46 capture point 52, 54, 56, 58 D-type flip-flop 50 control S, SI, S2 control signal CK clock signal 12