1273774 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種提高解析度之裝置鱼方卜 麵於提高編碼器解析度之裝置與方法/、方去，特別係指一 【先前技術】 按，-般來說，習知編碼器輸出訊號是兩個相位差9〇产 的弦波，其中一個是正弦波（sine wavef〇rm)，另一個是& 弦波（cosine waveform)，其編碼處理方式都是利用越 點來做切割轉成數位訊號。然，現今許多精密電子嗖^，在 ，行運算速度上及其結構設計上普遍具有朝向高速^及高精 密度化之趨勢，因此’習知該種編碼處理方式之技術益法 到精密電子設備之需求。 … 至於一般塢碼技術欲藉由ADC(類比數位轉換器）來提升 解析度會植多醜產生，尤其，因編碼糾錢振幅會隨 著馬達轉速的不同而有所不同，轉速越快所感應出來的訊號 振幅會越小，故在此以一般的ADC方式來增加解析度有其困 難度，誠難以可行。 八 • 習知關於高解析度編碼器之技術，已有公開在美國專利 公報中，由Santos等人所發明，專利名稱為:「ffighres〇luti〇n encoder」，專利號碼分別爲^987,41?及5,0^^ 然其皆係屬於固定機構之設計，並不具有彈性選擇倍頻之功 能，產業上之利用範圍有限。 有鑑於此，本發明人遂於93年2月26日以「高解析度磁感 淚1器編碼器之編碼方法」向鈞局提出發明專利申請，並已 獲准專利，公告在94年6月21日專利公報，證書號數：1234935， 在此併入本文，以供參考。 因此，關於提高編碼器解析度之技術，對於促進產業上 1273774 之發展，係有正面之助益。 【發明内容】 梦詈明目的係提供—種提高編碼11解析度之 ^置裝置包含-相位延遲電路、_第—倍頻比較電路、一 第一倍頻味電H彳或（NC)R)賴餘單元、以 ΐ位ίϊ=。該相位延遲電路用以供一第-弦波訊號與-1273774 IX. Description of the Invention: [Technical Field] The present invention relates to an apparatus and method for improving the resolution of an apparatus for improving the resolution of a device, and in particular, a prior art In general, the conventional encoder output signal is two sine waves with a phase difference of 9 ,, one of which is a sine wave (sine wavef〇rm) and the other is a & cosine waveform. The encoding processing method uses the more points to make the cutting into digital signals. However, many of today's precision electronic devices have a tendency toward high speed and high precision in terms of line operation speed and structural design. Therefore, it is known that the technology of the code processing method is advantageous to precision electronic equipment. Demand. As for the general docking code technology, the ADC (analog digital converter) is used to improve the resolution. It will be ugly, especially because the amplitude of the code correction will vary with the motor speed. The smaller the amplitude of the signal coming out, the more difficult it is to increase the resolution by the general ADC method. VIII. The technology of high-resolution encoders is disclosed in the US Patent Gazette, invented by Santos et al., and the patent name is “ffighres〇luti〇n encoder”. The patent numbers are ^987,41 respectively. And 5,0^^ are all designed to be fixed mechanisms, and do not have the function of elastic selection of frequency multiplication, and the industrial use range is limited. In view of this, the inventor filed an invention patent application with the "High-resolution Magnetic Tear-Tear Encoder Coding Method" on February 26, 1993, and has been granted a patent, announced in June 1994. The Patent Gazette on the 21st, the number of the certificate number: 1234935, is incorporated herein by reference. Therefore, the technology for improving the resolution of the encoder has a positive effect on promoting the development of the industry in 1273774. SUMMARY OF THE INVENTION The object of the present invention is to provide a phase-delay circuit, a _first-multiplier comparison circuit, a first frequency doubling power H彳 or (NC)R. Depend on the unit, in the position ϊ ϊ =. The phase delay circuit is used for a sine wave signal and -
^ ’彼此間具有-相位輯。該第—倍紙較電路，用以= ^ - ^訊號與該第二弦波訊號輸人，而輸出具有—第一^頻 ，之第-訊號與-第-倍頻數之第二訊號。該第二倍頻比較電 路资用以供該第-延遲訊號與第二延遲訊號輸人，❿輸出且有 二，-倍頻數之第三訊號與-第—倍頻數之第四訊號。該2 J (NOR)邏輯運算單元，用接收該第一倍頻數之第一訊號、 ，一,頻數之第三猶、第一倍頻數之第三訊號以及第一倍頻 數之第四訊號，而產生一第二倍頻數之第一號盥^ ' There is a phase sequence between each other. The first-fold paper comparison circuit is configured to input a ^^-^ signal and the second string signal, and output a second signal having a first frequency, a first signal, and a -first frequency. The second frequency doubling comparison circuit is used for inputting the first delay signal and the second delay signal, and outputting the second signal of the second and the octave numbers and the fourth signal of the -first octave number. The 2 J (NOR) logic operation unit receives the first signal of the first octave, the first signal of the third frequency, the third signal of the first octave number, and the fourth signal of the first octave number, and Generate a first doubling of the second octave
其中，第二倍雜之第-訊號與第二喊比該第之 第一讯號、第二訊號、第三訊號以及第四訊號之倍頻數更高。 該相位差解碼電路，肋接收該第二倍頻數之第—訊號斑第二 訊號，並計數該第二倍頻數之第一訊號與第二訊號的上升緣及 下降$，而產生一第三倍頻數之第一訊號與第二訊號，其中， 該第三倍頻數之第一訊號與第二訊號比該第二倍頻數之第一 訊號與第二訊號之倍頻數更高。 本發明之另一目的係提供一種提高編碼器解析度之方 法，該方法包含下列步驟：係將兩個相位差9〇度的第一弦波 訊號與第二弦波訊號，從0度至360度共同區分為16個區間寬 度皆為22.5度之區間；將上述兩個弦波訊號各自經由兩個反相 放大器串接，並搭載阻抗匹配，依據這兩個弦波訊號在22.5 度等份區間邊界角度有固定比值的條件判斷，以解析出複數 個可用之輸出訊號；將該些複數個輸出訊號作互斥或（N〇R) 1273774 邏，運算得到第一個更高兩倍頻訊號；將前述之訊號帶入一 運鼻式，產生第一與第二弦波延遲1125度之訊號，此訊號並 使用上述步驟方法得到第二個更高兩倍頻訊號，達到從〇度至 360度區分為32個區間寬度皆為丨丨·25度之效果；接著結合該編 碼器外之比較電路，利用訊號的上升緣及下降緣，以達到高 倍頻高解析度效果。 根據本發明之另一觀點，提高編碼器解析度之方法，該 方法亦可包含下列步驟：係將兩個相位差9〇度的第一弦波訊 號與第二弦波訊號，從〇度至360度共同區分為16個區間寬度 皆為22.5度之區間；採用微處理器中的類比數位轉換器 (ADC)對馬達所用編碼器輸出的弦波訊號做等份分割，並 依據上述這兩個弦波訊號在22·5度等份區間邊界角度有固定 比值的條件判斷，以解析出複數個可用之輸出訊號；將上述 之輸出訊號帶入一運算式與互斥或（N〇r)邏輯運算，達到 從〇度至360度區分為32個區間寬度皆為η·25度之效果；接著 結合該編碼器外之比較電路，利用訊號的上升緣及下降緣， 以達到高倍頻高解析度效果。 根據本發明之又一觀點，提南編碼器解析度之方法，該 方法亦可包含下列步骤··輸入一組弦波與一組方波；當一馬 達轉動時，該編碼器輸出第一、第二弦波訊號；將上述之訊 號輸入到一微處理器中的類比數位轉換器，當該微處理器之 程式啟動時，其類比數位轉換器會以一預定時間之取樣週期 時間間隔對上述第一、第二弦波訊號作類比數位轉變，且不 斷將最新轉換值代入一預定之數學模組進行運算，依區間分 割每個弦波訊號切出四個方波；上述之方波訊號，經互斥或 (NOR)邏輯運算時，以得到更高兩倍頻(八個方波)的第一個 訊说，將此訊说帶入一運鼻式’並使用一相位延遲電路，使 6 1273774 前述兩個弦波延遲1L25度之訊號；並達到從〇度至36〇度區分 為32個區間寬度皆為1125度之效果，使用上述步驟方法得到 另一組四個方波訊號，將之作互斥或（N〇R)邏輯運算可得 到更高兩倍頻(八個方波)的第二個訊號；接著結合該編碼器外 之比較電路，利用前述之第一個訊號與第二個訊號的上升緣 及下降緣，可達到高倍頻高解析度的效果。 【實施方式】 請參閱第一圖，係本發明實施例編碼器之原始訊號與經過 四倍頻訊號輸出的比較示意圖，包含有一第一弦波訊號（Y) 與一第二弦波訊號（X)，其分別表示為正弦波（sinewave) 與餘弦波（cosinewave)。該第一弦波訊號與第二弦波訊號之 相位差為90度。且，該第一弦波訊號與第二弦波訊號在36〇 度之週期内共同區分為第一複數個區間（如個區間）寬度 角度相同之第一角度（如22·5度）區間。 請參閱第二圖，其係將前述相位差90度的第一弦波訊號 與第二弦波訊號以360度做16等分的示意圖，其中，橫軸（即 X軸）表示係餘弦訊號（COS0 )，而縱軸（即γ軸）表示係正 弦訊號（siM)，以致，可劃分為16個區間寬度皆為22.5度之 區間。 請參閱第三圖，其係前述第二圖中所示之22.5度區間之區 間邊界，表示X轴之餘弦訊號（cos^ )與γ轴之正弦訊號（sin<9 ) 在22·5度時，sin<9/cos<9有一個0.414倍的關係。 請參閱第四圖，其係依據前述第一至第三圖所示資訊整 理之比較圖。包含有輸出、輸入比較、以及輸出區間三個欄 位，其中，在輸出欄位之訊號A，所對應之輸入比較攔位内之 第一式和第三式、第二式和第四式，以及在輸出攔位之訊號 B，所對應之輸入比較攔位内之第一式和第三式、第二式和第 四式，皆具有對稱相反關係。 1273774 請參閱第五圖，係本發明實施例四倍頻之訊號比值示意 圖。其中’第一個為反或閘（>=1後面有一個圈的方塊，即 NOR閘），其輸出等於在第四圖中訊號a所對應輸入比較欄位 内第一個式子[&>〇) & (x>y)]、第五圖第二個為及閘（AND 閘）’其輸出等於在第四圖中訊號A所對應輸入比較欄位内第 三個式子、第五圖第三個為反或閘（X0R閘）其輸出等於第 四圖中訊號A所對應輸入比較攔位内第四個式子、第五圖第四 個為及閘（AND閘）其輸出為第四圖中訊號a所對應輸入比 較攔位内第二個式子，最後這四個式子輸出（P1、P2、P3、 P4)的地方用一個或閘（>=1後面沒有圈的方塊，〇R閘）結 合起來就變成一條我們所想要的輸出訊號A ;輸出訊號B也以 此類推。因此，利用這個關係圖也就可以更進一步得到如第 一圖下半部所示的倍頻輸出圖。 上述硬體部分的設計方式係可利用運算放大器（〇pA) 作訊號倍率更改與訊號互相比較來達到各區間的切割，在倍 率更改部分運算放大器（OPA)是作為放大用，只需調整電 阻的比值就可以作不同倍率的轉換。 請參閱第六圖，係本發明實施例四倍頻之阻抗匹配示意 圖。由剞述第二圖所示之區間邊界圖，可知訊號包含有有X、 •X、0.414X、Y、-Y和〇·414Υ等六種訊號，本發明此一較佳 實施例只要把上述這兩個原始訊號（即正弦訊號與餘弦訊 號）’各自經由兩個反相放大器0ΡΑ1串接〇1>八2與〇1>八3串接 0ΡΑ4，並搭配適當的阻抗匹配，就可以製作出上述所需的訊 號（X、·Χ、0.414Χ、Υ、-Υ 和 0·414γ)。 再把這些訊號依照第三圖的關係下去互相作比較，结合 比較電路，包括有：比較器CP卜CP2、CP3、CP4、ΟΡ5、epY、 CP7、CP8 ’並再結合各自需求之邏輯㈣（請配合參閱第五 1273774 圖所示）U、L2、L3、L4、L5、L6、L7、L8就可以各自得 到不同脈波？卜？2、？3、？4、卩5、？6、？7、？8的輸出，之後， 再將PI、P2、P3、P4之訊號經由或閘（〇R閘）L9結合與P5、 p6 ' P7、P8之訊號經由或閘（〇R閘）L1〇結合就可以得到最 終邏輯輸出，也就是輸出訊號A及B(此訊號即具有四倍頻）。The second multiplicity of the first signal, the second signal, and the second signal are higher than the first signal, the second signal, the third signal, and the fourth signal. The phase difference decoding circuit receives the second signal of the second frequency multiplied by the rib, and counts the rising edge and the falling value of the first signal and the second signal of the second multiple frequency to generate a third time The first signal and the second signal of the frequency, wherein the first signal and the second signal of the third multiplier are higher than the first and second signals of the second multiplier. Another object of the present invention is to provide a method for improving the resolution of an encoder, the method comprising the steps of: first sine wave signals and second sine wave signals having two phase differences of 9 degrees from 0 degrees to 360 degrees The degrees are divided into 16 sections with a width of 22.5 degrees; the two sine signals are connected in series via two inverting amplifiers, and impedance matching is performed according to the two chord signals in the 22.5 degree interval. The boundary angle has a fixed ratio of conditional judgments to resolve a plurality of available output signals; the plurality of output signals are mutually exclusive or (N〇R) 1273774 logic, and the operation obtains the first higher double frequency signal; Bringing the aforementioned signal into the nose mode, generating a signal of 1125 degrees delay between the first and second chord waves, and using the above steps to obtain a second higher frequency signal, from 〇 to 360 degrees The effect is that the width of each of the 32 sections is 丨丨·25 degrees; then, the comparison circuit outside the encoder is used to use the rising edge and the falling edge of the signal to achieve high frequency multiplication effect. According to another aspect of the present invention, a method for improving the resolution of an encoder, the method may further comprise the steps of: first chord signal and second chord signal with two phase differences of 9 degrees from 360 degrees are commonly divided into 16 sections with a width of 22.5 degrees; the analog-to-digital converter (ADC) in the microprocessor divides the sine wave signal output by the encoder used by the motor into equal parts, and according to the above two The sine wave signal has a fixed ratio conditional judgment at the boundary angle of the 22·5 octave interval to parse a plurality of available output signals; the above output signal is brought into an arithmetic expression and mutual exclusion or (N〇r) logic The calculation achieves the effect that the width of each of the 32 sections is η·25 degrees from the twist to 360 degrees; then, using the comparison circuit outside the encoder, the rising edge and the falling edge of the signal are used to achieve high frequency and high resolution. effect. According to still another aspect of the present invention, a method for extracting a resolution of a grading encoder, the method may further include the following steps: inputting a set of sine waves and a set of square waves; when a motor rotates, the encoder outputs the first a second sine wave signal; an analog digital converter that inputs the above signal into a microprocessor, and when the program of the microprocessor is started, the analog digital converter performs the above sampling interval time interval The first and second chord signals are analogously digitized, and the latest converted value is continuously substituted into a predetermined mathematical module for calculation, and each square wave signal is divided into four square waves according to the interval; the square wave signal mentioned above, In the case of mutual exclusion or (NOR) logic, to get the first double of the higher frequency (eight square waves), bring this message into the nose and use a phase delay circuit. 6 1273774 The two chords are delayed by 1L25 degrees; and the effect is from 1 to 36 degrees, and the width of each of the 32 segments is 1125 degrees. Use the above steps to obtain another set of four square wave signals. Mutually exclusive or (N〇 R) logic operation can obtain a second signal with a higher frequency (eight square waves); then, in combination with the comparison circuit outside the encoder, the rising edge and the falling of the first signal and the second signal are used. The edge can achieve high multi-frequency and high resolution effects. [Embodiment] Please refer to the first figure, which is a comparison diagram of an original signal of an encoder and a quadruple frequency signal output according to an embodiment of the present invention, including a first sine wave signal (Y) and a second sine wave signal (X). ), which are represented as sinewave and cosinewave, respectively. The phase difference between the first chord signal and the second chord signal is 90 degrees. Moreover, the first sine wave signal and the second sine wave signal are jointly divided into a first plurality of intervals (such as a section) and a first angle (such as 22·5 degrees) having the same width and angle in a period of 36 degrees. Please refer to the second figure, which is a schematic diagram of dividing the first sine wave signal and the second sine wave signal with a phase difference of 90 degrees by 16 degrees in 360 degrees, wherein the horizontal axis (ie, the X axis) represents a cosine signal ( COS0), and the vertical axis (ie, the γ-axis) represents a sinusoidal signal (siM), so that it can be divided into 16 sections with a width of 22.5 degrees. Please refer to the third figure, which is the interval boundary of the 22.5 degree interval shown in the second figure, which indicates that the cosine signal (cos^) of the X-axis and the sine signal (sin<9) of the γ-axis are at 22·5 degrees. , sin<9/cos<9 has a relationship of 0.414 times. Please refer to the fourth figure, which is based on the comparison of the information processing shown in the first to third figures. There are three fields of output, input comparison, and output interval, wherein the signal A in the output field corresponds to the first type and the third type, the second type and the fourth type in the input comparison block. And in the signal B of the output block, the first type and the third type, the second type and the fourth type in the corresponding input comparison block have symmetric opposite relations. 1273774 Referring to FIG. 5, it is a schematic diagram of a signal ratio of four times the frequency of the embodiment of the present invention. Where 'the first one is the inverse or gate (>=1 followed by a circle of squares, ie NOR gate), the output is equal to the first expression in the input comparison field corresponding to the signal a in the fourth diagram [& ;>〇) &(x>y)], the second figure of the fifth figure is the AND gate (AND gate)' whose output is equal to the third formula in the input comparison field corresponding to the signal A in the fourth figure. The third figure in the fifth figure is the inverse or gate (X0R gate). Its output is equal to the fourth type in the input comparison block corresponding to the signal A in the fourth figure, and the fourth figure in the fourth figure is the AND gate (AND gate). The output is the second expression in the input comparison block corresponding to the signal a in the fourth figure, and the last four output outputs (P1, P2, P3, P4) use one or a gate (>=1 behind) The ring without the ring, 〇R gate) combines to become the output signal A we want; the output signal B is also deduced by analogy. Therefore, using this diagram, the multiplier output map as shown in the lower half of the first figure can be further obtained. The above-mentioned hardware part can be designed by using an operational amplifier (〇pA) for signal multiplication change and signal comparison to achieve cutting in each interval. In the magnification change part, the operational amplifier (OPA) is used for amplification, and only needs to adjust the resistance. The ratio can be converted to different magnifications. Please refer to the sixth figure, which is a schematic diagram of impedance matching of four times the frequency of the embodiment of the present invention. By referring to the interval boundary diagram shown in the second figure, it can be seen that the signal includes six kinds of signals, such as X, X, 0.414X, Y, -Y, and 〇·414, and the preferred embodiment of the present invention is as long as The two original signals (ie, the sinusoidal signal and the cosine signal) are respectively connected in series by two inverting amplifiers 0ΡΑ1, 八1>8 and 〇1>8 and 3 are connected to 0ΡΑ4, and can be fabricated with appropriate impedance matching. The above required signals (X, · Χ, 0.414 Χ, Υ, -Υ, and 0·414 γ). Then compare these signals according to the relationship of the third figure, combined with the comparison circuit, including: comparator CP Bu CP2, CP3, CP4, ΟΡ5, epY, CP7, CP8 ' and then combine the logic of their respective needs (four) (please With reference to the fifth 1273774 picture) U, L2, L3, L4, L5, L6, L7, L8 can each get different pulse waves? Bu? 2,? 3,? 4, 卩 5,? 6,? 7,? 8 output, after that, the signal of PI, P2, P3, P4 can be combined with the signal of P5, p6 'P7, P8 via the sluice (〇R gate) L1〇 via the yoke (〇R gate) L9. The final logic output is obtained, that is, the output signals A and B (this signal has a quadruple frequency).
此法在作較低的倍頻化技術（如四倍頻）時因硬體電路 較不複雜且訊號處理速度快，以硬體方式機構處理係較為適 合的選擇。但如要處理更高的倍頻技術時就會因硬體電路擴 t而造成系統整合與偵錯困難，此外因利用OPA作等比例分 割在電阻值匹配需有一定的準確度，否則極易造成輸出誤 差，此點在實際應用上有一定的困難。 因此’為了能達到處理更高的倍頻技術，以提高解析度， 本發明一較佳實施例係採用微處理器（如MSP-430)中的類比 數位轉換器（ADC )對:焉達所用編碼器輸出的弦波訊號作類 比，位轉換，且不斷將最新轉換值代入數學模組進行運算， ，區間分割每組弦波訊號來達到高解析度，利用此方式可使 侍整體倍頻技術都架構在程式化的基礎上，具有修改程式方 ，之優點，使得在系統需多少倍頻的回授資料時，只需修改 矛，式中的數學式即可，而無需修改硬體電路，大大增加系統 彈性同時也達到降低成本的目標。 因 再者，本發明此一較佳實施例可利用微處理器内部的 =DC將弦波訊號轉成數位值做運算，再用等比例分割方式計 t波分咖所對應醜值，最後當ADC轉讀&來的值等於 :。丨^應點時’立即可輸出一個脈波。此法的優點在於可將 |統_化且胁維修，又因倍頻化雜是_微處理器作為 具，故在倍頻數選擇上相當具有彈性，經實際測試， 刖在微處理n方面已可完成MSP_43G實現16倍頻技術。 9 1273774 本發明此一實施例經實際測試所呈現之波形圖請配合參 閱第七圖所示，由圖中可發現四個訊號，分別為一組弦波與 一組方波’弦波即為馬達轉動時由磁編碼器感測元件輸出的 第一、第二弦波訊號，可將此兩訊號輸入到MSP-430的ADC 通道，當程式啟動時ADC會以取樣週期5μδ時間間隔對這兩 弦波訊號作A/D轉變，且不斷將最新轉換值代入數學模組進行 運算，依區間分割每個弦波訊號會切出四個方波訊號(圖七所 不之方波訊號’或圖九所示之乂’、万，）。 又因有兩個方波訊琴，所以將之作互斥或邏輯運算時， 可得到更高兩倍題(八個方波)的第一個訊號，即編碼器之輸出 訊號ΡΑ(如圖九所示）。 接著利用一運算式（如三角函數之和差角公式），並使 用間單的電阻電路產生兩個弦波sin0、cos0延遲11.25度之訊 號，如圖八所示， ΚιThis method is a relatively suitable choice for hardware processing when it is used for lower frequency doubling techniques (such as quadruple frequency) because the hardware circuit is less complex and the signal processing speed is faster. However, if you want to deal with higher frequency multiplication technology, it will be difficult to integrate and debug the system due to the expansion of the hardware circuit. In addition, the use of OPA for equal-scale segmentation requires a certain degree of accuracy in resistance value matching, otherwise it is extremely easy. This causes an output error, which has certain difficulties in practical applications. Therefore, in order to achieve a higher frequency multiplication technique to improve the resolution, a preferred embodiment of the present invention uses an analog digital converter (ADC) pair in a microprocessor (such as MSP-430): The sine wave signal output by the encoder is analogized, bit converted, and the latest conversion value is continuously substituted into the mathematical module for calculation. The interval is divided into each group of chord signals to achieve high resolution, and the overall frequency doubling technique can be used by this method. On the basis of stylization, the architecture has the advantage of modifying the program side, so that when the system needs to multiply the feedback data, it only needs to modify the mathematical formula of the spear, without modifying the hardware circuit. Significantly increase the flexibility of the system while also achieving the goal of reducing costs. In addition, the preferred embodiment of the present invention can use the internal DC = DC to convert the sine wave signal into a digital value, and then use the equal division method to calculate the ugly value corresponding to the t wave coffee, and finally The ADC read & value is equal to:. When the 应^ should be clicked, a pulse wave can be output immediately. The advantage of this method is that it can be used for _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MSP_43G can be used to achieve 16 times frequency technology. 9 1273774 The waveform diagram presented by the actual test of this embodiment of the present invention should be referred to the seventh figure. Four signals can be found in the figure, which are a set of sine waves and a set of square wave 'sine waves. When the motor rotates, the first and second chord signals output by the magnetic encoder sensing component can input the two signals into the ADC channel of the MSP-430. When the program is started, the ADC will take the sampling period by 5μδ time interval. The chord signal is used for A/D conversion, and the latest conversion value is continuously substituted into the math module for calculation. Each chord signal is divided according to the interval, and four square wave signals are cut out (the square wave signal of Figure 7 is not shown) or The nine shown in the ', million,). Since there are two square wave telescopes, when they are mutually exclusive or logically operated, the first signal of the higher double problem (eight square waves) can be obtained, that is, the output signal of the encoder is as shown in the figure. Nine shows). Then use an arithmetic expression (such as the trigonometric sum and difference angle formula), and use a single resistor circuit to generate two sine waves sin0, cos0 delay 11.25 degrees signal, as shown in Figure 8, Κ
cosO sin^· COS0)cosO sin^· COS0)
Vs2 :_Δ_ 及1+及2MIK{ Rl+R2 dcos(0-(p) sin0+- COS0 sin^+- Λ_ COS0) ίαηφ = ^ /i?2 = tan(l 1.25°)«1/ 5 a =-— 及1 +及2 達到從G度至360航分為％健㈣度料丨丨·25度之效 1273774 果’並使用上述方法得到另-組四個方波訊號(®九所示之 ’’將，作互斥麵輯運算可得到更高兩倍頻(八個方波) 的第-個訊，，即編竭器之輸出訊號pB(如圖九所示）。最後 並結合編碼卜之味電路，姻pA、pB城社升緣及下 降緣」可達到兩倍頻（如32倍）高解析度的效果。 第十圖所不即為本發明另一較佳實施例整個32倍頻電路 裝置之方塊圖。 該裝置包含一相位延遲電路1〇、一第一倍頻比較電路 12、一第二倍頻比較電路14、一互斥或（N〇R)邏輯運算單 * 元16、以及一相位差解碼電路18。該相位延遲電路1〇用以供 一第一弦波訊號100與一第二弦波訊號1〇2輸入，而輸出一第 一延遲訊號104與一第二延遲訊號1〇6，彼此間具有一相位延 遲。該第一倍頻比較電路12，甩以供該第一弦波訊號1〇〇與該 第二弦波訊號102輸入，而輸出具有一第一倍頻數之第一訊號 120與一第一倍頻數之第二訊號122。該第二倍頻比較電路 14，用以供該第一延遲訊號1〇4與第二延遲訊號1〇6輸入，而 輸出具有一第一倍頻數之第三訊號140與一第一倍頻數之第 四訊號142。該互斥或（NOR)邏輯運算單元16，用接收該第 一倍頻數之第一訊號120、第一倍頻數之第二訊號122、第一 倍頻數之第三訊號140以及第一倍頻數之第四訊號142，而產 生一第二倍頻數之第一訊號160與第二訊號162，其中，該第 二倍頻數之第一訊號160與第二訊號162比該第一倍頻數之第 一訊號120、第二訊號122、第三訊號140以及第四訊號142之 倍頻數更高。該相位差解碼電路18，用以接收該第二倍頻數 之第一訊號160與第二訊號162，並計數該第二倍頻數之第一 訊说160與第二訊號162的上升緣及下降緣，而產生"—第三倍 頻數之第一訊號180與第二訊號182，其中，該第三倍頻數之 11 1273774 第一訊號180與第二訊號182比該第二倍頻數之第一訊號160 與第二訊號162之倍頻數更高。 其中，該第一倍頻比較電路12為前所述四倍頻的部分， 而第一倍頻比較電路12與第二倍頻比較電路14這兩個部分為 完全相同，第一倍頻數之第一訊號120與一第一倍頻數之第二 訊號122 (訊號/、义），就等於第五圖中比較電路的輸出訊 號A、輸出訊號B。而互斥或（NOR)邏輯運算單元16，產生 兩個八倍頻訊號PA、PB，即分別為第二倍頻數之第一訊號16〇 與第二訊號162。相位差解碼電路18為相位差九十度解碼器Vs2 : _Δ_ and 1+ and 2MIK{ Rl+R2 dcos(0-(p) sin0+- COS0 sin^+- Λ_ COS0) ίαηφ = ^ /i?2 = tan(l 1.25°)«1/ 5 a =- — and 1 + and 2 reach from G degree to 360 aeronautical range % health (four) degree material 丨丨 25 degree effect 1273774 fruit 'and use the above method to get another set of four square wave signals (® nine shows ' 'When, the mutual exclusion surface operation can get the first message of higher frequency (eight square waves), that is, the output signal pB of the editing device (shown in Figure 9). Finally, combined with the code The taste circuit, the marriage pA, pB city society rising edge and falling edge" can achieve twice the frequency (such as 32 times) high resolution effect. The tenth figure is not the same as another preferred embodiment of the present invention 32 times A block diagram of a frequency circuit device. The device includes a phase delay circuit 1A, a first frequency multiplication circuit 12, a second frequency comparison circuit 14, a mutually exclusive or (N〇R) logic operation unit*16. And a phase difference decoding circuit 18. The phase delay circuit 1 is configured to input a first sine wave signal 100 and a second sine wave signal 1 〇 2, and output a first delay signal 104 and a second delay. Signal 1〇6, There is a phase delay between the first frequency doubling circuit 12 for inputting the first sine wave signal 1 〇〇 and the second sine wave signal 102, and outputting the first signal 120 having a first octave number. And a second frequency signal 122 of the first multiple frequency. The second frequency multiplication circuit 14 is configured to input the first delay signal 1〇4 and the second delay signal 1〇6, and the output has a first multiple frequency The third signal 140 and the fourth signal 142 of the first multiplier. The mutually exclusive or (NOR) logic operation unit 16 receives the first signal 120 of the first multiplication frequency and the second signal of the first multiplication frequency. 122. The third signal 140 of the first multiplier and the fourth signal 142 of the first multiplier generate a first signal 160 and a second signal 162 of the second multiplication frequency, wherein the second frequency is the first The signal 160 and the second signal 162 are higher than the first frequency 120, the second signal 122, the third signal 140, and the fourth signal 142 of the first frequency. The phase difference decoding circuit 18 is configured to receive the signal. The first signal 160 of the second frequency and the second signal 162, and counting the second The first signal of the frequency multiplier 160 and the rising edge and the falling edge of the second signal 162 generate a first signal 180 and a second signal 182 of the third frequency, wherein the third frequency is 11 1273774 The first signal 180 and the second signal 182 are higher than the first frequency 160 and the second signal 162 of the second frequency. The first frequency comparison circuit 12 is the portion of the previously described quadruple frequency. The first frequency doubling comparison circuit 12 and the second frequency doubling comparison circuit 14 are identical, the first signal 120 of the first octave number and the second signal 122 of the first octave number (signal/, meaning ), which is equal to the output signal A and the output signal B of the comparison circuit in the fifth figure. The mutually exclusive or (NOR) logic operation unit 16 generates two eight-frequency signals PA, PB, that is, a first signal 16 〇 and a second signal 162 which are respectively the second octave number. The phase difference decoding circuit 18 is a phase difference ninety degree decoder
(quadrature encoder pulse circuit，QEP)，利用計數PA、PB訊號 的上升緣及下降緣，產生四倍頻效果' 即分別為第三倍頻數 之第一訊號180與第二訊號182。 換言之，一個弦波訊號經過八倍頻技術會產生八個脈 波，所以一個弦波週期時間内pamPB訊號會有16個脈波，而 一個脈波會有一個上升緣及一個下降緣，整個計數起來就會 有32個數值，而計數器是往上計數還是往下計數就要判斷是 訊號A相位領先B還是B領先A，以此方式即可達到32倍的效 果。 是以，經由上述說明可知，本發明可應用在各種電子設 備之編碼用途上，如運用在馬達編碼器的部分，即可提高其 解析度，將-圈原來只有200個脈波回授量提升到16〇〇個，^ 用兩種訊號的上升及下降緣，達到64_，甚至更高。若馬 達係應用在極精準的定位系統裡或極低速運轉時會有更好的 控制，使用本發·術可以將成本有效降低下來，而且 及!很簡單’具有顯著之功效增進與產業上 剌翻縣之規定，纽法提出發明專 利申凊’懇請賜予核准，實感德便。 12 1273774 准以上所述者’僅為本發明之較佳可行實施例而已，當 不能以此即限定本發明之實施範圍，舉凡依本發明專利範圍 内所作之鱗變化與修飾，皆_屬本發明專稿括之範圍 内，於此先申明之。 【圖式簡單說明】 第圖所示係本發明實施例編碼器之原始訊號與經過四倍頻 鲁訊號輸出的比較示意圖。 第—騎讀本發明實闕將_她娜度齡波以· 度做16等分的示意圖。 第二圖所示係第二圖中22·5度區間之邊界。 第四圖所示係第二圖中相對於輸出的區間圖。 第士圖所，係轉明實關四倍狀訊航值示意圖。 第六圖所*係本發明實施例四倍頻錄抗匹齡意圖。 第七圖所不係本發明實施例16倍頻經測試時所呈現之波形 圖。 • 第八圖所示係本發明實施例相位延遲電路。 ，丸圖所*係本發明實施例之32倍頻訊號示意圖。 第十圖所7F係本發明實施例之32倍頻電路裝置方塊圖。 13 1273774 第一倍頻比較電路12 互斥或（NOR)邏輯運算單元16 第一弦波訊號100 第一延遲訊號104 【主要元件符號說明】 相位延遲電路 第二倍頻比較電路 相位差解碼電路 第二弦波訊號 第二延遲訊號 第一倍頻數之第一訊號 第一倍頻數之第二訊號 第一倍頻數之第三訊號 第一倍頻數之第四訊號 第二倍頻數之第一訊號 第二倍頻數之第二訊號 第三倍頻數之第一訊號 第三倍頻數之第二訊號 14(Quadrature encoder pulse circuit, QEP), which uses the rising edge and the falling edge of the counting PA and PB signals to generate a quadruple frequency effect, that is, the first signal 180 and the second signal 182 which are respectively the third frequency. In other words, a sine wave signal will generate eight pulses after eight times of frequency, so there will be 16 pulses in the pamPB signal during a sine wave period, and one pulse will have a rising edge and a falling edge. There will be 32 values, and the counter will count up or down to determine whether the signal A phase leads B or B leads A, in this way can achieve 32 times the effect. Therefore, it can be seen from the above description that the present invention can be applied to the coding applications of various electronic devices, such as the portion of the motor encoder, which can improve the resolution, and the original circle has only 200 pulse wave feedback. To 16 ,, ^ with the rising and falling edges of the two signals, reaching 64_, or even higher. If the motor is used in a very precise positioning system or has a better control at very low speeds, the cost can be effectively reduced by using this hair and surgery, and it is very simple 'with significant efficiency enhancement and industry 剌In the case of the county, Newfa filed an invention patent application, 'please give it approval, and it is really good. 12 1273774 The above description is only a preferred embodiment of the present invention, and when it is not possible to limit the scope of implementation of the present invention, the scale changes and modifications made within the scope of the patent of the present invention are Within the scope of the invention, it is stated here first. BRIEF DESCRIPTION OF THE DRAWINGS The figure shows a comparison of the original signal of the encoder of the embodiment of the present invention with the output of the quadruple frequency signal. The first-riding-reading of the present invention is a schematic diagram in which the _herna dynasty wave is divided into 16 equal parts. The second figure shows the boundary of the 22·5 degree interval in the second figure. The fourth figure shows the interval diagram relative to the output in the second figure. The Tushi Maps Institute is a schematic diagram of the four-fold navigation value of the real-time. The sixth figure is a four-fold recording anti-sitting intention of the embodiment of the present invention. The seventh figure is not a waveform diagram presented when the frequency doubling of the embodiment 16 of the present invention is tested. • The eighth diagram shows a phase delay circuit in accordance with an embodiment of the present invention. The figure is a schematic diagram of the 32-fold frequency signal of the embodiment of the present invention. FIG. 7F is a block diagram of a 32-fold frequency circuit device according to an embodiment of the present invention. 13 1273774 First frequency doubling comparison circuit 12 Mutual exclusion or (NOR) logic operation unit 16 First sine wave signal 100 First delay signal 104 [Description of main component symbols] Phase delay circuit second frequency doubling comparison circuit phase difference decoding circuit The second signal of the second delay signal, the first frequency of the first frequency, the second signal of the first frequency, the third signal of the first frequency, the fourth signal of the first frequency, the first signal of the second frequency, the second signal Second signal of the octave number, first signal of the third octave number, second signal of the third octave number 14