!273263 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種測試系統，特別是關於一種積體電 路晶片的電路測試系統。 ψ #【先前技術】 一般而言，積體電路晶片在量產前之測試階段會外接 鲁一個測試模組，用來讀取積體電路晶片（以下稱為待測試電 路)之測試除錯運作情形，以進一步針對待測試電路進行適 當的除錯動作。 如圖1所示，一測試模組20係以複數個腳位21電連 接—待測試電路10之複數個腳位11以控制待測試電路1〇 測試除錯運作過程，其中測試模組20經由複數個腳位21 傳送之測試訊號包括高位元組位址碼A8~A15、資料寫入 控制訊號WR、資料讀取控制訊號RD、位址問鎖致能訊號 春ALE、低位元組位址碼與資料訊號AD〇〜AD7(含低位元組 位址碼A0〜A7與資料訊號D〇〜D7)、時脈訊號cpucLK、 =斷訊號INTI以及中斷訊號INTG。上述之複數個腳位u 疋以一對一的方式連接到複數個腳位21。 而^著電子產品尺寸微小化的趨勢以及開發成本之考 二’積體電路晶片的整體體積亦相對縮小，相對使得待測 路10之複數個腳位11減少，因此待測試電路10所 月b提t、的腳位數量無法符合測試模組之腳位數需求， 而無法有效連接至測試模組20，而測試模組20也無法進 5 1273263 行待測試電路ίο的測試除錯。 因此，如何提供一種電路測試系統及方法，以期在減 少待測試電路之腳位數時，仍得以藉由測試模組測試待測 試電路以檢視待測試電路測試除錯過程的情形，正是當前 • 重要課題之一。 :【發明内容】 有鑑於上述課題，本發明之目的為提供一種能夠在待 _ 測試電路減少腳位數時，仍能夠檢測待測試電路的電路測 試糸統及方法。 緣是，為達上述目的，依本發明之電路測試系統係測 試具有複數個第一腳位之一待測試電路，且包含一測試模 組以及一轉換模組。在本發明中，該測試模組具有複數個 第二腳位，並產生複數個測試訊號，其中該等第二腳位之 數量大於該等第一腳位之數量，而該轉換模組係以電連接 ’ 之方式連接該等第一腳位與該等第二腳位，以利用並列傳 ® 輸模式經由該等第二腳位接收該等測試訊號，接著利用序 列傳輸模式經由該等第一腳位傳送該等測試訊號至該待 測試電路，措以操作該待測試電路。 另外，本發明亦提供一種電路測試方法，其係應用於 一電路測試系統以測試具有複數個第一腳位之一待測試 電路，其中該電路測試系統包含一測試模組及一轉換模 組，該測試模組具有複數個第二腳位，而且該等第二腳位 之數量大於該等第一腳位之數量，此方法包含以下步驟： 6 1273263 首先，該測試模組產生複數個測試訊號，然後該轉換模組 利用並列傳輸模式經由該等第二腳位接收該等測試= 號，接著S玄轉換模組利用序列傳輸模式經由該等第一腳位 傳送該等測試訊號至該待測試電路，藉以操作該待測試= 路。 “ 承上所述，依本發明之電路測試系統係提供一轉換模 組，其係以並列傳輸模式接收來自測試模組的測試訊號，、BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a test system, and more particularly to a circuit test system for an integrated circuit chip. ψ #[Prior Art] In general, the integrated circuit chip will be connected to a test module before the mass production test to read the test circuit of the integrated circuit chip (hereinafter referred to as the circuit to be tested). The situation is to further perform appropriate debugging operations for the circuit to be tested. As shown in FIG. 1, a test module 20 is electrically connected by a plurality of pins 21 - a plurality of pins 11 of the circuit 10 to be tested to control the circuit to be tested, and the test module 20 is controlled. The test signals transmitted by the plurality of pins 21 include the high byte address code A8~A15, the data write control signal WR, the data read control signal RD, the address query lock enable signal spring ALE, the low byte address code And data signals AD〇~AD7 (including low byte address codes A0~A7 and data signals D〇~D7), clock signal cpucLK, = break signal INTI and interrupt signal INTG. The plurality of pins u 上述 are connected to the plurality of pins 21 in a one-to-one manner. However, the trend of miniaturization of electronic products and the development cost of the second integrated circuit chip are also relatively small, and the number of pins 11 of the circuit to be tested 10 is relatively reduced, so the circuit to be tested 10 is b. The number of feet in the t, can not meet the pin number requirements of the test module, and can not be effectively connected to the test module 20, and the test module 20 can not enter the test of the circuit to be tested ίο 5 1273263. Therefore, how to provide a circuit test system and method, in order to reduce the number of bits of the circuit to be tested, it is still possible to test the circuit to be tested by the test module to check the debugging process of the circuit to be tested, which is the current One of the important topics. SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a circuit test system and method capable of detecting a circuit to be tested while the number of bits of the circuit to be tested is reduced. Therefore, in order to achieve the above object, the circuit test system according to the present invention tests one of a plurality of first pins to be tested, and includes a test module and a conversion module. In the present invention, the test module has a plurality of second pins, and generates a plurality of test signals, wherein the number of the second pins is greater than the number of the first pins, and the conversion module is Electrically connecting the first pin and the second pin to receive the test signals via the second pin using the parallel transmission mode, and then using the sequence transmission mode via the first The pin transmits the test signals to the circuit to be tested, and operates to operate the circuit to be tested. In addition, the present invention also provides a circuit test method, which is applied to a circuit test system for testing a circuit to be tested having a plurality of first pins, wherein the circuit test system includes a test module and a conversion module. The test module has a plurality of second pins, and the number of the second pins is greater than the number of the first pins. The method includes the following steps: 6 1273263 First, the test module generates a plurality of test signals. And then the conversion module receives the test=numbers via the second pin by using the parallel transmission mode, and then the S-switching module transmits the test signals to the to-be-tested via the first pin by using the sequence transmission mode. Circuit to operate the test to be tested = way. According to the above, the circuit test system according to the present invention provides a conversion module that receives test signals from the test module in a parallel transmission mode,
然後以序列傳輸模式傳送測試訊號至待測試電路，7 ^M 夠在待測試電路減少腳位數時，仍能夠檢測待測試電路， 不需另行開發新的測試模組以配合減少腳位數的待測試 電路，進而節省產品開發成本。 ” 【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之電 路測試系統。 如圖2所示，依本發明較佳實施例之電路測試系統4 係測試一具有複數個第一腳位3〇1之待測試電路3〇，其中 该電路測試系統包含一測試模組4〇以及一轉換模組41。 在本貫施例中，測试模組40係具有複數個第二腳位4〇1， 且該等第二腳位401之數量大於該等第一腳位3〇1之數 量，另外轉換模組41係分別與該等第一腳位3〇1及該等 第二腳位401電連接。 在本實施例中，待測試電路30具有四個第一腳饭 3〇1，其分別用以傳送一致能控制訊號SEN、一時脈訊鰊 7 1273263 SCLK資料讯號SDAT1以及一資料訊號另外， 測试模組40至少具有二十二個第二腳位傾，其分別用以 傳送高位元組位址碼A8〜A15、一資料寫入控制訊號、 一資料讀取控制訊號RD、—位址閃鎖致能訊號剔、低 位元組位址碼與資料訊號AD〇〜Α〇7、一時脈訊號 CPUCLK中斷:為虎INTl以及—中斷訊號游〇。 K上二斤述測试模組4〇係產生複數個測試訊號，亦 = 2第一腳位4〇1所傳送的訊號，藉由轉換模組41 Γοΐ 30 , 雪作(此稱為㈣寫人週期）。而當待測試 Γ二ΓΓ試訊號進行相對應的測試除錯動作之 後，會產生一對應的執行妗果 I Μ 〇 σ ;U，此時該等執行結果訊 !傳送回測試模級啊^ =:=則試電路w 並萨由m θ生中斷訊號1Ντ〇或中斷訊號匪， 並精由邊4第一腳位301將中 4，其中中斷訊號_=事:傳二電路， SDAT1、SDat〇傳送 要疋透過貝枓訊號 主要是在Λ、祆、1。轉換模組41的功能 再時將該等、號閃_·， 路30(此稱^庠$丨值:立301輸出該等測試訊號至待測試電 路3〇(此稱為序列傳輪模 接收執行結果訊號並問鎖住，並—f由該4第—腳位301 號至測試模組4〇(此稱為並列傳輸彳^)出料執行結果訊 在本實施例中，該等測試訊號包括資料寫入控制訊號 8 1273263 WR、資料讀取控制訊號RD、位址閂鎖致能訊號ALE、高 位元組位址碼A8~A15以及低位元組位址碼與資料訊號 ADO~AD7。這些測試訊號係以並列傳輸模式經由該等第二 腳位401傳送至轉換模組41。然後，轉換模組41係將接 收之測試訊號以序列傳輸模式經由該等第一腳位3〇1傳送 至待測試電路30。此時轉換模組41係依據這些測試訊號 輸出致能控制訊號SEN、資料訊號SDAT1、SDAT〇至待 測試電路30，藉以操作待測試電路3〇。換句話說，由測 試模組40所發出的高位元組位址碼A8~a15、低位元組位 址碼與資料訊號AD0-AD7或是待測試電路30所發出的中 斷訊號INTI、INTO皆可透過資料訊號SDAT^、SDAT〇來 傳送。 再者’在本實施例中，待測試電路3〇所產生之執行 結果訊號係以序列傳輸模式經由該等第一腳位3〇1傳送至 轉換模組41，其中執行結果訊號係透過資料訊號sdati、 SDAT0來傳送。然後’轉換模組41係將所接收之資料訊 號SDAT1、SDAT0(亦即執行結果信號）以並列傳輸模式經 由該等第二腳位401傳送至測試模組4〇。 另外，在本實施例中，中斷訊號INT1、INT〇係也透 過資料訊號SDAT1、SDAT0傳送至轉換模組41。接著， 轉換模組41將所接收之資料訊號SDAT1、SDAT〇(亦即中 斷訊號INT1、INTO)以並列傳輸模式經由該等第二腳位4〇工 傳送至測試模組40。 除此之外，待測試電路30更可以至少包含一解碼/編 9 1273263 碼單元(圖未示），其係用以將輸人至待測試電路3Q的測^ 訊號由序列傳輸模式轉換成並列傳輸模式，另外，其亦^ 以將待輸出至轉換模組41的執行結果訊號與中斷訊號 INTI、INTO由並列傳輸模式轉換成序列傳輸模式，以產u 生資料訊號SDAT1、SDAT0。 如圖3所示，為使本發明更加清楚，以下將參照圖示、 並以一資料寫入週期為例，說明利用電路測試系統4測試 待測試電路30的機制，其中圖3為資料寫入週期之時序 圖。首先，在時間t〇~t6之間，自轉換模組41傳送至待測 試電路30的致能控制訊號SEN為高準位，以便針對待測 試電路30進行測試，其中致能控制訊號SEN係依據從測 試模組40輸出至轉換模組41的資料寫入控制訊號WR而 產生。此時待測試電路30提供適當之時脈訊號SCLK至 轉換模組41，而資料訊號SDAT1、SDAT〇係於待測試電 路30與轉換模組41之間傳送。在本實施例中，於時間ti〜t2 之間，資料訊號SDAT1、SDAT0 ·係經由轉換模組41傳送 至測試模組40，以通知測試模組4〇可以輸出測試訊號， 如前述之咼位元組位址碼A8〜A15、及低位元組位址碼與 資料訊號ADO〜AD7(含低位元組位址碼A0〜A7與資料訊 號DO〜D7)。其次，在時間t2~t3之間，資料訊號SDAT1包 含依序傳送之8個高位元位址碼A15〜A8，而資料訊號 SDAT0包含依序傳送之8個低位元位址碼A7~A0,其係經 由轉換模組41傳送至待測試電路3〇。接著，在時間t3〜t4 之間，資料訊號SDAT1包含依序傳送之4個資料訊號 1273263Then, the test signal is transmitted to the circuit to be tested in the sequence transmission mode, and 7 ^M can still detect the circuit to be tested when the circuit to be tested reduces the number of bits, and does not need to develop a new test module to reduce the number of bits. The circuit to be tested, thereby saving product development costs. [Embodiment] A circuit test system according to a preferred embodiment of the present invention will be described with reference to the related drawings. As shown in FIG. 2, a circuit test system 4 according to a preferred embodiment of the present invention has a plurality of tests. The circuit to be tested is 3 一1, wherein the circuit test system includes a test module 4〇 and a conversion module 41. In the present embodiment, the test module 40 has a plurality of second The foot position is 4〇1, and the number of the second foot positions 401 is greater than the number of the first foot positions 3〇1, and the conversion module 41 is respectively associated with the first foot positions 3〇1 and the same The second pin 401 is electrically connected. In this embodiment, the circuit to be tested 30 has four first feet 3〇1, which are respectively used for transmitting the uniform energy control signal SEN, a clock signal 7 1273263 SCLK data signal SDAT1. And a data signal. In addition, the test module 40 has at least twenty-two second pin positions, which are respectively used to transmit the high-order byte address codes A8-A15, a data write control signal, and a data read control. Signal RD, address flash lock enable signal tick, low byte address code and capital Material signal AD〇~Α〇7, one clock signal CPUCLK interrupt: for Tiger INTl and - interrupt signal game. K on the two pounds test module 4 system generates a plurality of test signals, also = 2 first foot The signal transmitted by 4〇1 is generated by the conversion module 41 Γοΐ 30, snow (this is called (4) writer cycle), and when the test signal to be tested is subjected to the corresponding test debugging action, it will be generated. A corresponding execution result I Μ 〇 σ; U, at this time, the execution result is transmitted back to the test mode level ^ =: = then the test circuit w and the m θ interrupt signal 1 Ν 〇 or interrupt signal 匪, And the first foot 301 of the side 4 will be 4, in which the interrupt signal _= thing: the second circuit, SDAT1, SDat〇 transmission through the Bellow signal is mainly in Λ, 祆, 1. The conversion module 41 When the function is repeated, the number flashes _·, the road 30 (this is called ^庠$丨 value: the vertical 301 outputs the test signal to the circuit to be tested 3〇 (this is called the sequence transmission mode receives the execution result signal and asks Locked, and -f from the 4th - pin 301 to the test module 4 〇 (this is called parallel transmission 彳 ^) discharge execution results in this embodiment The test signals include data write control signal 8 1273263 WR, data read control signal RD, address latch enable signal ALE, high byte address code A8~A15, and low byte address code and data. Signals ADO~AD7. These test signals are transmitted to the conversion module 41 via the second pin 401 in a parallel transmission mode. Then, the conversion module 41 passes the received test signals in the sequence transmission mode via the first pins. The bit 〇1 is transmitted to the circuit to be tested 30. At this time, the conversion module 41 outputs the enable control signal SEN and the data signal SDAT1, SDAT 依据 to the circuit to be tested 30 according to the test signals, thereby operating the circuit to be tested 3〇. In other words, the high byte address code A8~a15, the low byte address code and the data signal AD0-AD7 issued by the test module 40 or the interrupt signals INTI and INTO issued by the circuit to be tested 30 can be used. Transmitted via the data signals SDAT^, SDAT〇. In the present embodiment, the execution result signal generated by the circuit to be tested is transmitted to the conversion module 41 via the first pin 3〇1 in a sequence transmission mode, wherein the execution result signal is transmitted through the data signal. Sdati, SDAT0 to transfer. Then, the conversion module 41 transmits the received data signals SDAT1, SDAT0 (i.e., execution result signals) to the test module 4 via the second pin 401 in a parallel transmission mode. Further, in the present embodiment, the interrupt signals INT1, INT are also transmitted to the conversion module 41 via the data signals SDAT1, SDAT0. Then, the conversion module 41 transmits the received data signals SDAT1, SDAT〇 (i.e., the interrupt signals INT1, INTO) to the test module 40 via the second pin 4 in a parallel transmission mode. In addition, the circuit to be tested 30 may further include at least one decoding/encoding 9 1273263 code unit (not shown) for converting the measurement signal input to the circuit to be tested 3Q from the sequence transmission mode to the parallel. In the transmission mode, the execution result signal and the interrupt signals INTI and INTO to be outputted to the conversion module 41 are converted from the parallel transmission mode to the serial transmission mode to generate the data signals SDAT1 and SDAT0. As shown in FIG. 3, in order to make the present invention clearer, the mechanism for testing the circuit to be tested 30 by the circuit test system 4 will be described below with reference to the drawings and taking a data write cycle as an example, wherein FIG. 3 is a data write. Timing diagram of the cycle. First, between time t 〇 and t6, the enable control signal SEN transmitted from the conversion module 41 to the circuit to be tested 30 is at a high level for testing the circuit 30 to be tested, wherein the enable control signal SEN is based on The data output from the test module 40 to the conversion module 41 is written by the control signal WR. At this time, the circuit to be tested 30 supplies the appropriate clock signal SCLK to the conversion module 41, and the data signals SDAT1 and SDAT are transmitted between the circuit to be tested 30 and the conversion module 41. In this embodiment, between time ti and t2, the data signals SDAT1 and SDAT0 are transmitted to the test module 40 via the conversion module 41 to notify the test module 4 that the test signal can be output, such as the aforementioned clamp. The tuple address codes A8 to A15, and the low byte address code and the data signals ADO to AD7 (including the low byte address codes A0 to A7 and the data signals DO to D7). Secondly, between time t2 and t3, the data signal SDAT1 includes 8 high-order address codes A15~A8 transmitted sequentially, and the data signal SDAT0 includes 8 low-order address codes A7~A0 sequentially transmitted. It is transmitted to the circuit to be tested 3〇 via the conversion module 41. Then, between time t3 and t4, the data signal SDAT1 contains four data signals sequentially transmitted 1273263
DhD4,而資料訊號SDATG包含依序傳送之*個資料^號 D3~D0，其係經由轉換模組41傳送至待測試電路％5。然: 後，在時間t4~t5之間，暫停傳送寫入之時脈訊號叱Μ、’、、 而資料訊號SDAn、SDATG不具有f料訊號。最後 -間以之間’資料訊號SDAT1、SDAT〇得經 且 ;傳送至測賴組4〇，以通知結束測試。由圖3可^， :當待測試電路3〇發生中斷事件時，中斷訊號附0 訊號INTI亦分別透過資料訊號 一 眷來傳送。 Ai0次貝枓讯垅SDAT1 照圖圖;::敗為:吏本發明更峨^ 統4讀取待測試電路’說明利用電路剛試系 中圖4為資料1 產生之執仃結果訊號的機制，其 自轉換模組41偟、、， 曰凡你T间t〇〜t7j 為高準位，μ以❹m電路3G的魏控制訊號 模組4/1 取週期之時序圖。首先，在時間W之間， SEN 訊 ，以俤紅 工φί矶妮S】 號傳送回n路_2將制試電路3G產生之執行結果訊 從測試模!且4〇 統4 ’其中致能控制訊號咖係依據 RD而產生。^出至轉換模組41的資料讀取控制訊號 SCLK至轉換^、’待測試電路3G提供適當之時脈訊號 測試電路30、與^ 41 ’而資料訊號·Τ1、SDAT〇係於待 時間t广t2之門換模組41之間傳送。在本實施例中，於 組W傳送至二資料訊號SDAT1、SDAT〇係經由轉換模 铉袖 > 认《 、式挺級40,以通知測試模組40可以接收該 專執仃結果訊鞔。 唸 包含依序傳送8 t在時間㈣之間，資料訊號SDAT1 ' 個高位元位址碼A15~A8，而資料訊號 11 1273263 士絲二包3依序傳送之8個低位元位址碼A7〜Αί)，其係經 紅^模、、且Μ傳送至測試模組4〇。接著，在時間t3〜t4之 貝τ料傳輸’而在時間U〜t5之間暫停傳送讀取之時脈訊 ί 然後’在時間W之間，資料訊號S丽包含 入佑皮送之4個貢料訊號D7〜04，而資料訊號SDAT0包 Γο 皇、、傳送之4個貧料訊號D3〜D〇，其係經由待測試電路 矣曰达至轉換模組41，然後自轉換模組41傳送至測試模 “、、後在時間t6〜t?之間，資料訊號SDArn、SDAT0 门、^轉換模组41傳送至測試模組.以通知結束測試。 同樣地，由圖4可知，主、 中斷訊號mTG或發生中斷事件時， ςηΑΤΛ ή ^斷·^ ΙΝτι亦分別透過資料訊號 SD與育料訊號SDAT1來傳送。 上、本，明亦揭露—種電路測試方法，其係應用於 試；路30路測忒系統^以測試具有複數個第-腳位之待測 :、共勹入卓如圖5所不’依本發明較佳實施例之電路測試 方法包：步驟S〇1至步驟S06，其詳細說明敘述如下。 味〜在步驟SG1中’由測試模組產生複數個測試訊 二:Γ:寫入控制訊號WR、資料讀取控制訊號rd、位 ㈣號ale、高位元組位址碼w、低位元 、、、位址碼A0〜A7以及資料訊號D〇〜D7。 在步驟S02中，轉換模組係。以並列傳輸模式自 組接收測試訊號。詳言之，轉換模組與測試模組之 間透過複數個第二腳位互相連接，例如至少二十二根第二 腳位，以便分別透翁腳位接收對應之測試訊號(並列傳輸 12 1273263 模式）° 然後，在步驟S03中，轉換模組係以序列傳輸 送測試訊號至待測試電路。詳言之，轉換模組與㈣= 路之間透過複數個第-紗互相連接，例_根第 ^位，以便將複數個測試訊號經由同一拇# :(序列傳輸模式）。 根第一腳位進行傳輸 之後，在步驟S〇4中，符測試電路依據測試訊號產生 至少一執行結果訊號，例如為所讀取 籲或是中斷訊號mT1、麵。 之貝枓顧的， 接著，在步驟S05中，轉換模組係再以序列傳輪 接收執行結果訊號。如前所述，數個勃 、工 由同:根第-腳位進行傳輸(序列傳輪^)。果訊號可以經 最後，在步驟S06中，轉換模組 送執行結果訊號至測試模組。如前===傳 以分別透過對應之各腳位傳到並列傳輪模 =:果㈣可 然後以序列傳輸模式傳:測試訊二=模，的測試訊號， 該轉換模組也可以序列傳輪模二二= 執行結果訊號，然後以* η 收术自待測試電路的 此在待測試電路減少聊么數^輪模式傳送至測試模組。因 仍能夠檢測待測試電路，=，依本發明之電路測試系統 合減少腳位數的待㈣^另㈣發新的測試模組以配 本。 。电路，進而能夠節省產品開發成 13 1273263 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範疇，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 【圖式簡單說明】 圖1係顯示習知電路測試系統之一區塊圖； 圖2係顯示依本發明較佳實施例之電路測試系統之一 區塊圖； 圖3係顯示依本發明較佳實施例之電路測試系統之資 料寫入週期的時序圖； 圖4係顯示依本發明較佳實施例之電路測試系統之資 料讀取週期的時序圖；以及 圖5係顯示依本發明較佳實施例之電路測試方法的流 程。 元件符號說明： 10、 30 :待測試電路 11、 21 :腳位 20、40 :測試模組 301 ··第一腳位 4:電路測試系統 401 ··第二腳位 41 :轉換模組 A0-A7 :低位元組位址碼 1273263 A8~A15 ··高位元組位址碼 ADO〜AD7 ··低位元組位址碼與資料訊號 ALE :位址閂鎖致能訊號 CPUCLK、SCLK :時脈訊號 ，D0~D7:資料訊號 T INTO、INT1 ··中斷訊號 ：RD ··資料讀取控制訊號 SDAT0、SDAT1 :資料訊號 • SEN ··致能控制訊號 S01~S06 :電路測試方法 t〇~t7 :時間 WR :資料寫入控制訊號 15DhD4, and the data signal SDATG includes the *data number D3~D0 transmitted sequentially, which is transmitted to the circuit to be tested %5 via the conversion module 41. However, after the time t4~t5, the clock signal 叱Μ, ', and the write signal is paused, and the data signals SDAn and SDATG do not have the f-signal. Finally, the data signal between SDAT1 and SDAT is transmitted to and from the test group to notify the end of the test. From Fig. 3, when the interrupt event occurs in the circuit to be tested, the interrupt signal with the 0 signal INTI is also transmitted through the data signal. Ai0 times 枓 枓 SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD The self-conversion module 41偟,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, First of all, between the time W, the SEN message is sent back to the n way by the 俤 工 φ 矶 矶 _2 _2 _2 _2 _2 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制The control signal is generated based on the RD. The data read control signal SCLK to the conversion module 41 is supplied to the conversion module 41. The circuit to be tested 3G provides an appropriate clock signal test circuit 30, and ^41', and the data signal Τ1, SDAT is tied to the waiting time t. The door of the wide t2 is transferred between the modules 41. In this embodiment, the group W is transmitted to the two data signals SDAT1, SDAT, and the mode is determined by the conversion module > to notify the test module 40 that the result of the task can be received. The reading includes sequentially transmitting 8 t between time (four), data signal SDAT1 'high bit address code A15~A8, and data signal 11 1273263 士丝二包3 sequentially transmitting 8 low bit address code A7~ Αί), which is transmitted to the test module 4 via a red die. Then, at time t3~t4, the material is transmitted, and the time of transmission is read between time U and t5. Then, between time W, the data signal S is included in the 4 The tribute signal D7~04, and the data signal SDAT0 package Γ 、 、, the transmission of the four poor material signals D3~D〇, which are transmitted to the conversion module 41 via the circuit to be tested, and then transmitted from the conversion module 41 After the test mode "," and between time t6 and t?, the data signal SDArn, SDAT0, and the conversion module 41 are transmitted to the test module to notify the end of the test. Similarly, as shown in Fig. 4, the main and the interrupt are When the signal mTG or the interruption event occurs, ςηΑΤΛ ή ^断·^ ΙΝτι is also transmitted through the data signal SD and the breeding signal SDAT1. The above, this, and the Ming also expose a circuit test method, which is applied to the test; The road test system ^ is tested to have a plurality of first-pin positions to be tested: a total of the circuit test method package according to the preferred embodiment of the present invention is as shown in FIG. 5: steps S〇1 to S06, The detailed description is as follows: Taste ~ is generated by the test module in step SG1 Several test messages 2: Γ: write control signal WR, data read control signal rd, bit (four) number ale, high byte address code w, low bit, , address code A0~A7, and data signal D〇 ~D7. In step S02, the conversion module is configured to receive the test signal in a parallel transmission mode. In detail, the conversion module and the test module are connected to each other through a plurality of second pins, for example, at least twenty. Two second pins are arranged to receive corresponding test signals (parallel transmission 12 1273263 mode) respectively. Then, in step S03, the conversion module transmits the test signals to the circuit to be tested in sequence transmission. The conversion module is connected to the (four)= road through a plurality of first-yarns, for example, the root_th position, so that the plurality of test signals are transmitted through the same thumb#: (sequence transmission mode). After the transmission, in step S〇4, the character test circuit generates at least one execution result signal according to the test signal, for example, the read or interrupt signal mT1, the surface of the signal, and then, in step S05, Conversion module The transmission wheel receives the execution result signal. As mentioned above, several Bo, the work is the same as: the root-pin position transmission (sequence transmission ^). The fruit signal can be finally passed, in step S06, the conversion module is sent to execute The result signal is sent to the test module. If the previous === pass is transmitted to the parallel transmission mode through the corresponding pin position respectively:: (4) can then be transmitted in the sequence transmission mode: test signal = test mode, the test signal, The conversion module can also transmit the wheel mode 2 = the execution result signal, and then transmit the test signal to the test module by the number of the circuit to be tested in the circuit to be tested by * η. Test circuit, =, according to the circuit test system of the present invention, the number of bits to be reduced is reduced (four) ^ another (four) to send a new test module to match the book. . The circuit, which in turn saves product development, is described above and is not intended to be limiting. Any equivalent modifications or alterations to the spirit and scope of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a conventional circuit test system; FIG. 2 is a block diagram showing a circuit test system according to a preferred embodiment of the present invention; FIG. 4 is a timing diagram showing a data read cycle of a circuit test system in accordance with a preferred embodiment of the present invention; and FIG. 5 is a preferred embodiment of the present invention. The flow of the circuit test method of the embodiment. Component symbol description: 10, 30: circuit to be tested 11, 21: pin 20, 40: test module 301 · · first pin 4: circuit test system 401 · · second pin 41: conversion module A0- A7: low byte address code 1272263 A8~A15 · high byte address code ADO~AD7 · low byte address code and data signal ALE: address latch enable signal CPUCLK, SCLK: clock signal , D0~D7: Data signal T INTO, INT1 ·· Interrupt signal: RD ·· Data read control signal SDAT0, SDAT1: Data signal • SEN ··Enable control signal S01~S06: Circuit test method t〇~t7 : Time WR: data write control signal 15