l272565 t脈波寬度調整控制電踗Γ p ^L272565 t pulse width adjustment control power 踗Γ p ^
Cir .十 PWMr. ·η ( SeWldthM—nCir.10 PWMr. ·η ( SeWldthM-n
Circuit,PWM Circuit) 42之古十皇 聲41對脈波寬度調整控制電路42乂 J 1數輸入界 替样rPWM r十】P ·路42輪脈波寛度調整控制 戾錄(PWM Control Registe )機制來 功率(PWMDuty)輸出。)㈣末决疋脈波寛度調整 請參閱圖八A、B、C所示,係分別. _素電容為小、中、大負載二為=明利用液晶顯 ,度週整功杨—』,其中複數共點 曰曰顯示器之晝素電容進行充電動作,者 ”一叩、貝子液 電容的電容值越大,表示可提供带、、六奋曰曰”、、員不為之晝素 ♦、 扠仏包流充電的時間越長,於 嘵流轉態時充份提供晝素電容所需I 、 ^ , 而受<大電流後,書素雷 各之放電動作即可達到長時間的穩壓狀態。 ,、 藉由該介面來設定若干位元(bit)之脈波宽度調整控 制登錄機制,以選擇最佳脈波寬度調整輸出,以維持最佳 液晶顯示态之顯示品質,以及達到最佳之省電效果。 ^請參閱圖五所示,係為本發明脈波寬度調整控制之轉態 ^號不意圖,其中脈波寛度調整控制於轉態至正半週時, 可將分壓電路致能(Enable),換言之為對電路進行充電動 作,待共點與節點電壓穩定後(代表轉態至負半週),分壓 電路利用晝素電容及分壓電容來維持電壓,此時分墨電路 毋需動作,亦代表分壓電路不會消耗電流,因此可有效p 低電流之消耗。 請參閱圖七所示,係為本發明液晶電容負载對應共點與 節點轉態信號示意圖,設計者可根據液晶顯示器所提供負 載規格及積體電路(IC)之驅動能力,利用查表方式來決 1272565 定最佳之脈波寛度調整功峯Γ异 ^ 门正功丰该取佳之脈波寛度調整功率 乃才日可驅動複數分壓電路之最小電流值,八十— ,若干位元(bit)之脈波宽度調整控制登數: 至正半週時’可將分昼電路致能( :壓隨㈣之分壓電容、共點及節輯行充電 子 ==定後(代表轉態至負半週),電壓由該分壓電容 :ί=:維持,此時分— 藉由上述圖三至圖八c之揭露,即可瞭 之 容負載節點處,据供,ΐ 液晶顯示器之複數電 貝戰即‘,,,占處,如供一穩定之驅 r脈波寛度調整(Pulse咖hM_latl:二之 透過後數共點、節點來控制分®電阻及電®隨辑器 動功率’當電壓穩定後即關閉脈波整二 由電容負載來穩壓,利用本發 =路乂 貝戟;做5又相整,皆可達到顯示器做一良好 及P牛低驅動電流達到省雷之曰沾 * ' ' 進的領域t,二;::::果於==器的製程* 尋求專利權之保護。果’故提出專利案申請以 之進步性,明案在目的及功效上均深富實施 見之運用:業價值,且為目前市面上前所未 專利之要件精神所述,本發明案完全符合發明 1272565 唯以上所述者,僅為本發明之較佳實施例而已,當不能 以之限定本發明所實施之範圍,即大凡依本發明申請專利 範圍所作之均等變化與修飾,皆應仍屬於本發明專利涵蓋 之範圍内,謹請 貴審查委員明鑑,並祈惠准,是所至 禱。 【圖式簡單說明】 圖一係為習知液晶顯不器利用分壓電阻所組成之分壓電路 圖。 圖二係為係於圖一架構於分壓電阻之一端點加入一穩壓電 路圖。 圖三係為本發明省電型液晶顯示裝置之功能方塊圖。 圖四係為本發明省電型液晶顯示裝置之信號對照圖。 圖五係為本發明脈波寬度調整控制之轉態信號示意圖。 圖六係為本發明省電型液晶顯示裝置之較為詳細電路圖。 圖七係為本發明液晶電容負載對應共點與節點轉態信號示 意圖。 圖八A係為本發明利用液晶顯示器晝素電容為小負載時之 分壓電路致能之脈波寬度調整功率信號示意圖。 圖八B係為本發明利用液晶顯示器畫素電容為中負載時之 分壓電路致能之脈波寬度調整功率信號示意圖。 圖八C係為本發明利用液晶顯示器晝素電容為大負載時之 分壓電路致能之脈波寬度調整功率信號示意圖。 【主要元件符號說明】 1272565 1〜分壓電阻 2〜穩壓電路 3〜電壓隨耦器 31〜運算放大器 32〜分壓電容 41〜參數輸入界面 42〜脈波寬度調整控制電路 43〜計數控制電路 44〜穩壓電路 45〜分壓電路 451〜分壓電阻 452〜電壓隨耦器 4521〜運算放大器 4522〜分壓電容 46〜液晶顯示器驅動器 461〜共點 462〜節點Circuit,PWM Circuit) 42 ancient ten emperor 41 pairs of pulse width adjustment control circuit 42乂J 1 number input boundary substitute rPWM r ten] P · road 42 pulse wave temperature adjustment control record (PWM Control Registe) Mechanism to power (PWMDuty) output. (4) At the end of the decision, please refer to Figure VIII, A, B, and C for the adjustment. _ Prime capacitor is small, medium, and large load II = Ming use liquid crystal display, degree week work Yang - 』 In the case where a plurality of pixel capacitors of a plurality of displays are charged for charging, "the larger the capacitance value of the capacitors of a 叩 叩 贝 液 , , , 越大 越大 越大 ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ The longer the charging time of the forked bag is, the more I and ^ are needed to provide the halogen capacitor in the turbulent state, and the large discharge current, the discharge action of the book Sulei can achieve long-term stability. Pressure state. , by using the interface to set a pulse width adjustment control registration mechanism of a bit to select an optimal pulse width adjustment output to maintain the optimal liquid crystal display quality and achieve the best province Electric effect. ^ Please refer to FIG. 5, which is the intention of the pulse width adjustment control of the present invention, wherein the pulse wave twist adjustment is controlled to the positive half cycle, and the voltage dividing circuit can be enabled ( Enable), in other words, charging the circuit. After the common point and the node voltage are stable (representing the transition state to the negative half cycle), the voltage dividing circuit uses the halogen capacitor and the voltage dividing capacitor to maintain the voltage. No action is required, and it means that the voltage divider circuit does not consume current, so it can effectively consume low current. Please refer to FIG. 7 , which is a schematic diagram of the liquid crystal capacitor load corresponding to the common point and the node transition state signal. The designer can use the table lookup method according to the load specifications provided by the liquid crystal display and the driving capability of the integrated circuit (IC). Determined the best pulse wave degree adjustment power peak difference ^ Gate positive power Feng this good pulse wave degree adjustment power is the minimum current value that can drive the complex voltage divider circuit, eighty - several The pulse width adjustment control number of the element (bit): When the positive half cycle is reached, the branch circuit can be enabled (: voltage divider (4) voltage divider capacitor, common point and section line charge sub-character == fixed (representative Transition to negative half cycle), the voltage is divided by the voltage divider capacitor: ί=:, at this time - by the above-mentioned Figure 3 to Figure 8c, the load node can be used, according to the supply, ΐ LCD The multiple electric warfare of the display is ',,, occupying, for example, for a stable drive r pulse wave adjustment (Pulse coffee hM_latl: two after the total number of points, the node to control the point о resistance and electricity о The power of the device 'When the voltage is stable, the pulse wave is turned off. The capacitor is regulated by the capacitive load. Send = road 乂 乂 戟; do 5 and phase, can achieve a good display and P cattle low drive current to achieve the thunder of the mine * ' ' into the field t, two;:::: fruit === The process of the device* seeks the protection of the patent right. Therefore, the application for the patent case is progressive, and the purpose and efficacy of the case are well implemented. See the application: industry value, and it is currently unpatented on the market. In the spirit of the present invention, the present invention is fully in accordance with the invention, and is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the scope of the patent application of the present invention. The equal changes and modifications should still fall within the scope of the patent of the present invention. I would like to ask your review committee to give a clear explanation and pray for it. It is the prayer. [Simplified illustration] Figure 1 is a conventional LCD display. The voltage divider circuit diagram of the voltage dividing resistor is used. Figure 2 is a voltage-stabilizing circuit diagram attached to one end of the voltage-dividing resistor in Figure 1. Figure 3 is a functional block diagram of the power-saving liquid crystal display device of the present invention. Figure 4 is the main issue Fig. 5 is a schematic diagram of a transition signal of the pulse width adjustment control of the present invention. Fig. 6 is a detailed circuit diagram of the power saving type liquid crystal display device of the present invention. The invention relates to a schematic diagram of a liquid crystal capacitive load corresponding to a common point and a node transition state signal. FIG. 8A is a schematic diagram of a pulse width adjustment power signal enabled by a voltage dividing circuit when a liquid crystal display halogen capacitor is used as a small load. It is a schematic diagram of the pulse width adjustment power signal which is enabled by the voltage dividing circuit when the liquid crystal display pixel capacitor is a medium load according to the present invention. FIG. 8C is a partial voltage when the liquid crystal display halogen capacitor is used as a large load. Schematic diagram of the pulse width adjustment power signal enabled by the circuit. [Main component symbol description] 1272565 1~ Voltage divider resistor 2~ Voltage regulator circuit 3~ Voltage follower 31~ Operational amplifier 32~ Voltage divider capacitor 41~ Parameter input interface 42 to pulse width adjustment control circuit 43 to counting control circuit 44 to voltage stabilization circuit 45 to voltage dividing circuit 451 to voltage dividing resistor 452 to voltage follower 4521~ Dividing capacitor operational amplifier 4522~ 46~ liquid crystal display driver 461~ common node point 462~