1271874 ί 九、發明說明： 【發明所屬之技術領域】 本發明係有關於—種半導體封裝電路板之結構及並 製法，尤指-種底穴置晶型球栅陣列型式（cavi，d_ ball gnd amy，CDBGA)封裝電路板結構。 【先前技術】1271874 ί 九 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明Amy, CDBGA) package circuit board structure. [Prior Art]
隨者電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、局性能的研發方向。為滿足半導體封裝件高積卑卢 (Integration )以及微型化（Miniatm.izati〇n )的封裝需^， 半導體晶片於運作時所產生之熱量將明顯增加，如不及時 將半導體晶j產生之熱量有效逸散，將嚴重縮短半導體晶 片之性能及壽命；此外，—般半導體封裝件缺乏有效遮 效果（Shading)，將使其容易受到外界電磁及雜訊之干 擾，而嚴重影響其運作功能。With the rapid development of the electronics industry, electronic products have gradually entered the research and development direction of multi-functional and local performance. In order to meet the packaging requirements of semiconductor package parts, integration and miniaturization (Miniatm.izati〇n), the heat generated by the semiconductor wafer during operation will increase significantly, such as the heat generated by the semiconductor crystal j. Effective dissipation will severely shorten the performance and lifetime of semiconductor wafers. In addition, the lack of effective shielding for semiconductor packages will make them susceptible to external electromagnetic and noise interference, which will seriously affect their operational functions.
請參閱帛及第⑺圖，為解決上述問題，業界於是 發展出-種底穴置晶型球栅陣列型式（Cavi㈣。· _ gHdarray,CDBGA)封裝結構，此f知之封裝結構包含有 -⑽H)、-散熱件12、至少一半導體晶片13、複數 條焊線14、一封裝膠體15以及複數焊球16。 該電路板10具有一正面10a和—背自_，且㈣ 至少一開口丨(Η，其中，該電路板1〇上對應開口 ι〇ι之 壁110(side wall)内周圍區域形成有接地環u，且在該開 101之側壁HO (Sidewall)形成有一與該接地環二連幵; 之金屬保護層112’而該金屬保護層112係如鎳/金層， 18482 6 1271874 藉由鍍覆該金屬保護層112來 、， 該雷敗拓1Π — * 小θ刀接地面積，亚用以保護 二路板之表面電性連接墊17及接地ifll之接地 二：不❹境之氧化而損壞，從而可 良好之_果，防止其受到外界= 1俜二」12的材貝為一例如為銅之高導熱性材料，且 :二二黏著層12a接置在該電路板10的背 ， ，该電路板10形成開口 101朝下之底 面 13b(Inactive surface)，且方“歹丰私品 1Q1 ；丑方、该主動面13a上具有電極墊 。於組裝過程中，係將半導體晶片 的開口 101中，並將直非主 接置方、甩路板1〇 接卫肘，、非主動面13b黏結至散熱件12;缺 打線製程’藉以利用焊線14將半導 ; =塾⑶電性連接至該電路板1〇表面之電性連接整 封^地環11 ;接著，進行—封裝膠體製程，藉此而形成 、衣知體15來完全包覆半導體晶片13和焊線14;之後， 進打-植球製程，藉此而於電路板1〇的正面…上植 數個焊球16。此即完成該底穴置晶型球 (CDBGA)封裝結構。 Λ ^述之⑶遍縣結财，該電路板之製造方法， 係如弟2A至2H圖所示。 、、請參閱第則，首先提供一表面具有銅層2〇1之核 '板20，且該核心板20具有一開口 2〇2。 請參閱第2B® ’於該核心板2〇表面及其開口 2〇2内 之表面形成一金屬層21。 18482 7 1271874 請參閱第2C圖，於該金屬層21的表面形成一 Lpi層 22(Liqmd Photo Image ph〇to resister，液態感光顯 阻），接著該LPI層22進行圖案化製程，以於該開口 2〇2 内的金屬層21表面形成一 LP][層22，而得藉由該Lpi層 22覆蓋在開口 2〇2内的金屬層21表面上。 w芩閱第2D圖，再於該金屬層21及LPI層22表面 形成一阻層23,且該阻層23形成在[朽層^表面上。 φ 請麥閱第2E圖，該阻層23進行圖案化製程，以於該 阻層23上形成用以顯露出部分金屬層21之開口 。 • 請參閱第2F圖，之後以蝕刻移除未被阻層23所覆蓋 •之金屬層21以形成一圖案化金屬層21〇,即可在核心板^ 的表面形成線路及電性連接墊21a，並在開口 2Q2内的側 i上形成接地環21 b。 ^請參閱第2G圖，然後移除該阻層23及LPI層22,接 :於忒具有圖案化金屬層210之電路板1〇上形成一係如防 ⑩知層（solder mask)之絕緣保護層24，且該絕緣保護層以 上形成有開孔240用以顯露出圖案化金屬| 21〇之電性連 接墊2la及接地環21b。 凊麥閱第2H圖，最後於該電性連接塾…及接地環 21b的表面藉由電鍍形成—係如錄/金層之金屬保護層… 相對於核心板20之線路來說，該核心板2〇之開口 2们 =面f貝較大’當該金屬層21經圖案化製程而成為圖案化金 蜀層广〇後’若直接進行移除非阻層23所覆蓋之金屬層’ 知，該開口 202之側壁表面的接地環21b容易被渗透曰腐 8 18482 1271874 面必須先形 強化形成於 202内的接 ，該開口 202 造成腐i虫的 保護接地環 增加製造成 蝕。因此’於該開口 202内之接地環W的表 成一用以加強的LPI層22作為蝕刻阻層，藉以 開口 202内之阻層23㈣構強度，以防曰止；口 地環21b受腐蝕。 由於以_製㈣核^板2G形成線路時: =側壁、上的接地環21b容易因姓刻液渗透而 象，故必須先在開口 2〇2内形成LPI層22以 =b’如此即增加製程，使得製造步驟增加，而 〇 :二如何提出—種半導體封襄電路 之降低等缺失’實已成爲目前業界巫待解決 【發明内容】 ，提供之缺失，本發明之主要目的即在於 ’效果以防= 糊⑷⑽製法，得增加遮蔽 本發明之另—目的即在於提供— 板之結構及其製法 牛―版封衣％路 本仔間化裂程及降低製造成本。 路板之輪=目：：在於提供-種半導體封裝電 經濟效益之半導ί二1製程良率'具生产主性及符合 、心千蛉肢封裝電路板結構。 為達上述及其他目姑 製法，係包括:提供—核"月之半導體封裝電路板之 核心板，具有第-表面及第二表面； 18482 9 1271874 =核心,之預定形成開口的部位周圍形成複數條貫穿第 :::第二表面之溝槽⑻叫’且相鄰兩溝槽之間的鄰接 I:—、’、而形成—連接部，而在該預定形成開口的部位内 =待移除板；於該核心板的表面及溝槽内的側壁面形 土屬層，该金屬層進行圖案化製矛呈以 之圖案化金屬層；以及於該溝槽之間的連接部進=路 =板―，並使該開…落處二 ^圖案化金屬層具有接地環及複數個電 有圖案化金屬層之電路板上形成， 二，=化製程以露出接地環及複數個電性連接塾 二金屬保護Γ該接地環及電性連接墊與焊㈣表面形成 成之又之溝槽係以成型機台之銑刀或機械鑽孔形 壓形成二I部之鑽孔製程係可為機械鑽孔、銑刀或沖 路板:法乂發明復提供-種半導體封裝電 '、匕括.核心板’該核心板具第—表 一表面及至少一 f ^ 乐 化金屬層，切：二：一 Γ第二表面之開D;以及圖案 、， /成於该核心板之表面及開口内的钿辟 亚使：開口之角落處無該圖案化金屬層。、、土 ， 前述，構中之圖案化金屬層復包括有形成 圍之接地％及複數個電性連 」° 具有-絕緣俘，昆 安蛩方…亥θ案化金屬層表面 、呆❿且該絕緣保護層具有開口以露出該圖 18482 10 1271874 - 案化金屬層之接地環及複數個電性連接墊 及電性連接墊表$ 、’方；忒接地環 ^ 上表面形成一金屬保護層。 =封裝電路板結構復可於該核心、板 -散熱件以封住該核心板開口之一端：面接置 口中的散熱件上桩罢 *、、， …亥核心板之開 設於該開口中':晶片’以使該半導體晶片容 令該半導r曰片葬1 括有複數個電性連接墊， 地環焊線與該核心板之電性連接墊及該接 膠體。以及於今访、、此斤旻义牛¥版日日片及焊線之封裝 ,i4 、。板弟一表面植設多數焊球，以伊哕丰 ^封4核心板與外部電子裝置電性連接。 、。亥+ 相較於習知技術，本發明之半導體封裝 主要係於雷跋:te制^$路板、、，吉構， 後，再於預借带士 凡成防#層之 m 的位置先形成構成開口的溝样，而 /曰内形成用以遮蔽電磁波及雜訊干擾的金屬0 可=除溝槽之間的連接部而移除待移除板，故^制即 以降低製造成本。 日彳化衣程 '從而可簡化整體製程、降低生產成本、提 二:ϋ!支術中所引起的製程繁瑣、製程良率：低、穿 私成本增加等缺失。 -衣 【實施方式】 、以下藉由特定的具體實施例說明本發明之實施 t:熟悉此技藝之人士可由本說明書所揭示之：： 具點及功效。本發明亦可藉由i他 的/、肢貫施例加以施行或應用，本 ° 日〒的各項細節亦 18482 11 1271874 可基於不同的觀點與應用，在不悖籬太^RB + 1 各種修飾與變更。尤有甚去=子^本發明之精神下進行 可声、》、$ ffi b有甚者，本發明之封裝電路板結構， 了廣泛運用於一般半導㈣曰 曰刑+、u 牛曰曰片之封農’目式及說明雖以底 球狀間陣列（Cavity-downballgridarray，cDBGA) 制本封裝電路板閣明其結構情形，惟此應非用以限 制本發明運用之範圍，先予敘明。 之本Γ二閱$ 3A圖及第3G圖所示’係、為詳細説明本發明 =肢封裝電路板之結構及其製法較佳實施態樣。 30, f:閱第Μ目，提供一表面具有銅層31之核心板 :核心板30具有第-表面30a及第二表面3〇b，而 ^〆板3〇係為一銅羯基板、已完成線路之雙層或多層電 路板。 。月 > 閱第3B及3C圖，於該核心板3〇之預定形成開 口的部位周圍形成複數條貫穿第一表面30a及第二表面 3士〇b之溝槽32(sl〇t)，且相鄰兩溝槽32之間的鄰接處益接 修續而形成-連接部32a，而在該預定開口内構成一待移除 而。玄溝t 32係可藉由成型機台之銑刀或機械鑽孔 其中之一者形成之。 明麥閱第3D圖’接著該核心板30之銅層31表面及 其溝槽32内的侧壁表面形成—導電層（圖式中未表示），然 後以电解包鍍（E]extrolytic piating)、無電解電鍍 (Electioless Plating)或物理氣相沉積（physical Va㈧γPlease refer to 帛 and (7). In order to solve the above problems, the industry has developed a type of bottom-mounted crystal ball grid array type (Cavi (4) · _ gHdarray, CDBGA) package structure, which knows that the package structure contains -(10)H) a heat sink 12, at least one semiconductor wafer 13, a plurality of bonding wires 14, an encapsulant 15 and a plurality of solder balls 16. The circuit board 10 has a front surface 10a and a back surface, and (4) at least one opening 丨 (Η, wherein a grounding ring is formed in a surrounding area of the side wall of the corresponding wall ι ι on the circuit board 1 〇 u, and a side wall HO (Sidewall) is formed with a grounding ring; a metal protective layer 112' and the metal protective layer 112 is a nickel/gold layer, 18482 6 1271874 by plating The metal protection layer 112, the lightning failure extension 1Π - * small θ knife grounding area, sub-protection of the surface of the two-way board electrical connection pad 17 and grounding ifll ground 2: not oxidized and damaged, thereby It can be good to prevent it from being exposed to the outer layer of material, such as a high thermal conductive material such as copper, and the second adhesive layer 12a is attached to the back of the circuit board 10, the circuit The plate 10 forms an inward surface 13b (Inactive surface) of the opening 101, and has an electrode pad on the ugly side, the active surface 13a. In the assembly process, the opening 101 of the semiconductor wafer is And the straight non-main joint, the slab 1 〇 elbow, the non-active surface 13b stick To the heat sink 12; the wire break process 'by means of the wire 14 to semi-conducting; = 塾 (3) is electrically connected to the surface of the circuit board 1 electrically connected to the ground ring 11; then, the process of encapsulation, Thereby, the coating body 15 is formed to completely cover the semiconductor wafer 13 and the bonding wire 14; thereafter, the bonding-balling process is performed, whereby a plurality of solder balls 16 are implanted on the front surface of the circuit board 1 . That is, the bottom hole crystal ball (CDBGA) package structure is completed. Λ ^ (3) The county is rich, and the manufacturing method of the circuit board is as shown in the figure 2A to 2H. Please refer to the first, first A core plate 20 having a copper layer 2〇1 is provided, and the core plate 20 has an opening 2〇2. Please refer to the surface of the core plate 2 and its opening 2〇2. A metal layer 21. 18482 7 1271874 Referring to FIG. 2C, an Lpi layer 22 (Liqmd Photo Image ph〇to resister) is formed on the surface of the metal layer 21, and then the LPI layer 22 is patterned. So that an LP] [layer 22 is formed on the surface of the metal layer 21 in the opening 2〇2, and is covered by the Lpi layer 22 On the surface of the metal layer 21 in the opening 2〇2, a 2D pattern is formed, and a resist layer 23 is formed on the surface of the metal layer 21 and the LPI layer 22, and the resist layer 23 is formed on the surface of the layer. Φ Please refer to FIG. 2E, the resist layer 23 is patterned to form an opening on the resist layer 23 for revealing a portion of the metal layer 21. • Refer to FIG. 2F, and then remove by etching. The metal layer 21 covered by the resist layer 23 forms a patterned metal layer 21, that is, a line and an electrical connection pad 21a are formed on the surface of the core board, and a ground ring 21 is formed on the side i in the opening 2Q2. b. ^ Please refer to FIG. 2G, and then remove the resist layer 23 and the LPI layer 22, and then form a series of insulation protection such as a 10 hole on the circuit board 1 having the patterned metal layer 210. The layer 24 has an opening 240 formed thereon to expose the patterned metal pad 21a and the ground ring 21b. The buckwheat is read in FIG. 2H, and finally the surface of the electrical connection ... and the grounding ring 21b is formed by electroplating - a metal protective layer such as a recording/gold layer... the core plate is relative to the core board 20 2〇的开口2=face f shell is larger'. When the metal layer 21 is patterned to become a patterned metal layer, the metal layer covered by the non-resistive layer 23 is directly removed. The grounding ring 21b of the side wall surface of the opening 202 is easily penetrated by the rot. 8 18482 1271874. The surface must be shaped and strengthened in the connection 202. The opening 202 causes the protective earthing ring of the rot to increase the manufacturing etch. Therefore, the grounding ring W in the opening 202 is formed as an etch resist layer for reinforcing the LPI layer 22, whereby the resist layer 23 (4) in the opening 202 has a strength to prevent the stagnation; the ground ring 21b is corroded. Since the line is formed by the _ system (4) core board 2G: = the side wall and the ground ring 21b on the upper side are easily infiltrated by the surname engraving, so the LPI layer 22 must be formed in the opening 2〇2 first to =b' The process makes the manufacturing steps increase, and the second: how to propose - the reduction of the semiconductor sealing circuit and other defects have become the current industry to be solved [invention], the lack of provision, the main purpose of the present invention is to 'effect In order to prevent the addition of the paste (4) (10) method, the additional purpose of the present invention is to provide the structure of the board and the method for producing the method, and to reduce the manufacturing cost. The wheel of the road plate = the purpose of:: in the provision of a semiconductor package power economical semi-conductor ί 2 1 process yield 'have production and compliance, heart and limbs package circuit board structure. In order to achieve the above and other methods, the core board of the semiconductor package circuit board of the "nuclear" is provided with a first surface and a second surface; 18482 9 1271874 = core, which is formed around the portion where the opening is to be formed. The plurality of grooves (8) penetrating the second surface of the ::: second surface are called 'and the adjacent I: -, ' between the adjacent two grooves, forming a connection portion, and in the portion where the opening is intended to be formed = to be moved a surface layer on the surface of the core plate and a sidewall in the trench, the metal layer is patterned to form a metal layer; and a connection portion between the trenches is formed = board - and make the opening ... the patterned metal layer has a grounding ring and a plurality of electrically patterned circuit layers formed on the circuit board, the second process = to expose the ground ring and a plurality of electrical connections塾二金属保护Γ The grounding ring and the electrical connection pad and the surface of the welding (4) are formed into a groove which is formed by a milling cutter of a forming machine or a mechanical drilling to form a two-part drilling process system. Drilling, milling or swash plate: "Electrical", including: core board 'the core board has a surface - a surface and at least one f ^ Lehua metal layer, cut: two: a second surface of the opening D; and the pattern, / / in the The surface of the core plate and the enamel in the opening: there is no patterned metal layer at the corner of the opening. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The insulating protective layer has an opening to expose the grounding ring of the 18122 10 1271874 - the metal layer of the case and the plurality of electrical connection pads and the electrical connection pad table $, 'square; the top surface of the grounding ring ^ forms a metal protective layer . = The package circuit board structure is replenished in the core, the board-heat sink to seal one end of the core board opening: the heat sink in the surface connection port is piled up, and the core board is opened in the opening': The wafer is configured such that the semiconductor wafer accommodates the semiconductor wafer 1 and includes a plurality of electrical connection pads, an electrical connection pad of the ground wire bonding wire and the core plate, and the glue body. As well as the current visit, the package of the Japanese version of the Japanese version of the Japanese version of the Japanese and the wire, i4,. On the surface of the board, most of the solder balls are implanted, and the four core boards are electrically connected to the external electronic devices. ,. Compared with the prior art, the semiconductor package of the present invention is mainly used in the Thunder: te system, the road board, and the ji structure, and then the position of the m layer of the predecessor Forming a groove pattern constituting the opening, and forming a metal 0 for shielding electromagnetic waves and noise interference in the inside of the crucible can remove the board to be removed except for the connection portion between the grooves, so that the manufacturing cost can be reduced. In the future, it can simplify the overall process, reduce the production cost, and raise the second: ϋ! The process caused by the branch is cumbersome, the process yield is low, and the cost of wearing is increased. - EMBODIMENT [Embodiment] The following describes the implementation of the present invention by way of specific embodiments: t persons skilled in the art can be disclosed by the present specification:: The invention can also be implemented or applied by using his/her limbs, and the details of the sundial are also 18482 11 1271874 can be based on different viewpoints and applications, and the fences are too RB + 1 various Modifications and changes. In particular, it is possible to perform vocal, ", and $ffi b under the spirit of the present invention. The packaged circuit board structure of the present invention is widely used for general semi-conductance (4) 曰曰 + +, u 曰曰The film's closure of the farm's eyesight and description, although the bottom of the spherical array (Cavity-downballgridarray, cDBGA) made this package circuit board to illustrate its structure, but this should not be used to limit the scope of application of the invention, first Bright. The second embodiment of the present invention is a detailed description of the structure of the present invention, the structure of the limb-packaged circuit board, and a preferred embodiment thereof. 30, f: reading the first item, providing a core plate having a copper layer 31 on the surface: the core plate 30 has a first surface 30a and a second surface 3〇b, and the 〆 plate 3 is a copper enamel substrate, Complete the double or multi-layer circuit board of the line. . </ RTI> 3D and 3C, a plurality of grooves 32 (sl〇t) penetrating through the first surface 30a and the second surface 3, and a groove 32 (sl〇t) penetrating through the first surface 30a and the second surface 3 are formed around the portion of the core plate 3 that is intended to form an opening, and The abutment between the adjacent two grooves 32 is modified to form a connecting portion 32a, and a predetermined opening is formed in the predetermined opening. The Xuangou t 32 system can be formed by one of the milling cutters or mechanical drilling of the forming machine. 3D of the Ming Mai's view, then the surface of the copper layer 31 of the core plate 30 and the surface of the sidewalls in the groove 32 are formed - a conductive layer (not shown in the drawing), and then plated by electrolytic plating (E) extrolytic piating) , electroless plating (Electioless Plating) or physical vapor deposition (physical Va (eight) γ
Depos山on)等方式於該核心板3〇之銅層31表面及該溝槽 32内的侧壁面形成一係如銅之金屬層。 18482 12 1271874 請娜3E圖，於該核心板3〇之第—表面3〇“則形 烕一阻層3 4。 請參閱» 3F目，接著該阻層34進行圖案化製程，以 ^亥^層34j"形成用以顯露出部分金屬層33之開孔340。 月i閱第3G圖，之後以姓刻移除未被阻層34所耨罢 =^33及銅層31’即可在核心板2〇的表面形成1: 圖木化金屬層330, *該圖案化金屬層33〇係包含有 接地環33a、電性連接墊33b、焊球塾…及線路现。 打閱第3H圖，然後移除該阻層34,並於該已形成 —圖案化金屬層33〇之核心板3〇的第—表面1上形成 3如防焊層⑽如則叫之絕緣保護層35，再經圖案化 二了h亥:屬護層35上形成有開孔35〇用以顯露出接地 展33a及電性連接墊33b與焊球墊33c。 請麥閱第31圖，最後於該圖案化金 :或如接地環33a、電性連接墊现及焊球墊33e^= :如：鑛形成-金屬保護層36,而該金屬保護層％係為 孟 巴、銀、錫、鎳/姜巴、鉻7鈦、鎳/金、把/金或鎳/ 鈀/金等金屬或多層金屬。 ^ 請參閱第3J圖，該溝槽32之間的連接部❿以係如 銑刀、機械鑽孔或沖壓進行鑽孔製程去除該待移除板 32b，^以在該核心板3〇上形成—開口，，並使該開口地 之角洛處無該圖案化金屬層33〇及金屬保護層％。 由上述之製造方法，本發明復提供— 路板之結構，係包括：核心板30,該核^電 18482 13 1271874 面30a、第二表面30b及至少一貫穿該第一及第二表面 3〇a、30b之開口 30c;圖案化金屬層33〇,係形成於該核 心板川之表面及開口 30c内的侧壁面；以及金屬保護層 36，係形成於圖案化金屬層330之部分區域，其中該開口 30c之角洛處無该金屬層及金屬保護層36。 前述結構中之圖案化金屬層33〇之部分區域包括有米 .成於開口 30c内壁面的接地環33a及複數個電性連接墊 •鲁33b與焊球墊33c，於該形成有圖案化金屬層33〇之電路板 表面具有一絕緣保護層35，且該絕緣保護層％具有開孔 .350以露出該圖案化金屬層33〇之接地環33a及複數個電 .性連接墊33b與焊球墊33c，並於該接地環及電性連 接墊33b與干球墊33c表面形成—金屬保護層36。 ，、請參閱第4圖，係為應用本發明之封裝電路板結構所 製成之半導體封裝件，即例如為底穴置晶型球狀間陣列 仰職）半導體封裝件。該半導體㈣件主要係在核心板 • 30之底面上以一黏著層37接置一散熱件42,藉以封住該 開口 3〇c之-端。俾於該核心板3〇之開〇 *中之散熱件 42上以導熱膠41接置—半導體晶片43，並進行打線、封 勝及植球製程，以供該半導體晶片43藉由複數條焊線44 電性連接至該核心板30，並於該半導體晶片43及焊嗖料 形成用以包覆之封裝膠體45，以及於該核心板％之第一 表面30a植設複數焊球46，進而形成該半導體封裝件。 該半導體晶片43係具有一主動面…以及與該主動 面43a相對之非主動面们七，且該主動面43&上形成有多 18482 Ι27Ί874 * t，431。於本實施例中，該半導體晶片& 置於該散熱件42上’且容設於該核心板3 : 開口池中，俾使該半導體晶片43 = 過該散熱件42直接有 座生的…里可透 片43之使料命的制料界’^延長半導體晶 又:峨44係用以電性連接該半導體晶片 上的琶極墊431與該接地環33a，以及$妨4動 之第一表面30a的線路中#作 -杉〜板30 T 1/、1乍為電性連接 中該半導體晶片43藉由焊線 :二。 及今恳仅，既〇， 周圍之金屬層330 及孟屬保護層36以增加接地面積 4 3之電性功能。 、 升半‘體晶片 該封裝膠體45係心包覆 _ 環33a、該些焊線44。 卞等版日日片43、該接地 該焊球46係植置於該核心板3〇之 供容置有該半導體晶片43之 弟一表面30a，以 路板等外部電子裝置電性連接。肢封裝件與例如印刷電 因此，本發明之半導體封裝带 路板製程中，於該電路板預備形：板、-構，主要係於電 槽，而在溝槽内形成用以遮蔽電磁二：:立置先形成溝 護層後，即可鑽除溝槽之間的連邱=5fl干擾的金屬保 而可免除習知必須形成兩層阻：：移除該待移除板， 之缺失，故可簡化製程以降低^暴使得製程複雜度增加 -衣W成本。 再者，本發明之半導體封拿㊉ 、书板結構復可用以接置 15 18482 1271874 半導體晶片於其中，並進行打、 最終完成該半導蝴曰# $私# 、衣及植球等製程，以 設之導電元從而可藉由電路板表面植 裝置電性漣接：’ Π冑例如印刷電路板等外部電子 導體晶片運作：，可透過耦接於該電路板之散熱件將半 片十運作時產生的熱量直接有效的傳遞至外界。 效，而=施難為例㈣㈣本㈣之原理及其功 在不制:發明。任何熟習此項技藝之人士均可 改。因此t 神及崎下，對上述實施例進行修 圍所列此本㈣之權利保護範圍，應如後述之申請專利範 【圖式簡單説明】 知CDBGA封裝結構之剖面示意 知CDBGA封裝結構之製法剖面 第1 A及1 b圖係為習 圖及電路板上視圖； 第2A至2H圖係為習 示意圖； 弟3A至3J圖係為本發明之半導體封裝電路板之結 及其製法之剖面示意圖；以及 ° ...第4圖係為本發明之半導體封裝電路板之結構進行丰 寸體晶片封裝之剖面示意圖。 【主要元件符號說明】 1〇 電路板 l〇a 正面 10b 背面 101、202、230、240、30c、32、340、350 開口 11、2]上接地環 側壁 18482 Ι27Ί874 112 、 25 、 36金屬保護層 13、43 半導體晶片 13a、43a 主動面 14 > 44 焊線 16、46 焊球 20、30 核心板 22 LPI層 24、35 絕緣保護層 30b 第二表面 32b 待移除板 21、33 金屬層 33a 接地環 33d 線路層 41 導熱膠 12、42 散熱件 131 > 431 電極墊 13b 、 43b 非主動面 15、45 封裝膠體 17、21a、 33b 電性連接墊 201 ^ 31 銅層 23、34 阻層 30a 第一表面 32a 連接部 32 溝槽 330 、 210 圖案化金屬層 33c 焊球墊 37 黏著層 17 18482The surface of the copper layer 31 of the core plate 3 and the side wall surface of the trench 32 form a metal layer such as copper. 18482 12 1271874 Please take the picture of Na 3E, on the surface of the core board 3 - surface 3 〇 "The shape of a resist layer 3 4 . Please refer to » 3F mesh, then the resist layer 34 for the patterning process, ^ ^ ^ The layer 34j" is formed to expose the opening 340 of the portion of the metal layer 33. The moon is read in the 3G figure, and then the undestroyed layer 34 is removed by the last name, and the copper layer 31' can be removed at the core. The surface of the board 2 is formed: a metallization layer 330, * the patterned metal layer 33 includes a grounding ring 33a, an electrical connection pad 33b, a solder ball, and a line. Then removing the resist layer 34, and forming a 3 such as a solder resist layer (10), such as an insulating protective layer 35, on the first surface 1 of the core plate 3A of the formed-patterned metal layer 33〇, and then patterning The second layer is formed: an opening 35 is formed on the protective layer 35 for exposing the grounding exhibition 33a and the electrical connection pad 33b and the solder ball pad 33c. Please read the 31st picture, and finally the patterned gold: Or such as the grounding ring 33a, the electrical connection pad and the solder ball pad 33e^=: eg, the mineral formation-metal protective layer 36, and the metal protective layer % is Mengba, silver, tin, nickel/ginger, chrome 7 titanium Metal or multi-layer metal such as nickel/gold, handle/gold or nickel/palladium/gold. ^ Refer to Figure 3J. The joint between the grooves 32 is drilled by means of a milling cutter, mechanical drilling or stamping. The process removes the board 32b to be removed, so as to form an opening on the core board 3, and the corner of the opening ground is free of the patterned metal layer 33 and the metal protective layer %. The method of the present invention provides the structure of the road board, comprising: a core board 30, the core 18482 13 1271874 surface 30a, the second surface 30b and at least one of the first and second surfaces 3a, 30b The opening 30c; the patterned metal layer 33 is formed on the surface of the core plate and the side wall surface in the opening 30c; and the metal protection layer 36 is formed in a portion of the patterned metal layer 330, wherein the opening 30c The metal layer and the metal protective layer 36 are absent from the corner. The partial region of the patterned metal layer 33 in the foregoing structure includes a grounding ring 33a formed on the inner wall surface of the opening 30c and a plurality of electrical connecting pads. And a solder ball pad 33c, the circuit board on which the patterned metal layer 33 is formed The surface has an insulating protective layer 35, and the insulating protective layer % has an opening .350 to expose the grounding ring 33a of the patterned metal layer 33 and a plurality of electrically connecting pads 33b and solder ball pads 33c. The grounding ring and the electrical connection pad 33b and the surface of the dry ball pad 33c form a metal protective layer 36. Please refer to FIG. 4, which is a semiconductor package made by applying the package circuit board structure of the present invention, that is, for example, The semiconductor (4) member is mainly disposed on the bottom surface of the core board 30, and an adhesive member 42 is attached to the bottom surface of the core board 30 to seal the opening 3〇c. - the end. The semiconductor wafer 43 is connected to the heat sink 42 in the opening plate of the core board 3, and is subjected to a wire bonding, a sealing process and a ball bonding process for the semiconductor wafer 43 to be soldered by a plurality of wires. The wire 44 is electrically connected to the core plate 30, and the encapsulant 45 for coating is formed on the semiconductor wafer 43 and the solder material, and a plurality of solder balls 46 are implanted on the first surface 30a of the core board. The semiconductor package is formed. The semiconductor wafer 43 has an active surface ... and an inactive surface opposite to the active surface 43a, and the active surface 43 & is formed with a plurality of 18482 Ι 27 Ί 874 * t, 431. In this embodiment, the semiconductor wafer & is disposed on the heat sink 42 and is accommodated in the core plate 3: an open cell, so that the semiconductor wafer 43 is directly seated by the heat sink 42... The material boundary of the permeable film 43 is to extend the semiconductor crystal: the 峨44 is used to electrically connect the gate pad 431 and the ground ring 33a on the semiconductor wafer, and the In the line of a surface 30a, the metal wafer 43 is electrically connected to the semiconductor wafer 43 by a bonding wire: two. And now, only the surrounding metal layer 330 and the Meng protection layer 36 are used to increase the electrical function of the ground contact area. , </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI>版 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日The limb package and the printed circuit, for example, are in the semiconductor package strip circuit board process of the present invention, in the circuit board preparation shape: the board, the structure, mainly in the electric trough, and formed in the trench to shield the electromagnetic two: After the vertical formation of the trench guard layer, the metal between the trenches can be drilled, and the metal barrier can be eliminated. It is necessary to form a two-layer resist: the removal of the board to be removed is missing. The process can be simplified to reduce the complexity of the process and increase the complexity of the process. Furthermore, the semiconductor package of the present invention can be used to connect a semiconductor wafer of 15 18482 1271874, and to perform the process of hitting and finally completing the semiconductor film, clothing, and ball. The conductive element can be electrically connected by the surface of the circuit board: ' 外部 an external electronic conductor chip such as a printed circuit board: the semiconductor device can be operated by the heat sink coupled to the circuit board The generated heat is directly and effectively delivered to the outside world. Effect, and = as a case of (4) (4) The principle of this (4) and its merits in the system: invention. Anyone who is familiar with this skill can change. Therefore, the above-mentioned embodiments are subject to the scope of protection of the above-mentioned (4), and should be applied as described later. [Simplified description of the drawings] Knowing the profile of the CDBGA package structure, the method of forming the CDBGA package structure Sections 1A and 1b of the section are schematic and circuit board views; 2A to 2H are schematic diagrams; and 3A to 3J are diagrams of the junction of the semiconductor package circuit board of the present invention and its manufacturing method And Fig. 4 is a schematic cross-sectional view showing the structure of the semiconductor package circuit board of the present invention. [Main component symbol description] 1〇PCB l〇a front 10b back 101, 202, 230, 240, 30c, 32, 340, 350 opening 11, 2] upper grounding ring side wall 18482 Ι27Ί874 112, 25, 36 metal protective layer 13, 43 semiconductor wafer 13a, 43a active surface 14 > 44 bonding wire 16, 46 solder ball 20, 30 core plate 22 LPI layer 24, 35 insulating protective layer 30b second surface 32b to be removed plate 21, 33 metal layer 33a Grounding ring 33d circuit layer 41 thermal paste 12, 42 heat sink 131 > 431 electrode pad 13b, 43b inactive surface 15, 45 encapsulant 17, 21a, 33b electrical connection pad 201 ^ 31 copper layer 23, 34 resist layer 30a First surface 32a connection portion 32 groove 330, 210 patterned metal layer 33c solder ball pad 37 adhesive layer 17 18482