1271129 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電路板，尤指一種具有改良焊盤可提 高信號完整性之電路板。 【先前技術】 - 隨著積體電路輸出開關速度提高以及電路板之佈線密度 增加，信號完整性已經成爲高速數位電路板設計必須關心問 題之一。元器件和電路板之參數、元器件在電路板上之佈局、 局速信號之佈線等因素，都會引起信號完整性問題，導致系 統工作不穩定，甚至完全不工作。如何在電路板之設計過程 中充分考慮到信號完整性之因素，並採取有效之控制措施， 已^成爲當今電路板設計業界中之熱門課題。由於電路板上 之^號密度提高，就需要更多信號傳輸層，而且藉由通孔實 現，間信號傳輸也是不可避免。通孔主要由兩個部分組成，、 中間之鑽孔（drill hole)，用於電路板層間之電性連接 通迢；二是鑽孔周圍之焊盤（pad)，該焊盤存在信號層上， 用於鑽孔和㈣層上走線之焊接。在高速、高魅之電曰路板 設計時，設計者總是希望通孔越小越好，這樣 空間，此外，通孔越小，其自身寄生電容 更適合用於高速電路。 ❿ 習知電路板之焊盤為環形，第一圖係習知技術 |直剖面示意圖，請參照第-圖，該電路板4〇包括複數 =及複數鑽孔42 ’該等鑽孔42用於貫穿該等平面層'^面 δ亥荨平面層41包括信號層、電源層和接 42穿過之平面層41爲一信號層時， 孔 環職43，該焊盤43用於該等鑽孔42和二 之焊接，當該等鑽孔42穿過之平面層41爲一 =，且該電源層或接地層不需與該等鑽孔;^ 專鑽孔42顺環繞-反焊盤44，該反焊盤 1271129 域於阻隔該等鑽孔42與該電源層或接地層之連接。 第二圖係習知技術之電路板平面示意圖，請參照第二 ^該電路板40之寄生電容主要由該信號層上之焊盤、43^ =接地層耦合產生，產生之寄生電容給電路之影響是延長了、 ί號上升時間，使信號産生失真，並降低電路速度。通^雷 容之計算公式爲 又 其一中’匕爲電路板介電常數，τ爲電路板板厚，D1爲焊 j ·徑’D2爲接地層反焊盤直徑，假設該電路板4〇厚丁爲 =l(lmil=〇.〇254mm)，該焊盤43直徑m爲2誠，該接地 =t反谭盤直徑〇2爲32mil，假設該電路板40介電常數f ^ el，藉由前述公式近似算出該焊盤43產生寄生電容值大 約疋(假設該焊盤43產生寄生電容值爲Ci)1271129 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit board, and more particularly to a circuit board having improved pads for improved signal integrity. [Prior Art] - As the output switching speed of the integrated circuit increases and the wiring density of the board increases, signal integrity has become one of the concerns of high-speed digital board design. Factors such as the parameters of components and boards, the layout of components on the board, and the wiring of the local speed signals can cause signal integrity problems, resulting in unstable system operation or even no operation at all. How to fully consider the signal integrity factors and take effective control measures in the design process of the circuit board has become a hot topic in the circuit board design industry today. Since the density of the ^ on the board is increased, more signal transmission layers are required, and the transmission of the signals is inevitable by the through holes. The through hole is mainly composed of two parts, a drill hole in the middle for electrical connection between the circuit board layers, and a pad around the hole, which is present on the signal layer. , used for drilling and welding of the wires on the (four) layer. In the design of high-speed, high-featured electric circuit boards, designers always hope that the smaller the through holes, the better the space, in addition, the smaller the through holes, their own parasitic capacitance is more suitable for high-speed circuits.焊盘 The pad of the conventional circuit board is a ring, the first figure is a conventional technology | straight cross-sectional view, please refer to the figure - the circuit board 4 〇 includes the plural = and the plurality of holes 42 'the holes 42 are used for Through the planes of the planes, the planar layer 41 including the signal layer, the power layer and the planar layer 41 through which the junction 42 passes is a signal layer, and the pad 43 is used for the holes. 42 and 2, when the hole 42 passes through the plane layer 41 is a =, and the power layer or the ground layer does not need to be drilled with the hole; ^ the dedicated hole 42 is surrounded by the anti-pad 44, The anti-pad 1271129 is adapted to block the connection of the drill holes 42 to the power or ground plane. The second figure is a schematic diagram of a circuit board of a conventional technology. Please refer to the second circuit. The parasitic capacitance of the circuit board 40 is mainly generated by the pad on the signal layer, 43^=ground layer coupling, and the parasitic capacitance generated is given to the circuit. The effect is extended, ί rising time, distortion of the signal, and reduced circuit speed. The calculation formula of the pass-through is another one, '匕 is the dielectric constant of the circuit board, τ is the board thickness, D1 is the solder j · the diameter 'D2 is the ground layer anti-pad diameter, assuming the board 4〇 Thickness is = l (lmil = 〇. 〇 254mm), the diameter of the pad 43 is 2, the ground = t anti-tan plate diameter 〇 2 is 32 mil, assuming that the circuit board 40 dielectric constant f ^ el, borrow The parasitic capacitance value generated by the pad 43 is approximately calculated by the foregoing formula (assuming that the pad 43 generates a parasitic capacitance value of Ci).
C1==1.41*4.4*0.020*0.050/(0.032-0.020) ^0.517 pF 這部分電容引起之信號上升時間變化量 t=22C(Z0/2)=2.2*0.517*(55/2)=31.28ps 其中Z0爲信號傳輸線之特性阻抗，從這肚數值可以砉 孔之寄生電容狀信號上升延緩不錄明顯，但 線中多次使用通孔進行層間切換，則在設計時需要 Ζΐί。由於現有通孔之焊盤設計爲環形，且考慮到寄生 曰’焊盤直徑不能太大，所以焊盤面積比較小，這樣 焊盤與電路板層間走線之焊接，會造成虛焊或 盤興走線之斷開。 因爲通孔由鑽孔和鑽孔周圍之焊盤組成，這兩部分之尺 了大，定了it孔之大小，如果通孔越小，卿盤直徑m減 ip姑、s接地層紐盤襄徑此 容之計算公式其寄生電容就越小，所以對信號之 =衫響摘小。目前通孔減小主要是藉城小鑽孔内徑實 ，但是鑽孔之尺寸不可能無限制減小，它受到鑽孔和電 1271129 鍍等工藝技術限制··鑽孔越小，# 容易偏離中心位置；且當鑽孔深度超越 通孔寄生電容減小之方法很難實現。日由減小鑽孔大小以使 【發明内容】 、 板，用於提高信號完ί/ί要提供一種具有改良桿盤之電路 該等鑽等;=包__ 層和接地層，該等鑽孔穿^ ΐ層、電源 形區域向外延伸有四個延長匕括―環形區域’在該環 號層走線之連接。 叙長。卩祕《與該電路板信 相較習知技術，該電路板 容值隨之減小，提高了錢完整積減小，產生寄生電 【實施方式】 參照第三圖，為本發明較佳 ;，該電路板50包括複數鑽孔51和:4之Λ?ϊ:面， 平面層52’該等平面層包括 ^、胃牙之複數 鑽孔51穿過之平面層52爲一信和接地層，該等 別環繞一焊盤53，該焊般53句括;該專鑽孔51周圍分 ==上向外延伸的四^長部環形 面層52爲一電源層或_接 〜荨鑽孔51牙過之平 該鑽孔51連接，則在該等a ’ 源層或接地層不需與 54 ’該反焊盤54爲—環科 周圍分別環繞有-反焊盤 與該電源層或接地層之連接，、发^$’ ^於阻隔該等鑽孔51 前環形區域55外圓邊界，盥框爲該烊盤53形狀改變 發明較佳實施方式之環形區域t相比，本 |圆罝倥減小，由於該環形 1271129 ==減小，在魏板工題造時不胃 ί 接Γ財發雜时财式德《 53環形 二二延伸四個延長部56，且該四個延長部56呈十字 該環形區域55上’該等延長部56用來在電 ϊίΐί 蟬倾祕板信號層祕之連接，避免 ，域焊盤與走線不容易斷開。上述本發明較佳實 =式之電路鋪由減小焊盤外圓直徑所減小之 所 延長部之面積，從而達到減小焊盤面積之目的。 由於本發明較佳實施方式之蟬盤面積減小，根據^ Τ平板面積越大，電容值越大；平板距離 了 寄生電容值Ϊ小面1貝減小’轉盤53與接地層之 習知電路板通孔焊盤爲規則環形，可 容值之大小，本發明所設計電路板之通 形，不能使用公式進行數值計算。將本發明“芯3 J =50之平面二維_輸人—仿真 2 述電路板40之焊盤43寄生電容時 數 佳實施方式電路板50之焊盤53寄生電容值爲月較C1==1.41*4.4*0.020*0.050/(0.032-0.020) ^0.517 pF The amount of change in signal rise time caused by this part of capacitance t=22C(Z0/2)=2.2*0.517*(55/2)=31.28ps Z0 is the characteristic impedance of the signal transmission line. From this belly value, the parasitic capacitance signal of the pupil can be delayed and not recorded. However, if the through hole is used for interlayer switching multiple times in the line, it is necessary to design Ζΐί. Since the pad of the existing via hole is designed to be annular, and the diameter of the pad is not too large, the pad area is relatively small, so that soldering between the pad and the circuit board layer may cause soldering or rejuvenation. The disconnection of the line. Because the through hole is composed of the hole around the hole and the hole, the size of the two parts is large, and the size of the it hole is fixed. If the through hole is smaller, the diameter of the disk is m minus ip, s ground layer plate 襄The calculation formula of the diameter of this volume has a smaller parasitic capacitance, so the signal = shirt is small. At present, the reduction of through-holes is mainly due to the small inner diameter of the city, but the size of the borehole cannot be reduced without limitation. It is limited by the technical requirements of drilling and electro-1271129 plating. · The smaller the borehole, # easy to deviate The center position; and the method of reducing the parasitic capacitance of the hole beyond the through hole is difficult to achieve. By reducing the size of the borehole so that the board is used to improve the signal integrity, it is necessary to provide a circuit with an improved pole plate, such as the drill, etc.; = package __ layer and ground layer, the drill The hole piercing layer and the power source region extend outwardly with four extensions including a "ring region" in the ring layer connection. Xu Chang. "There is a conventional technique compared with the circuit board, the capacitance of the circuit board is reduced, the total product is reduced, and parasitic electricity is generated. [Embodiment] Referring to the third figure, the present invention is preferred; The circuit board 50 includes a plurality of drill holes 51 and: 4, a surface layer 52', and the planar layer 52 includes a planar layer 52 through which the plurality of drill holes 51 pass through is a letter and ground layer. The pads are surrounded by a pad 53 which is included in the 53-segment; the surrounding hole 51 is divided into the upper and lower outwardly extending four-length annular surface layer 52 as a power layer or _connected to the boring hole 51. If the hole is connected to the hole 51, then the a 'source layer or the ground layer does not need to be adjacent to 54' the anti-pad 54 - the ring is surrounded by the - anti-pad and the power layer or the ground layer The connection, the hair is made to block the outer boundary of the front annular region 55 of the bore 51, and the frame is such that the shape of the disk 53 is changed compared to the annular region t of the preferred embodiment of the invention. Decrease, because the ring 1271129 == reduction, when the Weiban problem is created, it is not stomach ί Γ Γ 发 发 财 财 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 And the four extensions 56 are cross-shaped on the annular area 55. The extensions 56 are used to connect the signal layer of the board to avoid the domain pads and the traces from being easily disconnected. The above preferred circuit of the present invention has the purpose of reducing the pad area by reducing the area of the extension portion which is reduced in the diameter of the outer circumference of the pad. Since the area of the disk is reduced according to the preferred embodiment of the present invention, the larger the area of the plate is, the larger the capacitance value is; the distance from the plate to the parasitic capacitance value is smaller than that of the small surface, and the conventional circuit of the turntable 53 and the ground layer is reduced. The through-hole pad of the board has a regular ring shape and can be of a value. The shape of the circuit board designed by the present invention cannot be numerically calculated using a formula. The present invention "core 3 J = 50 plane two-dimensional _ input - simulation 2 circuit board 40 pad 43 parasitic capacitance time better implementation circuit board 50 pad 53 parasitic capacitance value is monthly comparison
c2 ~0.288pF 由測試結果可以看出，本發明所設計具有改 路板50之寄生電容值比f知電路板4() 、 g可使信號上升時間減少，減少信號失真，完 ίίϊίϋΐ二叙紐修飾或匕， 9 1271129 【圖式簡單說明】 第一圖係習知技術之電路板豎直剖面示意圖。 第二圖係習知技術之電路板平面示意圖。 第三圖係本發明較佳實施方式之電路板平面示意圖。 【主要元件符號說明】 電路板 50 反焊盤 54 鑽孔 51 環形區域 55 平面層 52 延長部 56 焊盤 53C2 ~ 0.288pF It can be seen from the test results that the parasitic capacitance value of the modified circuit board 50 is designed to reduce the signal rise time and reduce the signal distortion. Modification or 匕, 9 1271129 [Simple description of the diagram] The first diagram is a schematic diagram of the vertical section of the circuit board of the prior art. The second figure is a schematic plan view of a circuit board of the prior art. The third figure is a schematic plan view of a circuit board according to a preferred embodiment of the present invention. [Main component symbol description] Board 50 Anti-pad 54 Drill hole 51 Ring area 55 Planar layer 52 Extension 56 Pad 53