CN215499727U - Circuit board - Google Patents
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- CN215499727U CN215499727U CN202121921547.7U CN202121921547U CN215499727U CN 215499727 U CN215499727 U CN 215499727U CN 202121921547 U CN202121921547 U CN 202121921547U CN 215499727 U CN215499727 U CN 215499727U
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Abstract
The embodiment of the utility model discloses a circuit board, which comprises: the circuit comprises a first circuit layer, a second circuit layer, a first bonding pad, at least one pair of differential via holes penetrating through the first circuit layer, the second circuit layer and the first bonding pad, a voltage signal transmission layer positioned between the first circuit layer and the second circuit layer, an anti-bonding pad area formed between the voltage signal transmission layer and the differential via holes, and differential wiring extending through the differential via holes; the differential routing comprises a first differential routing subsection, a second differential routing subsection and a third differential routing subsection, wherein the vertical projection of the first differential routing subsection on the plane of the circuit board is positioned in the region of the back welding disc, and the vertical projections of the second differential routing subsection and the third differential routing subsection on the plane of the circuit board are both positioned outside the region of the back welding disc; the width of the first differential routing subsection is smaller than that of the third differential routing subsection. By adjusting the width of the differential wiring, the signal loss of the differential wiring in the layer changing process is reduced, and the transmission performance of signals at the differential via is improved.
Description
Technical Field
The embodiment of the utility model relates to the technical field of circuit boards, in particular to a circuit board.
Background
With the development of the electronic industry, more and more electronic devices have been widely used. In the field of circuit board technology, the development of PCBs has grown day by day. With the continuous improvement of the signal transmission rate, the wiring density of the server circuit board is higher and higher, and the requirement on signal loss is higher and higher. At present, high-speed signal lines in a server circuit board are generally wired in a differential wiring mode. The differential transmission is a signal transmission technology, and is different from the traditional method of one signal wire and one ground wire, the differential transmission transmits signals on the two wires, the amplitudes of the two signals are the same, the phases of the two signals are opposite, and a signal receiving end compares the voltage difference values on the two cables to judge the logic state sent by a sending end. Generally, on a circuit board, the differential traces must be two cables that are equal in length, equal in width, and in close proximity. However, because the circuit board has high trace density, the differential traces often need to be punched to replace the layer traces. Therefore, how to avoid the problem of impedance discontinuity caused by layer changing and routing of the differential transmission cable, improve the impedance matching rate of the whole differential routing line, and reduce the differential signal loss is a technical problem faced by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model aims to provide a circuit board to improve the signal transmission effect of differential routing and reduce the insertion loss of signals at differential vias.
In order to achieve the above object, an embodiment of the present invention provides a circuit board, including: the circuit comprises a first circuit layer, a second circuit layer, a first bonding pad and at least one pair of differential via holes penetrating through the first circuit layer, the second circuit layer and the first bonding pad, wherein the first bonding pad is positioned on one side of the first circuit layer, which is far away from the second circuit layer;
the circuit board further comprises a voltage signal transmission layer positioned between the first circuit layer and the second circuit layer, the voltage signal transmission layer surrounds the differential via hole in a vertical projection of a plane where the circuit board is positioned, and an anti-pad area is formed between the voltage signal transmission layer and the differential via hole;
the circuit board further comprises a differential trace extending through the differential via;
the differential routing comprises a first differential routing subsection, a second differential routing subsection and a third differential routing subsection, the second differential routing subsection is respectively connected with the first differential routing subsection and the second differential routing subsection, the vertical projection of the first differential routing subsection on the plane of the circuit board is positioned in the region of the reverse welding disc, and the vertical projections of the second differential routing subsection and the third differential routing subsection on the plane of the circuit board are both positioned outside the region of the reverse welding disc;
the width of the first differential routing subsection is smaller than the width of the third differential routing subsection.
Optionally, the width of the first differential routing subsection is equal to the width of the second differential routing subsection and is smaller than the width of the third differential routing subsection.
Optionally, the extending length of the second differential routing subsection is L1, where L1 is less than 4 mils and less than 6 mils.
Optionally, the circuit board further includes a second pad and at least one reflow hole penetrating through the first circuit layer, the second circuit layer and the second pad;
the second bonding pad is positioned on one side of the first circuit layer far away from the second circuit layer.
Optionally, the first pad, the second pad and the anti-pad area are all circular.
Optionally, the minimum distance between the second pad and the first pad is L2, and L2 is greater than or equal to 5 mil.
Optionally, the differential via includes a first differential via and a second differential via, and the first pad includes a first sub-pad and a second sub-pad;
the first differential via hole penetrates through the first sub-pad, and the second differential via hole penetrates through the second sub-pad;
the anti-pad area comprises a first sub anti-pad area and a second sub anti-pad area, the first sub anti-pad area surrounds the first differential via hole, and the second sub anti-pad area surrounds the second differential via hole.
Optionally, the differential trace includes a first differential trace extending through the first differential via and a second differential trace extending through the second differential via; the first differential trace and the second differential trace each include the first differential trace subsection, the second differential trace subsection, and the third differential trace subsection;
the distance between the second differential routing subsection of the first differential routing and the second differential routing subsection of the second differential routing is S1, and the distance between the third differential routing subsection of the first differential routing and the third differential routing subsection of the second differential routing is S2;
wherein, S1 is S2.
Optionally, the first sub anti-pad region and the second sub anti-pad region are of an integrated structure.
Optionally, the anti-pad area comprises a rectangle or an ellipse.
An embodiment of the present invention provides a circuit board, including: the circuit comprises a first circuit layer, a second circuit layer, a first bonding pad and at least one pair of differential via holes penetrating through the first circuit layer, the second circuit layer and the first bonding pad, wherein the first bonding pad is positioned on one side of the first circuit layer, which is far away from the second circuit layer; the circuit board further comprises a voltage signal transmission layer positioned between the first circuit layer and the second circuit layer, the voltage signal transmission layer surrounds the differential via holes in the vertical projection of the plane of the circuit board, and an anti-pad area is formed between the voltage signal transmission layer and the differential via holes; the anti-bonding pad area can effectively reduce the capacitance load, improve the impedance at the differential through hole and reduce the signal transmission delay. The circuit board also comprises a differential wire extending through the differential via hole; the differential routing comprises a first differential routing subsection, a second differential routing subsection and a third differential routing subsection, the second differential routing subsection is respectively connected with the first differential routing subsection and the second differential routing subsection, the vertical projection of the first differential routing subsection on the plane of the circuit board is positioned in the region of the back welding disc, and the vertical projection of the second differential routing subsection and the vertical projection of the third differential routing subsection on the plane of the circuit board are both positioned outside the region of the back welding disc; the width of the first differential routing subsection is smaller than that of the third differential routing subsection. By adjusting the width of the differential wires passing through the differential via holes, the signal loss of the differential wires in the layer changing process of the differential via holes is reduced, and the transmission performance of signals at the differential via holes is improved.
Drawings
Other features, objects and advantages of the utility model will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
fig. 1 is a schematic structural diagram of a circuit board according to an embodiment of the present invention;
fig. 2 is a schematic top view of a circuit board according to an embodiment of the present invention;
fig. 3 is a schematic top view of another circuit board according to an embodiment of the present invention;
fig. 4 is a schematic top view of another circuit board according to an embodiment of the present invention;
fig. 5 is a schematic top view of another circuit board according to an embodiment of the present invention;
FIG. 6 is a graph showing a comparison of insertion loss between a circuit board with an undercut reverse pad area and a circuit board without an undercut reverse pad area provided in the prior art;
FIG. 7 is a graph comparing insertion loss of a circuit board according to an embodiment of the present invention with that of a prior art circuit board;
fig. 8 is a graph comparing insertion loss of another circuit board provided by an embodiment of the present invention with that of a prior art circuit board.
Detailed Description
To further illustrate the technical means and effects of the embodiments of the present invention for achieving the predetermined purpose of the utility model, the technical solutions of the embodiments of the present invention are clearly and completely described below with reference to the accompanying drawings and the preferred embodiments.
Next, the present invention is described in detail with reference to the schematic drawings, and in the detailed description of the embodiments of the present invention, the schematic drawings showing the structure of the device are not partially enlarged in general scale for convenience of description, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and height should be included in the actual fabrication.
Fig. 1 is a schematic structural diagram of a circuit board according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a circuit board according to an embodiment of the present invention, as shown in fig. 1 and fig. 2, a circuit board 100 includes: the circuit comprises a first circuit layer 101, a second circuit layer 102, a first bonding pad 103 and at least one pair of differential vias 104 penetrating through the first circuit layer 101, the second circuit layer 102 and the first bonding pad 103, wherein the first bonding pad 103 is positioned on one side of the first circuit layer 101, which is far away from the second circuit layer 102;
the circuit board 100 further comprises a voltage signaling layer 105 positioned between the first circuit layer 101 and the second circuit layer 102, wherein a vertical projection of the voltage signaling layer 105 on a plane where the circuit board 100 is positioned surrounds the differential via 104 and forms an anti-pad area 106 with the differential via 104;
the differential trace 107 includes a first differential trace subsection 1071, a second differential trace subsection 1072, and a third differential trace subsection 1073, the second differential trace subsection 1072 connects the first differential trace subsection 1071 and the second differential trace subsection 1072, respectively, the vertical projection of the first differential trace subsection 1071 on the plane of the circuit board 100 is located within the anti-pad area 106, and the vertical projection of the second differential trace subsection 1072 and the third differential trace subsection 1073 on the plane of the circuit board 100 is both located outside the anti-pad area 106;
the first differential trace branch 1071 has a width less than the width of the third differential trace branch 1073.
The circuit board 100 is formed by a multilayer structure, the multilayer structure can be provided with a circuit to realize connection, and the circuit board 100 can be a PCB, an FPC or a rigid-flex board. The circuit board 100 may include a first circuit layer 101, a second circuit layer 102, a first pad 103, and a differential via 104 penetrating through the first circuit layer 101, the second circuit layer 102, and the first pad 103, because the differential traces 107 are arranged in pairs and respectively carry differential signals with opposite polarities, the exemplary illustration in fig. 2 shows a pair of differential vias 104 for extending a pair of differential traces 107, the first pad 103 and the anti-pad area 106 are both circular, the second differential trace division 1072 is equal to the third differential trace division 1073 in width, and the first pad 103 is located on a side of the first circuit layer 101 away from the second circuit layer 102; the first pad 103 is a pad of the differential via 104, the size of the first pad 103 is larger than that of the differential via to ensure the adhesion of the first pad 103 on the first circuit layer 101, and the pad is made of copper, and can be electrically connected to pins of other inserted components on the circuit board 100. The size and shape of the differential via 104 and the first pad 103 may be selected according to actual design requirements, and embodiments of the present invention are not particularly limited. The differential via hole 104 penetrates through the first circuit layer 101, the second circuit layer 102 and the first pad 103 of the circuit board 100, the differential trace 107 extends through the differential via hole 104, meanwhile, a copper layer is also arranged in the differential via hole 104, and the copper layer can be prepared by adopting processes such as electroplating or chemical plating and the like and is used for realizing normal signal transmission of the differential trace 107 in the differential via hole. However, the influence on high-speed signals, radio frequency signals, and the like is large near the differential via holes, and the transmission performance of the signals at the differential via holes 104 is reduced. The circuit board 100 further includes a voltage signal transmission layer 105 located between the first circuit layer 101 and the second circuit layer 102, the voltage signal transmission layer 105 may be a power layer or a ground layer, a vertical projection of the voltage signal transmission layer 105 on a plane where the circuit board 100 is located surrounds the differential via 104, and an anti-pad area 106 is formed between the voltage signal transmission layer 105 and the differential via 104, since the voltage signal transmission layer 105 around the differential via 104 increases parasitic capacitance of the differential via 104, so that impedance of the differential trace 107 is significantly reduced when passing through the differential via 104, in order to ensure continuity of signal transmission in the differential trace 107 at the differential via 104, the voltage signal transmission layer 105 corresponding to the vertical projection of the differential via 104 and the first pad 103 on the circuit board 100 is hollowed out to avoid copper layers or vias of ground, power and signals, so that the anti-pad area 106 is formed between the voltage signal transmission layer 105 and the differential via 104, the area of the anti-pad region 106 is larger than the areas of the differential via 104 and the first pad 103, so as to ensure that the register capacitance of the differential via 104 to ground is minimized, thereby improving the transmission performance of the differential trace 107 at the differential via. The anti-pad area 106 may have a geometric shape such as a circle, an ellipse, a rectangle, a diamond, etc., and the size and shape of the anti-pad area 106 may be selected according to actual design requirements, which is not specifically limited in the embodiments of the present invention.
Further, the differential trace 107 includes a first differential trace subsection 1071, a second differential trace subsection 1072, and a third differential trace subsection 1073, the second differential trace subsection 1072 connects the first differential trace subsection 1071 and the second differential trace subsection 1072, respectively, a vertical projection of the first differential trace subsection 1071 on the plane of the circuit board 100 is located within the anti-pad area 106, and vertical projections of the second differential trace subsection 1072 and the third differential trace subsection 1073 on the plane of the circuit board 100 are both located outside the anti-pad area 106; the width of the second differential trace subsection 1072 may be the same as the width of the first differential trace subsection 1071, or the width of the second differential trace subsection 1072 may be the same as the width of the third differential trace subsection 1073, and may be selected according to actual design requirements, fig. 2 illustratively showing the width of the second differential trace subsection 1072 may be the same as the width of the third differential trace subsection 1073, setting the width of the first differential trace subsection 1071 located at the anti-pad region 106 to be less than the width of the third differential trace subsection 1073 located outside the anti-pad region 106, increasing the impedance at the first differential trace subsection 1071 due to the reduction in the width of the first differential trace subsection 1071, and decreasing the impedance at the differential via 104 due to the presence of parasitic capacitance at the differential via 104, so that when the first differential subsection 1071 passes through the differential trace 104, capacitive loading of the impedance occurs at the differential via 104, and further, the transmission performance of signals in the differential wiring 107 is improved, and the loss of the signals in a high-frequency area is avoided.
According to the embodiment of the utility model, on the basis of the arrangement of the anti-pad area at the differential via hole, the width of the first differential wiring subsection of the differential wiring is adjusted, so that the insertion loss of the signal at the differential via hole is effectively reduced when the differential wiring passes through the differential via hole for layer change, and the transmission performance of the signal at the differential via hole is improved.
Fig. 3 is a schematic top view structure of another circuit board according to an embodiment of the utility model, as shown in fig. 3, optionally, the width of the first differential trace branch 1071 is equal to the width of the second differential trace branch 1072 and is smaller than the width of the third differential trace branch 1073.
The width of the first differential trace subsection 1071 and the width of the second differential trace subsection 1072 are both narrowed and are smaller than the width of the third differential trace subsection 1073. Preferably, the width of the first differential trace subsection 1071 and the width of the second differential trace subsection 1072 can both be adjusted to be 0.8 times the width of the third differential trace subsection 1073 so that the transmission performance of the signals in the differential trace 107 at the differential vias 104 is effectively improved.
With continued reference to FIG. 3, optionally, the second differential routing section 1072 extends for a length L1, where 4mil < L1 < 6 mil.
On the basis of narrowing the width of the second differential trace subsection 1072, the extending length L1 of the second differential trace subsection 1072 is controlled to be 4mil < L1 < 6mil, mil is a length unit, i.e. thousandths of an inch, equal to 0.0254 mm, and can be used for indicating the diameter of a wire or a thread or the thickness of a material sold by pages, etc. Preferably, when the extended length L1 of the second differential trace subsection 1072 is 5 mils, the transmission of signals in the differential trace 107 at the differential vias 104 is further improved.
Fig. 4 is a schematic top view of another circuit board according to an embodiment of the present invention, as shown in fig. 4, optionally, the circuit board 100 further includes a second pad 108 and at least one reflow hole 109 penetrating through the first circuit layer 101, the second circuit layer 102 and the second pad 108;
the second pads 108 are located on a side of the first circuit layer 101 away from the second circuit layer 102.
In order to reduce the area surrounded by the signal return path, return holes 109 may be disposed around the differential via hole 104, so as to provide the shortest signal return path for the signals in the differential traces 107, and reduce the electric field radiation of the signals. The return via 109 can be a return ground via to achieve the best impedance match while the electric field radiation of the differential trace 107 at the differential via 104 is much smaller. Meanwhile, the second pad 108 and the first pad 103 are both obtained by the same preparation process, and the reflow hole 109 and the differential via hole 104 are both obtained by the same preparation process, so that the manufacturing difficulty is reduced. The number of the backflow holes 109 may be selected according to actual design requirements, and embodiments of the present invention are not particularly limited.
With continued reference to fig. 2, 3, and 4, optionally, the first pad 103, the second pad 108, and the anti-pad region 106 are all circular.
The first pad 103, the second pad 108 and the anti-pad area 106 can be in different shapes such as rectangle and ellipse, but the shapes of the first pad 103, the second pad 108 and the anti-pad area 106 are all designed to be circular in consideration of preparation difficulty and manufacturing cost, and are in concentric circle shape with the differential via hole 104 as the center of circle, so that the manufacturing difficulty is effectively reduced, and meanwhile, the layer changing difficulty of the differential routing 107 is favorably reduced.
With continued reference to FIG. 4, optionally, the minimum distance between the second pad 108 and the first pad 103 is L2, L2 ≧ 5 mil.
In order to ensure that the reflow hole 109 effectively affects the signal transmission state of the differential trace 107 in the differential via hole 104, the distance between the second pad 108 of the reflow hole 109 and the first pad 103 of the differential via hole 104 is reasonably controlled, and then the distance between the reflow hole 109 and the differential via hole 104 is controlled. The minimum distance L2 between the second pad 108 and the first pad 103 is greater than or equal to 5mil, so that the reflow hole 109 provides a reasonable reflow path for signals in the differential trace 107, and the signal transmission effect is ensured.
With continued reference to fig. 4, optionally, the differential via 104 includes a first differential via 1041 and a second differential via 1042, and the first pad 103 includes a first sub-pad 1031 and a second sub-pad 1032;
the first differential via 1041 penetrates through the first sub-pad 1031, and the second differential via 1042 penetrates through the second sub-pad 1032;
the anti-pad area 106 includes a first sub anti-pad area 1061 and a second sub anti-pad area 1062, the first sub anti-pad area 1061 surrounding the first differential via 1041, and the second sub anti-pad area 1062 surrounding the second differential via 1042.
The circuit board 100 includes a first differential via 1041 and a second differential via 1042, as well as a first sub-pad 1031 and a first sub-antipad area 1061 corresponding to the first differential via 1041, and a second sub-pad 1032 and a second sub-antipad area 1062 corresponding to the second differential via 1042, where the first differential via 1041 and the second differential via 1042 are respectively used to carry two differential traces 107 of equal-valued and opposite-valued differential signals. The first sub-land areas 1061 and the second sub-land areas 1062 may be independent from each other or partially overlapped, and the presence of the first sub-land areas 1061 and the second sub-land areas 1062 ensures impedance continuity when signals in the differential traces 107 pass through the differential vias 104.
With continued reference to fig. 4, optionally, the differential trace 107 includes a first differential trace 1074 extending through a first differential via 1041 and a second differential trace 1075 extending through a second differential via 1042; the first differential trace 1074 and the second differential trace 1075 each include a first differential trace subsection 1071, a second differential trace subsection 1072, and a third differential trace subsection 1073;
the spacing between the second differential trace subsection 1072 of the first differential trace 1074 and the second differential trace subsection 1072 of the second differential trace 1075 is S1, and the spacing between the third differential trace subsection 1073 of the first differential trace 1074 and the third differential trace subsection 1072 of the second differential trace 1075 is S2;
wherein, S1 is S2.
The first differential trace 1074 and the second differential trace 1075 serve as a pair of differential traces and transmit signals with opposite polarities and equivalent values to the driving end, so that the anti-interference capability of signals in the differential trace 107 can be effectively improved. The spacing S1 between the second differential trace subsection 1072 of the first differential trace 1074 and the second differential trace subsection 1072 of the second differential trace 1075 is equal to the spacing S2 between the third differential trace subsection 1073 of the first differential trace 1074 and the third differential trace subsection 1073 of the second differential trace 1075, ensuring consistent impedance between the first differential trace 1074 and the second differential trace 1075 and reducing signal reflections. Meanwhile, the extension lengths of the first differential routing line 1074 and the second differential routing line 1075 can be controlled to be the same, so that the signals transmitted by the first differential routing line 1074 and the second differential routing line 1075 can be ensured to keep opposite polarities constantly, the common mode component is reduced, and the signal transmission effect is ensured.
Fig. 5 is a schematic top view of another circuit board according to an embodiment of the present invention, and as shown in fig. 5, optionally, the first sub-back pad region 1061 and the second sub-back pad region 1062 are an integrated structure.
The voltage signal layer residue in the hollowing process of the first sub-pad area 1061 and the second sub-back-pad area 1062 is avoided, the residual metal affects the signal transmission of the differential wiring 107, the first sub-back-pad area 1061 and the second sub-back-pad area 1062 can be simultaneously prepared, the first sub-back-pad area 1061 and the second sub-back-pad area 1062 form an integrated structure, the signal transmission in the differential wiring 107 is guaranteed, the insertion loss is reduced, and the manufacturing process difficulty is reduced.
Optionally, the anti-pad area 106 comprises a rectangular or oval shape.
The anti-pad area 106 may be rectangular or elliptical, and when the first sub-anti-pad area 1061 and the second sub-anti-pad area 1062 are of an integrated structure, the integrated structure may be rectangular, elliptical or racetrack-shaped, so as to avoid high frequency loss of the signal of the differential trace 107.
The embodiment of the utility model also uses a three-dimensional magnetic field simulation tool for modeling, and performs simulation analysis on the circuit board provided by the utility model, fig. 6 is a comparison graph of insertion loss of a circuit board with an undercut reverse pad region and a circuit board with an undercut reverse pad region, as shown in fig. 6, a curve 1 represents the circuit board with the undercut reverse pad region, a curve 2 represents the circuit board with the undercut reverse pad region, m3 and m4 represent the insertion loss of the circuit board of the embodiment of the utility model and the circuit board of the prior art at the same position, and it can be seen that the position 43.95GHz where the insertion loss is improved to the maximum in fig. 7 is from original-50.418 dB to-47.425 dB, and the improvement condition is 2.993 dB.
Based on the above fig. 6, fig. 7 is an insertion loss comparison diagram of a circuit board according to an embodiment of the present invention and a circuit board according to the prior art, which is exemplarily illustrated in fig. 4, an aperture of a differential via of the circuit board is 8 mils, an outer diameter of a first pad is 16 mils, outer diameters of a first sub anti-pad area and a second sub anti-pad area are both 26 mils, widths of the first differential routing subsection and the second differential routing subsection are 4 mils, a width of the third differential routing subsection is 5 mils, an extension length of the second differential routing subsection is 5 mils, and the circuit board according to the prior art is only subjected to anti-pad emptying, widths of the respective subsections of the differential routing of the circuit board are both 5 mils, and other values are the same as those of the circuit board provided in fig. 5. Where the abscissa represents frequency in GHz and the ordinate represents insertion loss in dB. Curve 1 in fig. 7 represents the circuit board provided by the embodiment of the present invention, curve 2 represents the circuit board in the prior art, and m1 and m2 represent the insertion loss of the circuit board of the embodiment of the present invention and the circuit board in the prior art at the same position, respectively, and it can be seen that the place where the insertion loss is improved most in fig. 7 is from-50.418 dB to-46.022 dB, and the improvement is 4.396 dB.
Fig. 8 is an insertion loss comparison diagram of another circuit board provided by the embodiment of the present invention and a circuit board in the prior art, and a simulation test result is compared, as shown in fig. 8, a curve 1 is a circuit board provided by the prior art and having no hollowed-out anti-pad region, a curve 2 is a circuit board provided by the prior art and having hollowed-out anti-pad region, and a curve 3 represents the circuit board provided by the present invention, it can be seen that there is a great improvement in a high frequency band, a low frequency band simulation curve has a good fit, and particularly after 20GHz, a simulation result has a great improvement, which shows that the width of a differential trace near a differential via of the differential trace is reasonably adjusted on the basis of the hollowed-out anti-pad region, so that the loss of the signal can be well reduced in the high frequency band, and the transmission performance of the signal at the differential via can be improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
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| CN202121921547.7U CN215499727U (en) | 2021-08-16 | 2021-08-16 | Circuit board |
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| CN202121921547.7U CN215499727U (en) | 2021-08-16 | 2021-08-16 | Circuit board |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117279197A (en) * | 2023-11-23 | 2023-12-22 | 零壹半导体技术(常州)有限公司 | High-frequency bandwidth differential wiring structure for chip test and test circuit board |
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2021
- 2021-08-16 CN CN202121921547.7U patent/CN215499727U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117279197A (en) * | 2023-11-23 | 2023-12-22 | 零壹半导体技术(常州)有限公司 | High-frequency bandwidth differential wiring structure for chip test and test circuit board |
| CN117279197B (en) * | 2023-11-23 | 2024-01-23 | 零壹半导体技术(常州)有限公司 | High-frequency bandwidth differential wiring structure for chip test and test circuit board |
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