TWI269456B - Wafer level package process and a wafer level package - Google Patents

Abstract

A wafer level package process and a wafer level package which use a dry film with a plurality of first openings and a printing screen board with a plurality of second openings to form buffer layers on a wafer are disclosed. The buffer layers formed have advantages of uniformity, regular shape and flat surface.

Description

1269456 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a wafer level packaging process and a structure thereof. [Prior Art] In today's highly information society, with the increasing use of electronic devices, 'integrated circuit packaging technology also needs to cooperate with the thin, thin, networked, multiplexed and more humanized drivers of electronic devices. The development of mechanical micro-fine and high-density. At present, in the circuit packaging technology, the Wafer Level Packaging process is the wafer-level packaging process. In the day-to-day member-level packaging process, the wafer is bonded to the board by bumps or solder balls. Therefore, if there is no structure for holding or absorbing stress between the bumps, the convex ship may be broken by the force or the touch, causing the package structure to fail. Therefore, the output structure of the bumps on the chip is combined with the stress of the board. A typical package _ _ patent, which is first on the wafer:

Tin ball) 3 hunting under the conductor layer 5 fish; brother U into a strengthening layer 9 pattern (9) trace electric like ± electrical connection 'and then in the bump four continue to see the second Figure 7 = 瞒 bump 3 is applied Stress.

Wafer-level package structure is made of crystal/u, Zhanfeng 5· patent, its t-layer π and qing- solder ball 19 = road layer 13, ball-bottom metal layer 15, and tree-month board bonding stress-welded balls 21 constitutes. In addition, the wafer Hi further includes a first solder ball 19 ^ - a resin layer 17 on both sides of the solder ball 21 to W 1269456 printed in the brother 3 picture Ding Du's 圏 、, Wendi test 427 〇 33 patent issued a new concept The dielectric dielectric bump 23 and the conductive pin 27 formed on the pad and connected to the dielectric bump 23 replace the external stress buffer layer and the external contact of the tin package structure. The dielectric bumps can be formed in a printed manner. ',,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Poor flatness is not good for subsequent process operations. " Therefore, in the field where the development has gradually matured, how to improve the L-step silking caused by the above-mentioned various methods, the present invention is solved by the present invention, and the invention is the main problem of the present invention. The purpose is to provide a wafer-level county process and its structure. The buffer layer formed by the process design can have the advantages of high uniformity, flat m-plane surface, etc. The i-layer can be directly placed on the pad. Ride the metal layer of the configuration and directly replace the ball or bump as a contact between the wafer and the circuit board or other carriers, further eliminating the trouble and trouble of making solder balls or bumps. Therefore, in order to achieve the above object, the thief thief-type _ loading process includes the following steps: a wafer having a plurality of flank on the surface of the wafer; forming a dry film having a plurality of first openings An active surface of the wafer, wherein the plurality of openings correspond to the pads; and a printing screen having a plurality of second openings is disposed on the film, wherein the second openings correspond to the first openings And forming a plurality of buffer layers on the fresh sputum through the first opening and the second opening. 6 1269456 Therefore, in order to achieve the above object, a wafer level package structure disclosed in the present invention has a plurality of pads on the active surface of the wafer, and a plurality of pads are disposed on the pads. The buffer layer has a first surface and a second surface. The plurality of metal layers are disposed on the retardation g and the first surface of the buffer layer is extended by the sidewall. Sexually connected to the solder fillets. The details and advantages of the present invention will be described in detail in the embodiments, which are sufficient to enable any skilled person to understand the technology of the present invention and implement it, and any advantages and purposes associated with the present invention. It can be easily understood from the contents disclosed in the specification, the scope of the patent application and the drawings. The above description of the present invention and the following description of the embodiments are used to avoid the principle of the invention and to provide further explanation of the scope of the present application. [Embodiment] The features and implementations of the present invention are described in detail with reference to the drawings. The following ®:^ is only a simple description, and the actual size is drawn, that is, the actual size and characteristics of each level in the circuit board structure are not reflected, which will be described first. The main concept of the handle is to use a process method to achieve a uniform, regular shape and a flat surface on the active surface of the wafer. According to the concept of the present invention, the buffer layer is formed on the pad. Since the buffer layer is additionally provided with a metal layer, the use thereof is to replace the conventional bump ball as a contact between the wafer and the carrier or the circuit board. . In another application, bumps or solder balls 7 1269456 are formed on the buffer layers - after: they can be used as stress buffers for bumps or solder balls. When the buffer layer is used as a contact, the use of the ruthless technology has the advantage of being easy to control the shape, and therefore the use of the present invention has a more detailed and subsequent process operation. When the money layer is used as the stress buffer layer of the transfer block, because of its manufacturing process (4), and the shape of the buffer layer can be kept consistent, the process yield can be improved and the production cost can be reduced. Please refer to FIG. 4 to FIG. 4 for a manufacturing flow chart of a preferred embodiment of the package structure according to the present invention. First, the 'provide-wafer 29' wafer 29 may be a completed integrated circuit, and may include an active surface formed with a plurality of bonding pads or redistribution pads 31 and Corresponding back. A protective layer (not shown) may be additionally disposed on the wafer 29 to expose the plurality of pads 31. Next, a dry film 33 is formed on the wafer 29. The dry film 33 has a plurality of 31 _ σ corresponding to the pad or the weight, and the first opening 35 corresponds to the bonding of the wafer to the carrier or the circuit board. position. At the opening, it may be a circular or square shape having a concave shape. The dry film 33 having a plurality of openings 35 can be obtained in a commercially available manner or can be fabricated by a semiconductor process, which can be a photoresist. A printing screen 37 is disposed on the dry film 33. The printing screen 37 has a plurality of openings corresponding to the first port 35, which is first named as a second opening in the present specification. The printing screen 37 may be a steel sheet, and the second opening 39 is different in size from the first opening 35, for example, the second opening 39 may be smaller in size than the first opening. I269456 Buffer ΐΐΓ33 and _ plate 37 thickness are determined according to the thickness of the weighed layer to be formed, and are not particularly limited. The first opening 35 and the second opening 39 are also buffered, and the plurality of buffers are combined with the buffers. The surface of the buffer is formed by the stress symmetry. , size], at the first opening 35, the buffer layer 41 of the Qing will be as the first

:= The body is trapezoidal. However, the size of the second opening π 39 is not set to be smaller than the opening 35, which may be larger than the first opening 35. After the opening is filled, the heating is further formed. At this time, since the buffer layer 41 is surrounded by the autumn (four) to ride the plate at 37 years old, the size of the layer 41 can be fixed and does not exceed the predetermined range. Facilitate subsequent process operations. The material of the buffer layer 41 should be stress buffered, such as a polymer, a gelatin, a rubber or a polyamidamine. The first opening 35 and/or the second opening 39 may be a square shape, or may be a circle. According to the above, the dry film hardening and the double layer holding of the printing screen are formed, and the formed layer is defined as (4). There is no problem of height unevenness, large diameter or irregular shape. In addition, since the upper and lower openings can be different, the shape of the buffer layer can be more appropriately designed according to its use. After the formation of the buffer layer, the printing web 37 and the dry film 33 may be removed one after the other to give a structure as shown in Fig. 4D. Next, a metal layer 43 may be formed on the buffer layer 41, and the side of the buffer layer 41 1269456 is connected to the pad 31. Thereby, the structure of the buffer layer 41 and the metal layer 43 thereon is prepared in a conventional bump configuration, so that it can be utilized as a bonding element between the wafer and the circuit board or with other carriers. The metal layer can be formed by exposing and exposing to expose a region where the metal layer is to be formed, and then adding a tantalum or a chemical gas to form a metal. Alternatively, the metal may be formed by plating or chemical deposition, and then exposed and developed to form a metal layer at a specific position.

The metal layer may be composed of copper, iron, inscription, gold or an alloy thereof. Here, the use of a buffer layer of a metal layer is similar to the use of a ship bump or a solder ball, which can be used not only as a bonding element between a wafer and a carrier or a circuit board, but also because of the age of the stress buffering property. , it can disperse the stress caused by the difference between the carrier and the board, so the connection with the carrier or the board will not be caused by the poor joint, separation = ' The reliability of the whole package can be increased (f), and the step of eliminating the bumps or solder balls can be omitted, and the overall packaging process can be simplified. On the other hand, please refer to Figure 5, on the structure of Figure 4E. Alternatively, it can be shaped as a buffer 4 with a metal layer that is electrically connected to the circuit board or to other carriers 11. It is similar to a conventional bump or solder ball, because it is buffered by stress. The material composition, which can disperse the stress caused by the difference in thermal expansion coefficient between the wafer and the bearing or the board, so the bump does not cause a bump-like fatigue. , can also slightly disperse the force of the extrusion of the bump, Avoiding bump rupture, the reliability of the overall package can be increased. ^ According to the above, the buffer layer structure of the present invention and the metal layer thereon can be used as a substitute for the conventional bump or solder ball. The utility model can thereby omit the process of the bump and the solder ball, and further, since the buffer layer can be used as the electrical connection and the buffering at the same time, the buffer layer can not be absorbed as usual, and the stress can be saved. The cost of the buffer layer should be made. On the other hand, if necessary, bumps or solder balls can be added to the structure, whereby it can be used as a stress buffer layer for bumps or solder balls, but has Compared with the simple process of the stress buffer layer around the conventional bump, the reliability of the process can be increased. The process of the process is formed by the double-layered holding structure of the paste film (photoresist) and the printed screen board of the present invention. The buffer layer has the advantages of stable shape, high uniformity, and uniform diameter, so that the process yield can be improved.

Although the difficulty of implementing the present invention is as described above, it is intended to be a subject of the present invention, without departing from the spirit and scope of the present invention: the change of the invention and the refinement of the invention. This is subject to the definition of the scope of the patent application attached to this description. ', [Simple description of the schema] 'The first picture is the package structure of the national patent No. 411536; the second picture is the package name of the national patent No. 523891. The third fiscal, the national 2nd (4) public disclosure case Package (10). The first to the _, the following is a manufacturing flow chart of the preferred embodiment 1269456, and FIG. 5 is a schematic structural view of another preferred embodiment of the package structure in accordance with the teachings of the present invention. . [Main component symbol description]

1 wafer 3 bump 5 conductor layer 7 wafer 塾 9 reinforcement layer 11 wafer 13 circuit layer 15 ball metal layer 17 resin layer 19 first fresh ball 21 second fresh ball 23 dielectric bump 25 fresh 塾 27 lead pin 29 Wafer 31 Pad 33 Dry film 35 First opening 12 1269456 37 Printing screen 39 Second opening 41 Buffer layer 43 Metal layer 45 Bump

Claims (1)

1269456 十 'Application Range·· h — a wafer level packaging process comprising the following steps: providing a wafer having an active surface having a plurality of pads; forming a dry film having a plurality of first openings In the active surface of the wafer, wherein the first openings correspond to the pads; and a printing screen having one of the plurality of openings is disposed on the dry film, wherein the second openings correspond to The first openings; and Through the first opening and the second opening of the Hai, the Yinqing has a plurality of buffer layers on the pads. 2. If the wafer-level packaging process described in the above paragraph is specified, the opening of the towel is narrower than the first opening. 3. The wafer level packaging process of claim 3, wherein the buffer layers are composed of a high molecular polymer. 4. The closed-level packaging process as described in the scope of the patent application is narrow and wide. ^二冲冲 5. As claimed in the patent application, the wafer level packaging process layer has a flat surface.二欸冲 6. ^ Please specializes in the wafer-level packaging process described in item 1, in which the steps of Yinqing into these buffer layers utilize a scraper. Subtraction 7. The wafer level as described in the patent application, the step of printing the buffer layer further includes the step of heating. 8. The packaging process as described in item 7 of the patent application, in which the heating is printed 14 1269456 Step Money Contains - Steps to remove the plate and the face. Whip the touch β, which removes the stamp to connect the solder _including the axis—the gold (four) layer to 10. a wafer level package structure, comprising: a round, having a plurality of pads active on the wafer a plurality of buffer layers disposed on the pads, the buffer layers having a first surface and a second surface, the second surface being in contact with the pads; and a plurality of metal layers disposed On the buffer layers, the cans of the 'axis buffer layer of the buffer layers are extended to have a miscellaneous connection. The wafer level package structure of claim 10, wherein the buffer layers are composed of a high molecular polymer. The wafer level package structure of claim 10, wherein the buffer layers are substantially a trapezoidal body. 3. The wafer level package structure of claim 10, wherein the buffer layers are narrow and wide. The wafer-level package structure described in claim 10, wherein the first surface is a flat surface. 15