1267935 16580twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路測試用結構及測試方 法’且特別是有關於一種用以檢查内連線之測試鍵(Test Key)，以及使用該測試鍵檢查内連線的方法。 【先前技術】 在半導體製程的多重内連線(Multi-level Interconnect) 製程中’為確認導電插塞(C〇nduCtive piUg)與上下層導線之 間的電性連接，通常會在晶圓的切割道上形成測試鍵。 請參照圖1，其繪示習知測試鍵及對應之内連線結構 的一例’其中内連線形成在基底1〇〇的元件區1〇2上，且 測試鍵106形成在切割道1〇4上，而由金屬層110b、插塞 150b及金屬層160b構成。金屬層ii〇b/160b係上下交替 排列，且各上(下)金屬層160b (110b)以二插塞150b分別連 接兩相鄰之下(上)金屬層110b (160b)，而成連續導電結構。 測試鍵106的金屬層110b係與内連線下金屬層i10a 同時形成，插塞150b與内連線的插塞150a同時形成，金 屬層160b則與内連線上金屬層i6〇a同時形成。在金屬層 110a/b形成後，通常先於基底1〇〇上形成氧化層12〇，再 於金屬層ll〇a/b之間隙填入旋塗玻璃130以平坦化，然後 於金屬層ll〇a/b與旋塗玻璃130上形成氧化層ho，再於 元件區102/切割道104的氧化層140中形成介層洞146a/ 146b，之後填入金屬以形成插塞150a/150b。又如圖2所 示，為便於填入金屬，在形成介層洞146a/b之前，通常會 5 1267935 16580twf.doc/g 以定義介層洞146a/b的光阻層142為罩幕，用緩衝氧化矽 蝕刻劑(BOE)進行濕蝕刻，以形成較寬的凹洞144a/b。 在以測試鍵106檢查内連線時，係測量測試鍵1〇6的 電遷移(Electromigration，EM)毀損時間。如内連線的插塞 150a有缺陷，則同時形成的插塞i5〇b也應有缺陷，此二 測試鍵106的EM毀損時間即會縮短，而可反映出該問題。 然而，金屬層110a的受損並無法藉由測試鍵1〇6正確 肇 地反映出來。例如，當金屬層ll〇a間隙過小或旋塗玻璃 130原料的溝填性較差，致使旋塗玻璃13〇產生裂縫133 (圖2)並延伸貫穿氧化層120與140時，在使用b〇e餘刻 、 形成凹洞144a的步驟中，B0E即會通過裂縫133而侵蝕 金屬層110a，令其阻值升南。此種侵餘現象即無法藉由習 知的測試鍵106偵測出來。 【發明内容】 本發明目的之一即是提供一種用以檢查内連線的測試 鍵’以解決前述内連線侵|虫現象無法偵測的問題。 本發明另一目的則是提供一種檢查内連線的方法，其 係使用本發明之測試鍵來進行。 本發明之測試鍵的結構包括一連續金屬線及其上的多 個導電插塞。每一插塞的一端與連續金屬線接觸，且其中 至少有一插塞的另一端不與任何導體連接。另外，連續金 屬線的兩端係連接至不同的電壓。 在本發明一較佳實施例中，連續金屬線的兩侧配置有 方疋塗玻璃（SOG)，而連續金屬線與旋塗玻璃之間較佳隔有 6 1267935 16580twf.d〇c/s 土 2弟電層。此連績金屬線及旋塗玻璃上可配置第一 =電層，而導電插塞即位在此第二介電層中。每—導二 基^頂部可比其它部分寬，而此頂部的下表面 二介電層進行選擇性等向性㈣而得者。 續弟 /、鱼^ ’上述測試鍵更可包括至少二假圖案，其分別位 、、，貝1屬線兩側，且各自與連續金屬線之間有一距 等於内連線結構中與連續金屬線同層之兩相鄰 j層的間距’而此假圖案之材質可與連續金屬線相同。 突夕^述職鍵難形成在晶圓的_道上，而導電插 塞之材質包括鋁。 令电播 第插塞及—上金屬層。其中，各導電插塞位於 U:屬線上，且每-導電插塞的下端與第- 屬線:ΐ'==。上金屬層位於第-至第三連續金 另外，第-、車二上居且與每一導電插塞的上端接觸。 弟—連、’至屬線的兩端係連接至不同的電壓。 層二明:==方法，係在形成内連線之金屬 連線之莖一杯〜 σ、上形成一連續金屬線；在形成内 插塞，而與連==於連續金屬線上形成多個第二 線兩端施力成1試鍵。之後’在連續金屬 該㈣電致遷移特性，藉此判斷 金屬線的電致遷移毁之電致祕特性包括連續 7 1267935 16580twf.doc/g 另外，在一較佳實施例中，於内連線之金屬層與前述 連續金屬線形成後，更有旋塗玻璃形成在金屬層之間與連 績金屬線的兩側；而在旋塗玻璃形成之前，較佳先在金屬 層與連續金屬線表面上形成第一介電層，以免其與旋塗玻 璃的原料接觸而受損。另外，在旋塗玻璃形成後，可在金 屬層、連續金屬線與旋塗玻璃上形成第二介電層，而前述 第一與第二插塞係形成在此第二介電層中。 此外，在上述較佳實施例中，於第二介電層中形成第 一第一插基的方法例如是先在第二介電層上形成圖案化罩 幕層，其具有多個介層洞圖案，再以該罩幕層為罩幕等向1267935 16580twf.doc/g IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a structure and test method for testing an integrated circuit', and particularly relates to a test button for inspecting an interconnect ( Test Key), and how to use the test button to check the interconnects. [Prior Art] In the multi-level Interconnect process of semiconductor manufacturing process, in order to confirm the electrical connection between the conductive plug (C〇nduCtive piUg) and the upper and lower wires, the wafer is usually cut. A test button is formed on the track. Please refer to FIG. 1 , which illustrates an example of a conventional test key and a corresponding interconnect structure. The interconnect is formed on the element region 1 〇 2 of the substrate 1 , and the test button 106 is formed on the scribe line 1 〇 4 is composed of a metal layer 110b, a plug 150b, and a metal layer 160b. The metal layer ii〇b/160b is alternately arranged up and down, and each of the upper (lower) metal layers 160b (110b) is connected to the two adjacent lower (upper) metal layers 110b (160b) by two plugs 150b to form a continuous conductive structure. The metal layer 110b of the test key 106 is formed simultaneously with the lower interconnect metal layer i10a, the plug 150b is formed simultaneously with the interconnect plug 150a, and the metal layer 160b is formed simultaneously with the interconnect metal layer i6〇a. After the metal layer 110a/b is formed, the oxide layer 12 is usually formed on the substrate 1 and then the spin-on glass 130 is filled in the gap between the metal layers 11a/b to be planarized, and then the metal layer is patterned. An oxide layer ho is formed on a/b and spin-on glass 130, and via holes 146a/146b are formed in oxide layer 140 of element region 102/cutting channel 104, and then metal is filled to form plugs 150a/150b. As shown in FIG. 2, in order to facilitate the filling of the metal, before forming the vias 146a/b, the photoresist layer 142 defining the vias 146a/b is usually used as a mask for 5 1267935 16580 twf.doc/g. The buffered cerium oxide etchant (BOE) is wet etched to form wider recesses 144a/b. When the interconnect is inspected with the test key 106, the electromigration (EM) damage time of the test key 1〇6 is measured. If the plug 150a of the interconnect is defective, the plug i5〇b formed at the same time should also be defective, and the EM damage time of the test button 106 is shortened, which can reflect the problem. However, the damage of the metal layer 110a cannot be correctly reflected by the test keys 1〇6. For example, when the gap of the metal layer 11a is too small or the groove filling property of the spin-on glass 130 material is poor, causing the spin-coated glass 13 to generate cracks 133 (Fig. 2) and extending through the oxide layers 120 and 140, use b〇e In the remaining step of forming the recess 144a, the B0E will erode the metal layer 110a through the crack 133, so that its resistance rises south. Such a phenomenon of intrusion cannot be detected by the conventional test button 106. SUMMARY OF THE INVENTION One object of the present invention is to provide a test button for inspecting an interconnect to solve the problem that the aforementioned intrusion phenomenon cannot be detected. Another object of the present invention is to provide a method of inspecting interconnects which is carried out using the test keys of the present invention. The structure of the test key of the present invention includes a continuous metal line and a plurality of conductive plugs thereon. One end of each plug is in contact with a continuous metal line, and at least one of the other ends of the plug is not connected to any of the conductors. In addition, the ends of the continuous metal wire are connected to different voltages. In a preferred embodiment of the present invention, the sides of the continuous metal wire are provided with a square-coated glass (SOG), and the continuous metal wire and the spin-on glass are preferably separated by 6 1267935 16580 twf.d〇c/s soil. 2 younger electric layer. The first electrical layer can be disposed on the continuous metal wire and the spin-on glass, and the conductive plug is located in the second dielectric layer. The top of each of the two bases can be wider than the other portions, and the lower dielectric layer of the top portion is subjected to selective isotropic (four). Continued brother, fish ^ 'The above test button may further include at least two false patterns, which are respectively located, on both sides of the shell 1 line, and each has a distance from the continuous metal line equal to the interconnected line structure and the continuous metal The spacing between two adjacent j layers of the same layer of the line' and the material of the dummy pattern can be the same as the continuous metal line. It is difficult to form a button on the wafer, and the material of the conductive plug includes aluminum. Let the radio plug the plug and the upper metal layer. Wherein, each of the conductive plugs is located on the U: line, and the lower end of each of the conductive plugs and the first-line: ΐ'==. The upper metal layer is located at the first to third continuous gold. Further, the first and second sides are in contact with each other and are in contact with the upper end of each of the conductive plugs. The two ends of the line, the 'to the line, are connected to different voltages. Layer 2: The method of == is formed by forming a continuous metal wire on a stem of a metal wire forming an interconnect, ~ σ; forming an inner plug, and forming a plurality of segments on the continuous metal wire Apply force to both ends of the second line. After the 'fourth electromigration characteristic in the continuous metal, thereby judging the electro-stimulation characteristics of the electromigration of the metal line includes continuous 7 1267935 16580 twf.doc / g. In addition, in a preferred embodiment, the inner connection After the metal layer is formed with the continuous metal wire, more spin-on glass is formed on both sides of the metal layer and the continuous metal wire; and before the spin-on glass is formed, it is preferably on the surface of the metal layer and the continuous metal wire. The first dielectric layer is formed on the surface so as not to be damaged by contact with the raw material of the spin-on glass. Further, after the spin-on glass is formed, a second dielectric layer may be formed on the metal layer, the continuous metal line, and the spin-on glass, and the first and second plugs are formed in the second dielectric layer. In addition, in the above preferred embodiment, the method of forming the first first interposer in the second dielectric layer is, for example, first forming a patterned mask layer on the second dielectric layer, which has a plurality of via holes. Pattern, and then the mask layer is used as a mask
性蝕刻弟二介電層，以在其上形成多個凹洞，然後以同一 罩幕層為罩幕非等向性地⑽第二介電層，以在其中形成 多個介層洞，再於介層洞與凹洞中填入金屬即可。此第二 電層之材質包括氧化石夕，且等向性餘刻可利用b〇e。 另外，在本發明之檢查内連線的方法中，於晶圓切割 迢上形成連續金屬線的同時，更可同時於其兩側形成至少 二假圖案’其各自與連續金屬線之間有—輯，此距離較 佳等於内連線結構巾兩相鄰金制之㈤距 結構的絲。另外，第—與第二插塞之材質則包括銘 —貫施财，本發明之檢查__方法所針對 的内連線結構更包括第-插塞上方的多個第_上金屬層。 此方法係在形成下金屬層之同時，於晶圓_道上形^依 行之Γ、第二與第三連續金屬線。接著， 在开/成弟-插塞之同時，於第—與第三連續金屬線上形成 8 1267935 16580twf.doc/g 多個第二插塞。之後在形成第一上金屬層之同時，於第一 至第三連縯金屬線及第二插塞的上方形成第二上金屬層， 其中第一至第三連續金屬線、第二插塞及與第二上金屬層 係構成一測試鍵。然後，於第二連續金屬線的兩端施加^ 同的電壓，以測量其電致遷移特性，藉此判斷内連線的狀 況。Etching the second dielectric layer to form a plurality of recesses thereon, and then using the same mask layer as a mask to non-isotropically (10) the second dielectric layer to form a plurality of via holes therein, and then Fill the holes and holes with metal. The material of the second electric layer includes oxidized stone, and the isotropic residue can utilize b〇e. In addition, in the method for inspecting the interconnecting wire of the present invention, a continuous metal wire is formed on the wafer cutting crucible, and at least two dummy patterns are formed on both sides thereof at the same time, and between each of the continuous metal wires. In addition, the distance is preferably equal to the wire of the adjacent structure of the inner connecting fabric towel (5). In addition, the materials of the first and second plugs include the inscription, and the inner wiring structure for the inspection method of the present invention further includes a plurality of upper metal layers above the first plug. This method forms the lower, second and third continuous metal lines on the wafer_channel while forming the lower metal layer. Next, a plurality of second plugs of 8 1267935 16580 twf.doc/g are formed on the first and third continuous metal wires at the same time as the open/close-plug. Forming a second upper metal layer over the first to third series metal wires and the second plug, wherein the first to third continuous metal lines, the second plug and Forming a test key with the second upper metal layer. Then, a similar voltage is applied across the second continuous metal line to measure its electromigration characteristics, thereby judging the condition of the interconnect.
±由於本發明之測試鍵包括連續金屬線，且係測量此連 續金屬線之電遷移特性以進行檢查，而非如習知般測量由 上下交替排狀金屬層及減所構成的整伽懷鍵的電遷 移特性，所以當金屬層侵蝕現象發生時，測試鍵的電遷移 特性變化遠較習知者_。，#電路結構與/或製程條 件使得内連線金屬層與連續金屬線被侵⑽，該缺陷即可 明顯地反映在本發明之測試鍵的電遷移特性上。 ▲為毒本發明之上述和其它目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所關式，作詳細說 明如下。 、ϋ 【實施方式】 一 圖3Α為本發明較佳實施例之測試鍵及對應之内連線 結構的剖面圖，圖3Β則為此測試鍵的上視圖。 、 2明較佳實施例之測試鍵與對應之内 =_說明如下。首先，提供具元件請與ί i开晶圓/基底300 ’其中元件區302係元件與内連 隹 切割道304係測試鍵306及其它測試圖案 或對準圖案(未緣示)形成之處。接著在元件區302切 9 I2679ng 成金屬層31〇a’同時在切割道3〇4上形成連續金屬線 3滿’再於基底300上全面形成薄介電層32〇。其中，金 屬層310 a與連續金屬線3】〇 b之材質例如是铭 ’且薄介電 層32〇之材質例如是以化學氣相沉積法(CVD)沉積之無機 介電材料，如CVD-氧化石夕，用以保護金屬層遍與連續 金屬線31〇b免受後續製程中旋塗玻璃原料的破壞。 另外，在形成金屬層3 l〇a與連續金屬線31〇b時，更 可同日守在連續金屬線⑽兩側形成至少二假圖宰31〇c， 如圖3B所示，以模擬元件區如中内連線的實^狀態。 此二假圖案310c例如是與連續金屬線遍同寬之金屬 • 線，且各自與連續金屬線31〇b相隔一段距離。此距離較佳 等於元件區302中兩相鄰金屬層31〇a的間距，以盡可能模 擬内連線結構的狀態。如此，後續填入金屬層3術間隙的 方疋塗玻璃與填入連續金屬線31〇1>假圖案31〇c間隙的旋塗 玻璃即可有相同狀態，例如是有相同的魏產生機率。 然後，於金屬層310a的間隙及連續金屬線31〇b與假 擊目案廳的間隙中填人旋塗玻璃33()，其材質例如是氮石夕 倍半氧烷(HSQ)或曱基矽倍半氧烷(MSQ)，以進行平坦化， 再於310a、310b與旋塗玻璃33〇上形成介電層34〇，一其材 質例如是CVD·氧化石夕。接著於介電層34〇 ±形成具介層 洞圖案的罩幕層（未繪示，但可參考圖2的142)，再進行等 向性㈣，以在it件區搬内的介電層34()上形成凹洞 4a同時在切割道304的介電層340上形成凹洞344b， 其中所使用的蝕刻劑例如是含HF與的B〇E。形成 1267935 16580twf.d〇c/g 凹洞344a/b之目的在於供士入 中填入全>1，M 相頂部的寬度，以便於其 尤其^等覆纽較低的金屬。 件巴幕層為罩幕進行轉向性關，以在元 仵(he 302内的介電層34〇 道3〇4的介電層340上幵=介層洞編，同時在切割 β入爲、π。 乂成；丨層洞346b。然後於凹洞344a/b 302 J ^ 产”私層340中形成與金屬層31〇a連接的插塞3偷， =在巧道304的介電層中形成與連續金屬線憑 、的#基350b，其係與連續金屬線310b構成測試鍵 306。然後’於元件區3G2的介電層遍上形成與插塞聽 連接的金屬層360a，同時於切割道3〇4的介電層34〇上形 成金屬層360b，其係與位在連續金屬線31〇b兩端的插塞 350b連接’以使連續金屬線31〇b能與測試裝置電性連接。 其它的插塞350b則或可如圖示般皆不與任何導體相連，或 是可有數個連接至與金屬圖案36〇a/b同時形成的其它金屬 圖案（未繪示），以便測試插塞35〇a的品質。 在測試元件區302形成之内連線結構時，係於連續金 屬線310b兩端施加不同的電壓Vl與v2以引起電遷移 (EM)，並測量一電遷移特性，其例如是em毀損時間，亦 即在EM現象發生之條件下連續金屬線310b的毀損時間。 當金屬層間隙過小與/或旋塗玻璃330原料的溝填性較差 而令旋塗玻璃330中產生裂縫，致使連續金屬線310b如金 屬層310a般在後續濕蝕刻步驟中被侵蝕產生缺口 312 (圖 3B)時，連續金屬線310b的電遷移毁損時間即會明顯縮 1267935 16580twf.doc/g 短，而可反映出該問題。 另外，圖4為本發明另一較佳實施例之測試鍵的上視 圖。此測试鍵包括連績金屬線41 Ob、位於連續金屬線41 〇b 兩側且與之平行的兩條連續金屬線4i〇a、位於2條連續金 屬線410a上的導電插塞450，以及上金屬層46〇。其中， 上金屬層460位於3條連續金屬線41〇a/b與導電插塞450 上方，每一導電插塞450的下端與連續金屬線41〇a接觸， 上端則與上金屬層460接觸。 同樣地，連續金屬線410a與410b之間隙可填充有旋 塗玻㈣’旋塗玻璃與連續金屬線410a/410b之間可隔有薄 的無機介電層，且導電插塞450可配置於連續金屬線 410a、410b與旋塗玻璃上方的介電層之中。如此在前述擴 大容納導電插塞450之介層洞的頂部的濕蝕刻步驟中，腐 蝕性液體即可能經由貫穿旋塗玻璃與介電層的裂隙而腐蝕 連續金屬線410a與410b，如同前一實施例之情形。 不過’與前一實施例不同的是，在使用此測試鍵測試 内連線時，係將其上未形成密集導電插塞450的連續金屬 線410b的兩端連接至不同的電壓V1與V2。此種測試鍵 的運作原理與圖3B所示之測試鍵306相同，但其對金屬 知:餘現象的靈敏度高於後者。 再者’如欲同步形成圖3A左所示之内連線結構及圖4 之測試鍵，則可令連續金屬線410a、410b與金屬層310a 同時形成，令導電插塞450與導電插塞350a同時形成，並 令上金屬層460與金屬層360a同時形成。 12 1267935 16580twf.doc/g 戈口上尸/ΤΙ% ’ 升、奴％Α埏巴栝連續金屬線，且 係測量此連續金屬線之電遷移特性以進行檢查，所以當前 述侵蝕現象發生時，測試鍵的電遷移特性變化遠較習知測 試鍵更為明顯。因此，當電路結構與/或製程條件使得介電 層產生裂縫，致使内連線金屬層與連續金屬線在後續任何 濕钱刻製程巾被侵糾，關題即可鶴地反映在本發明 之測试鍵的電遷移特性上。 除此之外，雖然在上述較佳實施例巾，本發明之測試 鍵係用以偵測因旋塗玻璃產生裂縫而使内連線之金屬層在 擴大介層洞口的濕蝕刻步驟中被侵蝕 應用卻，於此。當内連線金屬層有可能在== 姓，步驟中因旋塗玻璃或它種介電材料的裂縫而被侵钱， ，疋因其匕緣故而可能在後龜㈣步驟或其它任 :被侵姓時’同樣可以使用本發明的測試鍵來檢查⑽ 开只要在内連線之金屬層有可能遭受魏的情 /以於被舰原因為何，皆可使用本發明之測試鍵 加以祆查，以確認元件的品質。 - 雖然本發明已以較佳實施例揭露如上 限定本發明，任何孰羽 ’、/、1非用以 釦rp^ / 技#者，在不本發明之精神 r鬥可作些許之更動與潤飾’因此本發明之保護 ㈣當視後附之申請專利範圍所界定者為準。 料 【圖式簡單說明】 圖1繪：習知測試鍵及對應之内連線結構的一例。 圖2緣示内連線之金屬層因旋塗玻璃中的裂縫而在後 13 1267935 16580twf.doc/g 續濕蝕刻步驟中被侵钱的情形。 圖3A為本發明較佳實施例之測試鍵及對應之内、、 結構的剖面圖，圖3B則為此測試鍵的上視圖。 連線 圖4為本發明另一較佳實施例之測試鍵的上視圖。 【主要元件符號說明】 100、300 :基底 102、302 :元件區 104、304 :切割道 106、306、406 :測試鍵 • ll〇a、310a :内連線的金屬層 110b、310b、410a、410b :連續金屬線 120、140、320、340 :介電層 130、330 :旋塗玻璃 133 :裂縫 142 :罩幕層 144a/344a、144b/344b :凹洞 • 146a/346a、146b/346b :介層洞 150a/350a、150b/350b、450 :導電插塞 160a/360a、160b/360b、460 :金屬層 310c :假圖案 14± Since the test key of the present invention includes a continuous metal wire and measures the electromigration characteristics of the continuous metal wire for inspection, instead of measuring the entire gamma key composed of alternating upper and lower metal layers and subtraction as is conventionally known The electromigration characteristics, so when the metal layer erosion phenomenon occurs, the electromigration characteristics of the test key change much more than the conventional one. The circuit structure and/or process conditions cause the interconnect metal layer and the continuous metal line to be invaded (10), and the defect can be clearly reflected in the electromigration characteristics of the test key of the present invention. The above and other objects, features and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment] FIG. 3A is a cross-sectional view showing a test key and a corresponding interconnect structure according to a preferred embodiment of the present invention, and FIG. 3 is a top view of the test key. 2, the test key of the preferred embodiment and the corresponding =_ are described below. First, the component is provided with the wafer/substrate 300' where the component region 302 component and the interconnect 隹 scribe 304 test button 306 and other test patterns or alignment patterns (not shown). Next, I 2679 ng is formed in the element region 302 to form a metal layer 31 〇 a' while a continuous metal line 3 is formed on the scribe line 3 〇 4 and a thin dielectric layer 32 全面 is formed on the substrate 300. The material of the metal layer 310 a and the continuous metal line 3 〇 b is, for example, the material of the thin dielectric layer 32 , for example, an inorganic dielectric material deposited by chemical vapor deposition (CVD), such as CVD- The oxidized stone is used to protect the metal layer from the continuous metal wire 31〇b from the destruction of the spin-on glass material in the subsequent process. In addition, when the metal layer 3 l〇a and the continuous metal line 31〇b are formed, at least two dummy patterns 31〇c can be formed on both sides of the continuous metal line (10), as shown in FIG. 3B, to simulate the element region. Such as the real ^ state of the inner connection. The two dummy patterns 310c are, for example, metal lines which are the same width as the continuous metal lines, and are each spaced apart from the continuous metal lines 31〇b. This distance is preferably equal to the spacing of two adjacent metal layers 31a in the element region 302 to simulate the state of the interconnect structure as much as possible. Thus, the spin-on glass which is subsequently filled in the gap between the metal layer 3 and the glass coated with the continuous metal wire 31〇1> the dummy pattern 31〇c can have the same state, for example, having the same Wei generation probability. Then, the spin-on glass 33 () is filled in the gap of the metal layer 310a and the gap between the continuous metal wire 31〇b and the fake eyepiece hall, and the material thereof is, for example, a nitrogen sulfosyl heptane (HSQ) or a sulfhydryl group. The sesquisesquioxane (MSQ) is planarized, and a dielectric layer 34 is formed on the spin-on glass 33A at 310a, 310b, and the material thereof is, for example, CVD·Oxide. Then, a mask layer having a via pattern is formed on the dielectric layer 34 (not shown, but reference may be made to 142 of FIG. 2), and then isotropic (4) is performed to move the dielectric layer in the element region. A recess 4a is formed in 34() while forming a recess 344b on the dielectric layer 340 of the dicing street 304, wherein the etchant used is, for example, B 〇 E containing HF and HF. The purpose of forming the 1267935 16580 twf.d〇c/g cavity 344a/b is to fill the width of the top of the full >1, M phase in the donor, so that it can especially be used to cover the lower metal. The slab layer is steered for the mask to be used in the dielectric layer 340 of the dielectric layer 34 in the heat 302. π. 乂 丨 丨 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 346 Forming a continuous metal wire with a #350b, which is connected to the continuous metal wire 310b to form a test key 306. Then, a metal layer 360a that is connected to the plug is formed over the dielectric layer of the component region 3G2, while cutting A dielectric layer 360b is formed on the dielectric layer 34 of the via 3, which is connected to the plug 350b positioned at both ends of the continuous metal line 31〇b so that the continuous metal line 31〇b can be electrically connected to the test device. The other plugs 350b may not be connected to any of the conductors as shown, or may have several other metal patterns (not shown) connected to the metal pattern 36〇a/b for testing the plugs. The quality of 35 〇a. When the inner structure of the test element region 302 is formed, a different voltage V1 is applied across the continuous metal line 310b. V2 to cause electromigration (EM), and to measure an electromigration characteristic, which is, for example, an em destruction time, that is, a damage time of the continuous metal line 310b under the condition that the EM phenomenon occurs. When the metal layer gap is too small and/or spin-coated The glass 330 raw material has poor groove filling property and causes cracks in the spin-on glass 330, so that the continuous metal wire 310b is eroded in the subsequent wet etching step like the metal layer 310a to form the notch 312 (Fig. 3B), the continuous metal wire 310b The electromigration damage time is obviously shortened by 1267935 16580 twf.doc/g, which can reflect the problem. In addition, Fig. 4 is a top view of a test key according to another preferred embodiment of the present invention. The metal line 41 Ob, two continuous metal lines 4i〇a on both sides of the continuous metal line 41 〇b and parallel thereto, a conductive plug 450 on the two continuous metal lines 410a, and an upper metal layer 46〇. The upper metal layer 460 is located above the three continuous metal wires 41〇a/b and the conductive plug 450. The lower end of each conductive plug 450 is in contact with the continuous metal wire 41〇a, and the upper end is in contact with the upper metal layer 460. Ground, continuous metal lines 410a and 4 The gap of 10b may be filled with spin-on glass (4) 'a thin inorganic dielectric layer may be interposed between the spin-on glass and the continuous metal line 410a/410b, and the conductive plug 450 may be disposed on the continuous metal lines 410a, 410b and spin-coated In the dielectric layer above the glass, in the wet etching step of expanding the top of the via hole accommodating the conductive plug 450, the corrosive liquid may corrode the continuous metal through the crack of the spin coating glass and the dielectric layer. Lines 410a and 410b are as in the previous embodiment. However, unlike the previous embodiment, when the test leads are used to test the interconnect, the two ends of the continuous metal line 410b on which the dense conductive plug 450 is not formed are connected to different voltages V1 and V2. The operation of this test button is the same as that of the test button 306 shown in Figure 3B, but it is more sensitive to metal than the latter. Furthermore, if the inner wiring structure shown in the left of FIG. 3A and the test key of FIG. 4 are synchronously formed, the continuous metal wires 410a and 410b and the metal layer 310a can be simultaneously formed, and the conductive plug 450 and the conductive plug 350a are formed. At the same time, the upper metal layer 460 is formed simultaneously with the metal layer 360a. 12 1267935 16580twf.doc/g 上口上尸/ΤΙ% ' 升, 奴%Α埏巴栝 continuous metal wire, and measuring the electromigration characteristics of this continuous metal wire for inspection, so when the aforementioned erosion phenomenon occurs, test The electromigration characteristics of the bond change much more clearly than the conventional test keys. Therefore, when the circuit structure and/or the process conditions cause cracks in the dielectric layer, causing the interconnect metal layer and the continuous metal line to be invaded in any subsequent wet money engraving process towel, the problem can be reflected in the present invention. Test the electromigration characteristics of the keys. In addition, although in the above preferred embodiment, the test key of the present invention is used to detect cracks in the spin-on glass to cause the metal layer of the interconnect to be eroded in the wet etching step of expanding the via hole. The application is here. When the inner metal layer is likely to be invaded by the spin-coated glass or cracks of its dielectric material in the step of == surname, it may be in the hind turtle (four) step or other: When invading the surname, you can also use the test button of the present invention to check (10). As long as the metal layer of the interconnect is likely to suffer from Wei/cause, the test button of the present invention can be used for inspection. To confirm the quality of the components. - Although the present invention has been disclosed in the preferred embodiments as defined above, any of the feathers ', /, 1 is not used to buckle rp ^ / technology #, in the spirit of the invention can be used to make some changes and retouching 'Therefore, the protection of the present invention (4) is subject to the definition of the scope of the patent application. [Simplified description of the drawings] Fig. 1 depicts an example of a conventional test button and a corresponding interconnect structure. Fig. 2 shows the case where the metal layer of the interconnect is invaded by the crack in the spin-coated glass in the subsequent wet etching step in the subsequent 13 1267935 16580 twf.doc/g. 3A is a cross-sectional view showing a test key and a corresponding inner and outer structure of the preferred embodiment of the present invention, and FIG. 3B is a top view of the test key. Connection Figure 4 is a top plan view of a test button in accordance with another preferred embodiment of the present invention. [Main component symbol description] 100, 300: substrate 102, 302: element region 104, 304: dicing streets 106, 306, 406: test key • ll〇a, 310a: interconnected metal layers 110b, 310b, 410a, 410b: continuous metal lines 120, 140, 320, 340: dielectric layers 130, 330: spin-on glass 133: cracks 142: mask layers 144a/344a, 144b/344b: recesses 146a/346a, 146b/346b: Vias 150a/350a, 150b/350b, 450: conductive plugs 160a/360a, 160b/360b, 460: metal layer 310c: dummy pattern 14