TWI266218B - Interface control circuit and related method thereof - Google Patents

Interface control circuit and related method thereof

Info

Publication number
TWI266218B
TWI266218B TW092128001A TW92128001A TWI266218B TW I266218 B TWI266218 B TW I266218B TW 092128001 A TW092128001 A TW 092128001A TW 92128001 A TW92128001 A TW 92128001A TW I266218 B TWI266218 B TW I266218B
Authority
TW
Taiwan
Prior art keywords
control circuit
predetermined number
interface control
predetermined
inputting
Prior art date
Application number
TW092128001A
Other languages
English (en)
Other versions
TW200513938A (en
Inventor
Hui-Huang Chang
Original Assignee
Realtek Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Realtek Semiconductor Corp filed Critical Realtek Semiconductor Corp
Priority to TW092128001A priority Critical patent/TWI266218B/zh
Priority to US10/710,889 priority patent/US20050078710A1/en
Priority to JP2004254377A priority patent/JP2005115924A/ja
Publication of TW200513938A publication Critical patent/TW200513938A/zh
Application granted granted Critical
Publication of TWI266218B publication Critical patent/TWI266218B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Control Of Stepping Motors (AREA)
  • Dc Digital Transmission (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Programmable Controllers (AREA)
  • Logic Circuits (AREA)
TW092128001A 2003-10-08 2003-10-08 Interface control circuit and related method thereof TWI266218B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW092128001A TWI266218B (en) 2003-10-08 2003-10-08 Interface control circuit and related method thereof
US10/710,889 US20050078710A1 (en) 2003-10-08 2004-08-11 General interface control circuit
JP2004254377A JP2005115924A (ja) 2003-10-08 2004-09-01 インターフェイス回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092128001A TWI266218B (en) 2003-10-08 2003-10-08 Interface control circuit and related method thereof

Publications (2)

Publication Number Publication Date
TW200513938A TW200513938A (en) 2005-04-16
TWI266218B true TWI266218B (en) 2006-11-11

Family

ID=34421008

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092128001A TWI266218B (en) 2003-10-08 2003-10-08 Interface control circuit and related method thereof

Country Status (3)

Country Link
US (1) US20050078710A1 (zh)
JP (1) JP2005115924A (zh)
TW (1) TWI266218B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2801915B1 (de) * 2013-05-10 2017-01-18 dSPACE digital signal processing and control engineering GmbH Adaptives interface zur kopplung von fpga-modulen

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4222103A (en) * 1978-09-25 1980-09-09 Motorola, Inc. Real time capture registers for data processor
US5701514A (en) * 1994-04-01 1997-12-23 International Business Machines Corporation System providing user definable selection of different data transmission modes of drivers of an I/O controller transmitting to peripherals with different data transmission rate
US5727170A (en) * 1994-12-29 1998-03-10 Siemens Energy & Automation, Inc. User defined port and protocol scheme for a programmable logic controller
US6038400A (en) * 1995-09-27 2000-03-14 Linear Technology Corporation Self-configuring interface circuitry, including circuitry for identifying a protocol used to send signals to the interface circuitry, and circuitry for receiving the signals using the identified protocol
US6138177A (en) * 1996-12-31 2000-10-24 Opti Inc. System and method of pin programming and configuration
US6026453A (en) * 1997-07-15 2000-02-15 International Business Machines Corporation System for facilitating serial data communications utilizing number of cycles input signal remained asserted to indicate data output logical state
US6088754A (en) * 1997-12-31 2000-07-11 Cisco Technology, Inc. Generic serial interface with automatic reconfigurability
US6289409B1 (en) * 1998-08-25 2001-09-11 Infineon Technologies North America Corp. Microcontroller with flexible interface to external devices

Also Published As

Publication number Publication date
TW200513938A (en) 2005-04-16
US20050078710A1 (en) 2005-04-14
JP2005115924A (ja) 2005-04-28

Similar Documents

Publication Publication Date Title
GB2403826B (en) Voltage margin testing under BMC control
HK1083657A1 (en) Method and apparatus for shuffling data
AU2003250755A8 (en) Circuit arrangement for generating an iq signal
WO2001057627A3 (en) Circuits, systems and methods for information privatization in personal electronic appliances
HK1056780A1 (en) Electronic device, reception control method for anelectronic device, and reception control program for an electronic device
GB0228642D0 (en) An electrical machine
EP1533906A4 (en) WAVEFORM GENERATION PROCESS, WAVEFORM GENERATION PROGRAM, WAVEFORM GENERATION CIRCUIT AND RADAR EQUIPMENT
DE502005010565D1 (zh)
GB2391370B (en) Control apparatus for computer
TWI266218B (en) Interface control circuit and related method thereof
TWI341461B (en) Programmable delay cell and a controller, a printed circuit board and a computer apparatus having the same, methods for using the same and an article holding instructions for testing timing of signals between a controller and a devices
AU2002366270A8 (en) Fast path for performing data operations
AU154270S (en) An electronic computer
TW200502960A (en) Retrieving data stored in a magnetic integrated memory
TWI256539B (en) Apparatus and method for generating a clock signal
EP1620857A4 (en) MEMORY REDUNDANCY ACTIVATED DURING THE TEST
HUP0302146A3 (en) Plug in unit, chiefly a lightning-arrester, an apparatus with this one and method for making this apparatus
AU156864S (en) An electronic computer
GB0017889D0 (en) A circuit for simulating an impedance
AU2003289811A1 (en) Method for recognizing errors during the cryptographic transformation of binary data, and associated circuit arrangement
AU2003277293A1 (en) Method for designing minimal cost, timing correct hardware during circuit synthesis
AU156863S (en) An electronic computer
TW200512469A (en) Circuitry and method of a IC having the simulative trimming
TW200519599A (en) Computer device and conversion method converting AGP interface into PCI interface
WO2005006194A3 (en) Efficient memory controller

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent