AU2003289811A1 - Method for recognizing errors during the cryptographic transformation of binary data, and associated circuit arrangement - Google Patents

Method for recognizing errors during the cryptographic transformation of binary data, and associated circuit arrangement

Info

Publication number
AU2003289811A1
AU2003289811A1 AU2003289811A AU2003289811A AU2003289811A1 AU 2003289811 A1 AU2003289811 A1 AU 2003289811A1 AU 2003289811 A AU2003289811 A AU 2003289811A AU 2003289811 A AU2003289811 A AU 2003289811A AU 2003289811 A1 AU2003289811 A1 AU 2003289811A1
Authority
AU
Australia
Prior art keywords
circuit arrangement
binary data
errors during
associated circuit
cryptographic transformation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003289811A
Inventor
Michael Gossel
Ramesh Karri
Grigori Kouznetsov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universitaet Postdam
Original Assignee
Universitaet Postdam
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universitaet Postdam filed Critical Universitaet Postdam
Publication of AU2003289811A1 publication Critical patent/AU2003289811A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/004—Countermeasures against attacks on cryptographic mechanisms for fault attacks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
AU2003289811A 2002-12-19 2003-11-27 Method for recognizing errors during the cryptographic transformation of binary data, and associated circuit arrangement Abandoned AU2003289811A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE2002161810 DE10261810B4 (en) 2002-12-19 2002-12-19 Error detection method for cryptographic transformation of binary data and circuit arrangement
DE10261810.0 2002-12-19
PCT/DE2003/003931 WO2004057794A1 (en) 2002-12-19 2003-11-27 Method for recognizing errors during the cryptographic transformation of binary data, and associated circuit arrangement

Publications (1)

Publication Number Publication Date
AU2003289811A1 true AU2003289811A1 (en) 2004-07-14

Family

ID=32478132

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003289811A Abandoned AU2003289811A1 (en) 2002-12-19 2003-11-27 Method for recognizing errors during the cryptographic transformation of binary data, and associated circuit arrangement

Country Status (3)

Country Link
AU (1) AU2003289811A1 (en)
DE (1) DE10261810B4 (en)
WO (1) WO2004057794A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004043480B3 (en) 2004-09-08 2005-12-29 Infineon Technologies Ag Apparatus and method for detecting a failure of a cryptographic unit, preferably the AES algorithm
DE102004062825B4 (en) 2004-12-27 2006-11-23 Infineon Technologies Ag Cryptographic unit and method for operating a cryptographic unit
US9646175B2 (en) * 2014-11-26 2017-05-09 Synopsys, Inc. Two-way parity error detection for advanced encryption standard engines
CN112118097B (en) * 2020-09-07 2021-10-08 昆明理工大学 Symmetric key encryption method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365591A (en) * 1993-10-29 1994-11-15 Motorola, Inc. Secure cryptographic logic arrangement
US5432848A (en) * 1994-04-15 1995-07-11 International Business Machines Corporation DES encryption and decryption unit with error checking

Also Published As

Publication number Publication date
WO2004057794A1 (en) 2004-07-08
DE10261810B4 (en) 2004-12-23
WO2004057794B1 (en) 2004-09-02
DE10261810A1 (en) 2004-07-08

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase