1264554 九、發明說明： 【發明所屬之技術領域】 月疋種積體電路测試承座接地型結構，特別指 :種—包含積體電路測試、高速PCB設計、PCB製作、加: 機精在製程等領域的積體電路測試承座。 【先前技術】 以現有技術而言，以往像QFN或QFP封裝且中間為 接地片之積體電路，其職承座在積體電路接地片部分我 們都是用幾個彈簧探針（p卿ριη)或不同結構之探針做 A號，丨面’其結構較為複雜，成本較高，且測試結果具有 較高的雜訊。 如圖-所示’封裝後的積體電路結構四周為訊號接 腳’中間有一塊接地片，典型_封裝就是屬於此種結 構。而傳統的封裝龍電路測試承座均採用如圖二所开之 設計，在巾間龍電路接地片區域㈣幾㈣簣針或各種 結構採針做訊號介面’此種介面方式因接地探針之寄生電 感效應會使得接地準位受_訊影響，即利『接地彈跳』 (Ground Bounce);另一古；π m lL ★ 4 力方面採用此架構之成本會較高， 因為適用於高頻訊號的探針其價位並不低，-整塊接地片 需要使用許多這樣的探針，造成成本負擔。 此可見’上述的習用方式顯然尚有諸多的缺失，實 非一良善的設計，而亟待加以改良。 1264554 本發明的全新架構，係將這部分的訊號介面改以一 .塊印刷電路板取代，不僅可以節省成本，且從實際測試我1264554 IX. Description of the invention: [Technical field of invention] Lunar seeding circuit test socket grounding structure, especially: species - including integrated circuit test, high speed PCB design, PCB fabrication, plus: Integrated circuit test sockets in the field of process and other fields. [Prior Art] In the prior art, in the past, an integrated circuit such as a QFN or QFP package with a grounding strip in the middle, the main bearing is used in the grounding piece of the integrated circuit. We use several spring probes. ) or probes of different structures do A number, the surface of the surface is more complicated, the cost is higher, and the test results have higher noise. As shown in the figure - the packaged circuit structure is surrounded by a grounding strip in the middle of the signal connector. The typical package is such a structure. The traditional packaged dragon circuit test sockets are designed as shown in Figure 2. In the area of the ground circuit between the two sides of the towel, (four) several (four) needles or various structures, the needle is used as the signal interface. The parasitic inductance effect will cause the grounding level to be affected by the signal, that is, the "Ground Bounce"; another ancient; π m lL ★ 4 The cost of using this architecture will be higher because it is suitable for high frequency signals. The price of the probe is not low, and the whole piece of grounding strip requires the use of many such probes, resulting in a cost burden. It can be seen that the above-mentioned methods of use obviously have many shortcomings, which are not a good design and need to be improved. 1264554 The new architecture of the present invention replaces this part of the signal interface with a block printed circuit board, which not only saves cost, but also tests me from the actual
們得到接地雜訊的改善，進而提昇積體電路剛試+良'率\ 【發明内容】 V 本發明的主要目的是提供一種積體電路測試承座接地 型結構，吁廣泛應用於封裝後積體電路測試領域。 • 本發明的另一目的是提供一種積體電路測試承座接地 參型結構，將測試承座接地信號部分作些許改良，成為一兼顧 成本及信號完整性之完整產品。 可測試承座為介於Load Board(測試承載板）與積體電路 間’用來測試積體電路功能好土裏’為積體電路測試分析不可 〆、之元件和體電路測试承座的電氣特性會影響測試的会士 果，尤其是當積體電路頻率越來越高，測試承座所產生之寄 •電感及電容所造成電氣特性影響越來越大，造成積體電路 測試瓶頸。經由本發明實作，將傳統用幾個彈簧探針或不同 _結構之探針做訊號介面改以一塊印刷電路板取代，提昇 體電路測試良率。 、 本發明具備高頻積體電路測試承座設計及信號分析技 術’技術内容如下： (Π高速電路設計。 (2) 高頻積體電路測試承座設計技術。 (3) 咼頻積體電路測試承座電氣特性萃取技術。 6 1264554 (4)印刷電路板製作技術。高頻量測技術 【實施方式】 如圖三所示，其說明一種典型積體電路測試方塊示 意圖，圖四為該積體電路測試簡化剖面圖。當測試時測試 機台12中的之測試頻道n可發送一數位或類比訊號，透 過彈黃探針1 〇、測試承載板08、測試承座〇4, 〇6 ，將We get the improvement of grounding noise, and then improve the integrated circuit test + good 'rate'. [Inventive content] V The main purpose of the present invention is to provide an integrated circuit test socket grounding type structure, which is widely used in package post-products. Field circuit testing field. • Another object of the present invention is to provide an integrated circuit test socket grounding reference structure that provides a slight improvement in the grounding signal portion of the test socket to become a complete product that combines cost and signal integrity. The testable seat is between the Load Board and the integrated circuit. It is used to test the function of the integrated circuit. It is an indispensable component and body circuit test socket for the integrated circuit test. The electrical characteristics will affect the tester's fruit, especially when the integrated circuit frequency is getting higher and higher, the electrical characteristics of the inductors and capacitors generated by the test socket are more and more affected, resulting in the bottleneck of the integrated circuit test. Through the practice of the present invention, a conventional spring probe or a different _ structure probe is used as a signal interface instead of a printed circuit board to improve the body circuit test yield. The invention has the high-frequency integrated circuit test socket design and signal analysis technology' technical content as follows: (Π high-speed circuit design. (2) high-frequency integrated circuit test socket design technology. (3) 咼 frequency integrated circuit Test socket electrical characteristics extraction technology. 6 1264554 (4) Printed circuit board fabrication technology. High-frequency measurement technology [Embodiment] As shown in Figure 3, it illustrates a typical integrated circuit test block diagram, Figure 4 shows the product. The body circuit test simplifies the cross-sectional view. When testing, the test channel n in the test machine 12 can send a digital or analog signal through the yellow probe 1 〇, the test carrier 08, the test socket 4, 〇 6, will
送出之數位或類比訊號，透過相同 藉由測試機台1 2的電腦121與處 理然後產生測試報告。The digital or analog signal sent is sent through the same computer 121 of the test machine 12 and processed to generate a test report.
訊號送至待測之積體電路01，或接收由待測積體電路W 路徑送回測試機台12， 理模組122進行訊號處 圖五為本發明相關結構圖，其中我們將圖二測試承 座切割為承座主體、接地印刷電路板、測試探針等二部 分，亦為本發明測試承座改良後之整體結構；此種架構將 介面訊號之探針改由一塊印刷電路板取代，其優點如下：· * ⑴降低成本。 (2) 汛唬介面由幾個點變為個面，接觸面的增加可有 效降低接觸阻抗。 (3) 降低接地路徑等效電感，可大幅降低整個接地面 雜訊之干擾，即改善接地彈跳問題。 此改良式架構内之印刷電路板設計我們需運用到高 速PCB設計之『電源完整性分析』技術，亦即在製作此印 刷電路板前我們須先做訊號模擬，圖六為當接㈣刷電路 7 1264554 板設計不良時’在接地面 主U义 、振抵式產生，在圖六郝侗 表列則五個模態的共振頻率， 在，我們 66 it ^ J± · 5 7 G Η z，在此所謂 的，、振表不當待測積體電 時，在這之#作頻率剛好是共振頻率 私相余., 钔，白'面之電壓準位就會有擾 ，使得接地平面之電壓準 卽所-^ > 位非良好的芩考零電位， 即所明接地雜訊，如圖七所示。 為了避免上述接地雜訊問題， f 丄 我們適當設計印刷電路 、 α八所不，亚糟由電源完整性分析，我 們可以將此結構之印刷電路板 ^ 個共振頻率提升至 1二Η:以上，這也表示當積體電路之測試頻率低於H)GHz 咖結構並不會有接地雜訊問題，圖九為適當設計接地 貫孔後列出前五個模態的共振頻率。 前面圖九提到適當設計接地貫孔可將共振頻率提升 至1 OGHz以上，這只菩便^αα , 勺一個茶考設計，變更接/地貫 孔設計可能會有更佳的D fThe signal is sent to the integrated circuit 01 to be tested, or received by the integrated circuit W path to be sent back to the test machine 12, and the control module 122 performs signal processing. Figure 5 is a related structural diagram of the present invention, wherein we will test Figure 2 The socket is cut into two parts: the base of the socket, the grounded printed circuit board and the test probe. It is also the improved overall structure of the test socket of the present invention; this structure replaces the probe of the interface signal with a printed circuit board. The advantages are as follows: · * (1) Reduce costs. (2) The interface is changed from several points to a single surface, and the increase of the contact surface can effectively reduce the contact impedance. (3) Reducing the equivalent inductance of the ground path can greatly reduce the noise of the entire ground plane noise, that is, improve the ground bounce problem. The printed circuit board design in this improved architecture requires the use of "power integrity analysis" technology for high-speed PCB design. That is, we must first perform signal simulation before making this printed circuit board. Figure 6 is the connection (four) brush circuit 7 1264554 When the design of the board is bad, 'the main U sense and the vibrating type are generated on the ground plane. In the figure of the six Hao Hao, the resonance frequency of the five modes is in, we 66 it ^ J± · 5 7 G Η z, in This so-called, when the vibrating table is not suitable for measuring the body electric power, the frequency in this is just the resonance frequency private phase. The voltage level of the ', 白' surface will be disturbed, so that the voltage of the ground plane is accurate. The location -^ > bit is not a good reference zero potential, that is, the grounding noise, as shown in Figure 7. In order to avoid the above ground noise problem, f 丄 we design the printed circuit properly, α 所 不, sub-matter by power integrity analysis, we can increase the resonant frequency of the printed circuit board of this structure to 1 Η: above, This also means that when the test frequency of the integrated circuit is lower than H) GHz, there is no ground noise problem. Figure 9 shows the resonant frequencies of the first five modes after properly designing the grounding via. Figure 9 above shows that the proper design of the grounding through-hole can increase the resonance frequency to above 1 OGHz. This is only a bogey ^αα, a tea test design, and the design of the change/ground hole design may have a better D f
Periormance，但可能必須考量印 刷電路板縱橫比（Aspect μ ^ & Ρ Ct Katl0)的限制，故實際上的設計 需要同時滿足訊號品質要束及制妒μ从 貝赘水及I私上的配合。製作完成後 我們可設計量測治具’利用高頻量測設備如網路分析儀來 量測此測試承座，量測結果可驗證測試承座電氣特性的好 壞及萃取它的之電性模型（Spice M〇del)。 上列詳細說明係針對本發明之一可行實施例之具體 說明，惟該實施例並非用以限制本發明之專利範圍，1未 8 1264554 之等效實施或變更，均應包含於 综上所述，本案不但 脫離本發明技藝精神所為 本案之專利範圍中uPeriormance, but it may be necessary to consider the limitations of the printed circuit board aspect ratio (Aspect μ ^ & Ρ Ct Katl0), so the actual design needs to meet both the signal quality and the 妒μ from Bellow and I private cooperation. . After the production is completed, we can design the measuring fixture to measure the test socket by using a high-frequency measuring device such as a network analyzer. The measurement result can verify the electrical characteristics of the test socket and the electrical properties of the test socket. Model (Spice M〇del). The detailed description above is a detailed description of one of the possible embodiments of the present invention, but the embodiment is not intended to limit the scope of the invention, and the equivalent implementation or modification of 1 to 8 1264554 should be included in the above description. This case is not only in the scope of the patent of the present invention, but not from the spirit of the present invention.
術芯涊上雏屬剧新，並能較 應已充分符合新穎性及進步 法提出申請’懇請貴局核 ，【圖式簡單說明】 畚圖-、為封裝後積體電路結構圖； 圖二、為封裝後積體電路測試承座； 圖三、為封裝後積體電路測試方塊示意圖； 圖四、為積體電路測試簡化剖面圖； 圖五、為封裝後積體電路測試承座結構示意圖； 圖，、、為接地印刷電路板設計不良時所產生之共 意圖； _ 口 圖七、為當接地印刷電路板產生共振頻率時所造成之接地 、雜訊示意圖； 〜圖八、為適當設計印刷電路板之接地貫孔示意圖； 圖九、與圖六比較共振頻率移至較高頻率示意圖。 【主要元件符號說明】 01 待測之積體電路； 02 積體電路封裝後訊號墊片； 03積體電路封裝後中間接地塊狀墊片，· 1264554 • 04 積體電路測試承座主結構； 05 固定螺絲； 06 接地印刷電路板； 07 做為測試承座與測試承載板訊號介接之彈簧針或各 種結構探針； 0 8 積體電路測試承載板（L 〇 a d B 〇 a r d)， 1 0 9 積體電路測試承載板錫墊； • 10 積體電路測試機台彈簧式探針； 11 測試頻道； 12 積體電路測試機台； 121 電腦； 12 2 處理模組。The core of the core is a new drama, and it can be applied in accordance with the novelty and the progressive law. 'Please ask your bureau to verify the core. [Simplified illustration] 畚图-, the package structure diagram after encapsulation; For the packaged integrated circuit test socket; Figure 3, is the block diagram of the integrated circuit test after packaging; Figure 4, simplified sectional view for the integrated circuit test; Figure 5, the package structure of the integrated circuit test package after packaging Figure, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Schematic diagram of the grounding through hole of the printed circuit board; Figure IX, and Figure 6 compare the resonant frequency to a higher frequency. [Main component symbol description] 01 Integrated circuit to be tested; 02 Signal pad after integrated circuit package; 03 Intermediate ground block gasket after integrated circuit package, · 1264554 • 04 Integrated circuit test socket main structure; 05 Fixing screw; 06 Grounding printed circuit board; 07 As a spring pin or various structure probes for testing the test socket and test carrier board signal; 0 8 Integrated circuit test carrier board (L 〇ad B 〇ard), 1 0 9 Integrated circuit test carrier board tin pad; • 10 integrated circuit test machine spring type probe; 11 test channel; 12 integrated circuit test machine; 121 computer; 12 2 processing module.